1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCIe host controller driver for NWL PCIe Bridge
4  * Based on pcie-xilinx.c, pci-tegra.c
5  *
6  * (C) Copyright 2014 - 2015, Xilinx, Inc.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of_address.h>
18 #include <linux/of_pci.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_irq.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ecam.h>
23 #include <linux/platform_device.h>
24 #include <linux/irqchip/chained_irq.h>
25 
26 #include "../pci.h"
27 
28 /* Bridge core config registers */
29 #define BRCFG_PCIE_RX0			0x00000000
30 #define BRCFG_PCIE_RX1			0x00000004
31 #define BRCFG_INTERRUPT			0x00000010
32 #define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
33 
34 /* Egress - Bridge translation registers */
35 #define E_BREG_CAPABILITIES		0x00000200
36 #define E_BREG_CONTROL			0x00000208
37 #define E_BREG_BASE_LO			0x00000210
38 #define E_BREG_BASE_HI			0x00000214
39 #define E_ECAM_CAPABILITIES		0x00000220
40 #define E_ECAM_CONTROL			0x00000228
41 #define E_ECAM_BASE_LO			0x00000230
42 #define E_ECAM_BASE_HI			0x00000234
43 
44 /* Ingress - address translations */
45 #define I_MSII_CAPABILITIES		0x00000300
46 #define I_MSII_CONTROL			0x00000308
47 #define I_MSII_BASE_LO			0x00000310
48 #define I_MSII_BASE_HI			0x00000314
49 
50 #define I_ISUB_CONTROL			0x000003E8
51 #define SET_ISUB_CONTROL		BIT(0)
52 /* Rxed msg fifo  - Interrupt status registers */
53 #define MSGF_MISC_STATUS		0x00000400
54 #define MSGF_MISC_MASK			0x00000404
55 #define MSGF_LEG_STATUS			0x00000420
56 #define MSGF_LEG_MASK			0x00000424
57 #define MSGF_MSI_STATUS_LO		0x00000440
58 #define MSGF_MSI_STATUS_HI		0x00000444
59 #define MSGF_MSI_MASK_LO		0x00000448
60 #define MSGF_MSI_MASK_HI		0x0000044C
61 
62 /* Msg filter mask bits */
63 #define CFG_ENABLE_PM_MSG_FWD		BIT(1)
64 #define CFG_ENABLE_INT_MSG_FWD		BIT(2)
65 #define CFG_ENABLE_ERR_MSG_FWD		BIT(3)
66 #define CFG_ENABLE_MSG_FILTER_MASK	(CFG_ENABLE_PM_MSG_FWD | \
67 					CFG_ENABLE_INT_MSG_FWD | \
68 					CFG_ENABLE_ERR_MSG_FWD)
69 
70 /* Misc interrupt status mask bits */
71 #define MSGF_MISC_SR_RXMSG_AVAIL	BIT(0)
72 #define MSGF_MISC_SR_RXMSG_OVER		BIT(1)
73 #define MSGF_MISC_SR_SLAVE_ERR		BIT(4)
74 #define MSGF_MISC_SR_MASTER_ERR		BIT(5)
75 #define MSGF_MISC_SR_I_ADDR_ERR		BIT(6)
76 #define MSGF_MISC_SR_E_ADDR_ERR		BIT(7)
77 #define MSGF_MISC_SR_FATAL_AER		BIT(16)
78 #define MSGF_MISC_SR_NON_FATAL_AER	BIT(17)
79 #define MSGF_MISC_SR_CORR_AER		BIT(18)
80 #define MSGF_MISC_SR_UR_DETECT		BIT(20)
81 #define MSGF_MISC_SR_NON_FATAL_DEV	BIT(22)
82 #define MSGF_MISC_SR_FATAL_DEV		BIT(23)
83 #define MSGF_MISC_SR_LINK_DOWN		BIT(24)
84 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH	BIT(25)
85 #define MSGF_MSIC_SR_LINK_BWIDTH	BIT(26)
86 
87 #define MSGF_MISC_SR_MASKALL		(MSGF_MISC_SR_RXMSG_AVAIL | \
88 					MSGF_MISC_SR_RXMSG_OVER | \
89 					MSGF_MISC_SR_SLAVE_ERR | \
90 					MSGF_MISC_SR_MASTER_ERR | \
91 					MSGF_MISC_SR_I_ADDR_ERR | \
92 					MSGF_MISC_SR_E_ADDR_ERR | \
93 					MSGF_MISC_SR_FATAL_AER | \
94 					MSGF_MISC_SR_NON_FATAL_AER | \
95 					MSGF_MISC_SR_CORR_AER | \
96 					MSGF_MISC_SR_UR_DETECT | \
97 					MSGF_MISC_SR_NON_FATAL_DEV | \
98 					MSGF_MISC_SR_FATAL_DEV | \
99 					MSGF_MISC_SR_LINK_DOWN | \
100 					MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
101 					MSGF_MSIC_SR_LINK_BWIDTH)
102 
103 /* Legacy interrupt status mask bits */
104 #define MSGF_LEG_SR_INTA		BIT(0)
105 #define MSGF_LEG_SR_INTB		BIT(1)
106 #define MSGF_LEG_SR_INTC		BIT(2)
107 #define MSGF_LEG_SR_INTD		BIT(3)
108 #define MSGF_LEG_SR_MASKALL		(MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
109 					MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
110 
111 /* MSI interrupt status mask bits */
112 #define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
113 #define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
114 
115 #define MSII_PRESENT			BIT(0)
116 #define MSII_ENABLE			BIT(0)
117 #define MSII_STATUS_ENABLE		BIT(15)
118 
119 /* Bridge config interrupt mask */
120 #define BRCFG_INTERRUPT_MASK		BIT(0)
121 #define BREG_PRESENT			BIT(0)
122 #define BREG_ENABLE			BIT(0)
123 #define BREG_ENABLE_FORCE		BIT(1)
124 
125 /* E_ECAM status mask bits */
126 #define E_ECAM_PRESENT			BIT(0)
127 #define E_ECAM_CR_ENABLE		BIT(0)
128 #define E_ECAM_SIZE_LOC			GENMASK(20, 16)
129 #define E_ECAM_SIZE_SHIFT		16
130 #define NWL_ECAM_VALUE_DEFAULT		12
131 
132 #define CFG_DMA_REG_BAR			GENMASK(2, 0)
133 #define CFG_PCIE_CACHE			GENMASK(7, 0)
134 
135 #define INT_PCI_MSI_NR			(2 * 32)
136 
137 /* Readin the PS_LINKUP */
138 #define PS_LINKUP_OFFSET		0x00000238
139 #define PCIE_PHY_LINKUP_BIT		BIT(0)
140 #define PHY_RDY_LINKUP_BIT		BIT(1)
141 
142 /* Parameters for the waiting for link up routine */
143 #define LINK_WAIT_MAX_RETRIES          10
144 #define LINK_WAIT_USLEEP_MIN           90000
145 #define LINK_WAIT_USLEEP_MAX           100000
146 
147 struct nwl_msi {			/* MSI information */
148 	struct irq_domain *msi_domain;
149 	DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
150 	struct irq_domain *dev_domain;
151 	struct mutex lock;		/* protect bitmap variable */
152 	int irq_msi0;
153 	int irq_msi1;
154 };
155 
156 struct nwl_pcie {
157 	struct device *dev;
158 	void __iomem *breg_base;
159 	void __iomem *pcireg_base;
160 	void __iomem *ecam_base;
161 	phys_addr_t phys_breg_base;	/* Physical Bridge Register Base */
162 	phys_addr_t phys_pcie_reg_base;	/* Physical PCIe Controller Base */
163 	phys_addr_t phys_ecam_base;	/* Physical Configuration Base */
164 	u32 breg_size;
165 	u32 pcie_reg_size;
166 	u32 ecam_size;
167 	int irq_intx;
168 	int irq_misc;
169 	u32 ecam_value;
170 	u8 last_busno;
171 	struct nwl_msi msi;
172 	struct irq_domain *legacy_irq_domain;
173 	struct clk *clk;
174 	raw_spinlock_t leg_mask_lock;
175 };
176 
177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
178 {
179 	return readl(pcie->breg_base + off);
180 }
181 
182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
183 {
184 	writel(val, pcie->breg_base + off);
185 }
186 
187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
188 {
189 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
190 		return true;
191 	return false;
192 }
193 
194 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
195 {
196 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
197 		return true;
198 	return false;
199 }
200 
201 static int nwl_wait_for_link(struct nwl_pcie *pcie)
202 {
203 	struct device *dev = pcie->dev;
204 	int retries;
205 
206 	/* check if the link is up or not */
207 	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
208 		if (nwl_phy_link_up(pcie))
209 			return 0;
210 		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
211 	}
212 
213 	dev_err(dev, "PHY link never came up\n");
214 	return -ETIMEDOUT;
215 }
216 
217 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
218 {
219 	struct nwl_pcie *pcie = bus->sysdata;
220 
221 	/* Check link before accessing downstream ports */
222 	if (!pci_is_root_bus(bus)) {
223 		if (!nwl_pcie_link_up(pcie))
224 			return false;
225 	} else if (devfn > 0)
226 		/* Only one device down on each root port */
227 		return false;
228 
229 	return true;
230 }
231 
232 /**
233  * nwl_pcie_map_bus - Get configuration base
234  *
235  * @bus: Bus structure of current bus
236  * @devfn: Device/function
237  * @where: Offset from base
238  *
239  * Return: Base address of the configuration space needed to be
240  *	   accessed.
241  */
242 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
243 				      int where)
244 {
245 	struct nwl_pcie *pcie = bus->sysdata;
246 
247 	if (!nwl_pcie_valid_device(bus, devfn))
248 		return NULL;
249 
250 	return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
251 }
252 
253 /* PCIe operations */
254 static struct pci_ops nwl_pcie_ops = {
255 	.map_bus = nwl_pcie_map_bus,
256 	.read  = pci_generic_config_read,
257 	.write = pci_generic_config_write,
258 };
259 
260 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
261 {
262 	struct nwl_pcie *pcie = data;
263 	struct device *dev = pcie->dev;
264 	u32 misc_stat;
265 
266 	/* Checking for misc interrupts */
267 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
268 				     MSGF_MISC_SR_MASKALL;
269 	if (!misc_stat)
270 		return IRQ_NONE;
271 
272 	if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
273 		dev_err(dev, "Received Message FIFO Overflow\n");
274 
275 	if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
276 		dev_err(dev, "Slave error\n");
277 
278 	if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
279 		dev_err(dev, "Master error\n");
280 
281 	if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
282 		dev_err(dev, "In Misc Ingress address translation error\n");
283 
284 	if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
285 		dev_err(dev, "In Misc Egress address translation error\n");
286 
287 	if (misc_stat & MSGF_MISC_SR_FATAL_AER)
288 		dev_err(dev, "Fatal Error in AER Capability\n");
289 
290 	if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
291 		dev_err(dev, "Non-Fatal Error in AER Capability\n");
292 
293 	if (misc_stat & MSGF_MISC_SR_CORR_AER)
294 		dev_err(dev, "Correctable Error in AER Capability\n");
295 
296 	if (misc_stat & MSGF_MISC_SR_UR_DETECT)
297 		dev_err(dev, "Unsupported request Detected\n");
298 
299 	if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
300 		dev_err(dev, "Non-Fatal Error Detected\n");
301 
302 	if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
303 		dev_err(dev, "Fatal Error Detected\n");
304 
305 	if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
306 		dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
307 
308 	if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
309 		dev_info(dev, "Link Bandwidth Management Status bit set\n");
310 
311 	/* Clear misc interrupt status */
312 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
313 
314 	return IRQ_HANDLED;
315 }
316 
317 static void nwl_pcie_leg_handler(struct irq_desc *desc)
318 {
319 	struct irq_chip *chip = irq_desc_get_chip(desc);
320 	struct nwl_pcie *pcie;
321 	unsigned long status;
322 	u32 bit;
323 
324 	chained_irq_enter(chip, desc);
325 	pcie = irq_desc_get_handler_data(desc);
326 
327 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
328 				MSGF_LEG_SR_MASKALL) != 0) {
329 		for_each_set_bit(bit, &status, PCI_NUM_INTX)
330 			generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
331 	}
332 
333 	chained_irq_exit(chip, desc);
334 }
335 
336 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
337 {
338 	struct nwl_msi *msi = &pcie->msi;
339 	unsigned long status;
340 	u32 bit;
341 
342 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
343 		for_each_set_bit(bit, &status, 32) {
344 			nwl_bridge_writel(pcie, 1 << bit, status_reg);
345 			generic_handle_domain_irq(msi->dev_domain, bit);
346 		}
347 	}
348 }
349 
350 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
351 {
352 	struct irq_chip *chip = irq_desc_get_chip(desc);
353 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
354 
355 	chained_irq_enter(chip, desc);
356 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
357 	chained_irq_exit(chip, desc);
358 }
359 
360 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
361 {
362 	struct irq_chip *chip = irq_desc_get_chip(desc);
363 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
364 
365 	chained_irq_enter(chip, desc);
366 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
367 	chained_irq_exit(chip, desc);
368 }
369 
370 static void nwl_mask_leg_irq(struct irq_data *data)
371 {
372 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
373 	unsigned long flags;
374 	u32 mask;
375 	u32 val;
376 
377 	mask = 1 << (data->hwirq - 1);
378 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
379 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
380 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
381 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
382 }
383 
384 static void nwl_unmask_leg_irq(struct irq_data *data)
385 {
386 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
387 	unsigned long flags;
388 	u32 mask;
389 	u32 val;
390 
391 	mask = 1 << (data->hwirq - 1);
392 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
393 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
394 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
395 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
396 }
397 
398 static struct irq_chip nwl_leg_irq_chip = {
399 	.name = "nwl_pcie:legacy",
400 	.irq_enable = nwl_unmask_leg_irq,
401 	.irq_disable = nwl_mask_leg_irq,
402 	.irq_mask = nwl_mask_leg_irq,
403 	.irq_unmask = nwl_unmask_leg_irq,
404 };
405 
406 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
407 			  irq_hw_number_t hwirq)
408 {
409 	irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
410 	irq_set_chip_data(irq, domain->host_data);
411 	irq_set_status_flags(irq, IRQ_LEVEL);
412 
413 	return 0;
414 }
415 
416 static const struct irq_domain_ops legacy_domain_ops = {
417 	.map = nwl_legacy_map,
418 	.xlate = pci_irqd_intx_xlate,
419 };
420 
421 #ifdef CONFIG_PCI_MSI
422 static struct irq_chip nwl_msi_irq_chip = {
423 	.name = "nwl_pcie:msi",
424 	.irq_enable = pci_msi_unmask_irq,
425 	.irq_disable = pci_msi_mask_irq,
426 	.irq_mask = pci_msi_mask_irq,
427 	.irq_unmask = pci_msi_unmask_irq,
428 };
429 
430 static struct msi_domain_info nwl_msi_domain_info = {
431 	.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
432 		  MSI_FLAG_MULTI_PCI_MSI),
433 	.chip = &nwl_msi_irq_chip,
434 };
435 #endif
436 
437 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
438 {
439 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
440 	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
441 
442 	msg->address_lo = lower_32_bits(msi_addr);
443 	msg->address_hi = upper_32_bits(msi_addr);
444 	msg->data = data->hwirq;
445 }
446 
447 static int nwl_msi_set_affinity(struct irq_data *irq_data,
448 				const struct cpumask *mask, bool force)
449 {
450 	return -EINVAL;
451 }
452 
453 static struct irq_chip nwl_irq_chip = {
454 	.name = "Xilinx MSI",
455 	.irq_compose_msi_msg = nwl_compose_msi_msg,
456 	.irq_set_affinity = nwl_msi_set_affinity,
457 };
458 
459 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
460 				unsigned int nr_irqs, void *args)
461 {
462 	struct nwl_pcie *pcie = domain->host_data;
463 	struct nwl_msi *msi = &pcie->msi;
464 	int bit;
465 	int i;
466 
467 	mutex_lock(&msi->lock);
468 	bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
469 				      get_count_order(nr_irqs));
470 	if (bit < 0) {
471 		mutex_unlock(&msi->lock);
472 		return -ENOSPC;
473 	}
474 
475 	for (i = 0; i < nr_irqs; i++) {
476 		irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
477 				    domain->host_data, handle_simple_irq,
478 				    NULL, NULL);
479 	}
480 	mutex_unlock(&msi->lock);
481 	return 0;
482 }
483 
484 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
485 				unsigned int nr_irqs)
486 {
487 	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
488 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
489 	struct nwl_msi *msi = &pcie->msi;
490 
491 	mutex_lock(&msi->lock);
492 	bitmap_release_region(msi->bitmap, data->hwirq,
493 			      get_count_order(nr_irqs));
494 	mutex_unlock(&msi->lock);
495 }
496 
497 static const struct irq_domain_ops dev_msi_domain_ops = {
498 	.alloc  = nwl_irq_domain_alloc,
499 	.free   = nwl_irq_domain_free,
500 };
501 
502 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
503 {
504 #ifdef CONFIG_PCI_MSI
505 	struct device *dev = pcie->dev;
506 	struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
507 	struct nwl_msi *msi = &pcie->msi;
508 
509 	msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
510 						&dev_msi_domain_ops, pcie);
511 	if (!msi->dev_domain) {
512 		dev_err(dev, "failed to create dev IRQ domain\n");
513 		return -ENOMEM;
514 	}
515 	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
516 						    &nwl_msi_domain_info,
517 						    msi->dev_domain);
518 	if (!msi->msi_domain) {
519 		dev_err(dev, "failed to create msi IRQ domain\n");
520 		irq_domain_remove(msi->dev_domain);
521 		return -ENOMEM;
522 	}
523 #endif
524 	return 0;
525 }
526 
527 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
528 {
529 	struct device *dev = pcie->dev;
530 	struct device_node *node = dev->of_node;
531 	struct device_node *legacy_intc_node;
532 
533 	legacy_intc_node = of_get_next_child(node, NULL);
534 	if (!legacy_intc_node) {
535 		dev_err(dev, "No legacy intc node found\n");
536 		return -EINVAL;
537 	}
538 
539 	pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
540 							PCI_NUM_INTX,
541 							&legacy_domain_ops,
542 							pcie);
543 	of_node_put(legacy_intc_node);
544 	if (!pcie->legacy_irq_domain) {
545 		dev_err(dev, "failed to create IRQ domain\n");
546 		return -ENOMEM;
547 	}
548 
549 	raw_spin_lock_init(&pcie->leg_mask_lock);
550 	nwl_pcie_init_msi_irq_domain(pcie);
551 	return 0;
552 }
553 
554 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
555 {
556 	struct device *dev = pcie->dev;
557 	struct platform_device *pdev = to_platform_device(dev);
558 	struct nwl_msi *msi = &pcie->msi;
559 	unsigned long base;
560 	int ret;
561 
562 	mutex_init(&msi->lock);
563 
564 	/* Get msi_1 IRQ number */
565 	msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
566 	if (msi->irq_msi1 < 0)
567 		return -EINVAL;
568 
569 	irq_set_chained_handler_and_data(msi->irq_msi1,
570 					 nwl_pcie_msi_handler_high, pcie);
571 
572 	/* Get msi_0 IRQ number */
573 	msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
574 	if (msi->irq_msi0 < 0)
575 		return -EINVAL;
576 
577 	irq_set_chained_handler_and_data(msi->irq_msi0,
578 					 nwl_pcie_msi_handler_low, pcie);
579 
580 	/* Check for msii_present bit */
581 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
582 	if (!ret) {
583 		dev_err(dev, "MSI not present\n");
584 		return -EIO;
585 	}
586 
587 	/* Enable MSII */
588 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
589 			  MSII_ENABLE, I_MSII_CONTROL);
590 
591 	/* Enable MSII status */
592 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
593 			  MSII_STATUS_ENABLE, I_MSII_CONTROL);
594 
595 	/* setup AFI/FPCI range */
596 	base = pcie->phys_pcie_reg_base;
597 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
598 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
599 
600 	/*
601 	 * For high range MSI interrupts: disable, clear any pending,
602 	 * and enable
603 	 */
604 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
605 
606 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &
607 			  MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
608 
609 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
610 
611 	/*
612 	 * For low range MSI interrupts: disable, clear any pending,
613 	 * and enable
614 	 */
615 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
616 
617 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
618 			  MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
619 
620 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
621 
622 	return 0;
623 }
624 
625 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
626 {
627 	struct device *dev = pcie->dev;
628 	struct platform_device *pdev = to_platform_device(dev);
629 	u32 breg_val, ecam_val, first_busno = 0;
630 	int err;
631 
632 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
633 	if (!breg_val) {
634 		dev_err(dev, "BREG is not present\n");
635 		return breg_val;
636 	}
637 
638 	/* Write bridge_off to breg base */
639 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
640 			  E_BREG_BASE_LO);
641 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
642 			  E_BREG_BASE_HI);
643 
644 	/* Enable BREG */
645 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
646 			  E_BREG_CONTROL);
647 
648 	/* Disable DMA channel registers */
649 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
650 			  CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
651 
652 	/* Enable Ingress subtractive decode translation */
653 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
654 
655 	/* Enable msg filtering details */
656 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
657 			  BRCFG_PCIE_RX_MSG_FILTER);
658 
659 	/* This routes the PCIe DMA traffic to go through CCI path */
660 	if (of_dma_is_coherent(dev->of_node))
661 		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
662 				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
663 
664 	err = nwl_wait_for_link(pcie);
665 	if (err)
666 		return err;
667 
668 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
669 	if (!ecam_val) {
670 		dev_err(dev, "ECAM is not present\n");
671 		return ecam_val;
672 	}
673 
674 	/* Enable ECAM */
675 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
676 			  E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
677 
678 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
679 			  (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
680 			  E_ECAM_CONTROL);
681 
682 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
683 			  E_ECAM_BASE_LO);
684 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
685 			  E_ECAM_BASE_HI);
686 
687 	/* Get bus range */
688 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
689 	pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
690 	/* Write primary, secondary and subordinate bus numbers */
691 	ecam_val = first_busno;
692 	ecam_val |= (first_busno + 1) << 8;
693 	ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
694 	writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
695 
696 	if (nwl_pcie_link_up(pcie))
697 		dev_info(dev, "Link is UP\n");
698 	else
699 		dev_info(dev, "Link is DOWN\n");
700 
701 	/* Get misc IRQ number */
702 	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
703 	if (pcie->irq_misc < 0)
704 		return -EINVAL;
705 
706 	err = devm_request_irq(dev, pcie->irq_misc,
707 			       nwl_pcie_misc_handler, IRQF_SHARED,
708 			       "nwl_pcie:misc", pcie);
709 	if (err) {
710 		dev_err(dev, "fail to register misc IRQ#%d\n",
711 			pcie->irq_misc);
712 		return err;
713 	}
714 
715 	/* Disable all misc interrupts */
716 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
717 
718 	/* Clear pending misc interrupts */
719 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
720 			  MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
721 
722 	/* Enable all misc interrupts */
723 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
724 
725 	/* Disable all legacy interrupts */
726 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
727 
728 	/* Clear pending legacy interrupts */
729 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
730 			  MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
731 
732 	/* Enable all legacy interrupts */
733 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
734 
735 	/* Enable the bridge config interrupt */
736 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
737 			  BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
738 
739 	return 0;
740 }
741 
742 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
743 			     struct platform_device *pdev)
744 {
745 	struct device *dev = pcie->dev;
746 	struct resource *res;
747 
748 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
749 	pcie->breg_base = devm_ioremap_resource(dev, res);
750 	if (IS_ERR(pcie->breg_base))
751 		return PTR_ERR(pcie->breg_base);
752 	pcie->phys_breg_base = res->start;
753 
754 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
755 	pcie->pcireg_base = devm_ioremap_resource(dev, res);
756 	if (IS_ERR(pcie->pcireg_base))
757 		return PTR_ERR(pcie->pcireg_base);
758 	pcie->phys_pcie_reg_base = res->start;
759 
760 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
761 	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
762 	if (IS_ERR(pcie->ecam_base))
763 		return PTR_ERR(pcie->ecam_base);
764 	pcie->phys_ecam_base = res->start;
765 
766 	/* Get intx IRQ number */
767 	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
768 	if (pcie->irq_intx < 0)
769 		return pcie->irq_intx;
770 
771 	irq_set_chained_handler_and_data(pcie->irq_intx,
772 					 nwl_pcie_leg_handler, pcie);
773 
774 	return 0;
775 }
776 
777 static const struct of_device_id nwl_pcie_of_match[] = {
778 	{ .compatible = "xlnx,nwl-pcie-2.11", },
779 	{}
780 };
781 
782 static int nwl_pcie_probe(struct platform_device *pdev)
783 {
784 	struct device *dev = &pdev->dev;
785 	struct nwl_pcie *pcie;
786 	struct pci_host_bridge *bridge;
787 	int err;
788 
789 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
790 	if (!bridge)
791 		return -ENODEV;
792 
793 	pcie = pci_host_bridge_priv(bridge);
794 
795 	pcie->dev = dev;
796 	pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
797 
798 	err = nwl_pcie_parse_dt(pcie, pdev);
799 	if (err) {
800 		dev_err(dev, "Parsing DT failed\n");
801 		return err;
802 	}
803 
804 	pcie->clk = devm_clk_get(dev, NULL);
805 	if (IS_ERR(pcie->clk))
806 		return PTR_ERR(pcie->clk);
807 
808 	err = clk_prepare_enable(pcie->clk);
809 	if (err) {
810 		dev_err(dev, "can't enable PCIe ref clock\n");
811 		return err;
812 	}
813 
814 	err = nwl_pcie_bridge_init(pcie);
815 	if (err) {
816 		dev_err(dev, "HW Initialization failed\n");
817 		return err;
818 	}
819 
820 	err = nwl_pcie_init_irq_domain(pcie);
821 	if (err) {
822 		dev_err(dev, "Failed creating IRQ Domain\n");
823 		return err;
824 	}
825 
826 	bridge->sysdata = pcie;
827 	bridge->ops = &nwl_pcie_ops;
828 
829 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
830 		err = nwl_pcie_enable_msi(pcie);
831 		if (err < 0) {
832 			dev_err(dev, "failed to enable MSI support: %d\n", err);
833 			return err;
834 		}
835 	}
836 
837 	return pci_host_probe(bridge);
838 }
839 
840 static struct platform_driver nwl_pcie_driver = {
841 	.driver = {
842 		.name = "nwl-pcie",
843 		.suppress_bind_attrs = true,
844 		.of_match_table = nwl_pcie_of_match,
845 	},
846 	.probe = nwl_pcie_probe,
847 };
848 builtin_platform_driver(nwl_pcie_driver);
849