1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge 4 * 5 * (C) Copyright 2019 - 2020, Xilinx, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/pci.h> 21 #include <linux/platform_device.h> 22 #include <linux/pci-ecam.h> 23 24 #include "../pci.h" 25 26 /* Register definitions */ 27 #define XILINX_CPM_PCIE_REG_IDR 0x00000E10 28 #define XILINX_CPM_PCIE_REG_IMR 0x00000E14 29 #define XILINX_CPM_PCIE_REG_PSCR 0x00000E1C 30 #define XILINX_CPM_PCIE_REG_RPSC 0x00000E20 31 #define XILINX_CPM_PCIE_REG_RPEFR 0x00000E2C 32 #define XILINX_CPM_PCIE_REG_IDRN 0x00000E38 33 #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C 34 #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340 35 #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 36 #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) 37 38 #define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 39 #define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 40 #define XILINX_CPM_PCIE_IR_LOCAL BIT(0) 41 42 /* Interrupt registers definitions */ 43 #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 44 #define XILINX_CPM_PCIE_INTR_HOT_RESET 3 45 #define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4 46 #define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8 47 #define XILINX_CPM_PCIE_INTR_CORRECTABLE 9 48 #define XILINX_CPM_PCIE_INTR_NONFATAL 10 49 #define XILINX_CPM_PCIE_INTR_FATAL 11 50 #define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12 51 #define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15 52 #define XILINX_CPM_PCIE_INTR_INTX 16 53 #define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17 54 #define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20 55 #define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21 56 #define XILINX_CPM_PCIE_INTR_SLV_COMPL 22 57 #define XILINX_CPM_PCIE_INTR_SLV_ERRP 23 58 #define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24 59 #define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25 60 #define XILINX_CPM_PCIE_INTR_MST_DECERR 26 61 #define XILINX_CPM_PCIE_INTR_MST_SLVERR 27 62 #define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28 63 64 #define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x) 65 66 #define XILINX_CPM_PCIE_IMR_ALL_MASK \ 67 ( \ 68 IMR(LINK_DOWN) | \ 69 IMR(HOT_RESET) | \ 70 IMR(CFG_PCIE_TIMEOUT) | \ 71 IMR(CFG_TIMEOUT) | \ 72 IMR(CORRECTABLE) | \ 73 IMR(NONFATAL) | \ 74 IMR(FATAL) | \ 75 IMR(CFG_ERR_POISON) | \ 76 IMR(PME_TO_ACK_RCVD) | \ 77 IMR(INTX) | \ 78 IMR(PM_PME_RCVD) | \ 79 IMR(SLV_UNSUPP) | \ 80 IMR(SLV_UNEXP) | \ 81 IMR(SLV_COMPL) | \ 82 IMR(SLV_ERRP) | \ 83 IMR(SLV_CMPABT) | \ 84 IMR(SLV_ILLBUR) | \ 85 IMR(MST_DECERR) | \ 86 IMR(MST_SLVERR) | \ 87 IMR(SLV_PCIE_TIMEOUT) \ 88 ) 89 90 #define XILINX_CPM_PCIE_IDR_ALL_MASK 0xFFFFFFFF 91 #define XILINX_CPM_PCIE_IDRN_MASK GENMASK(19, 16) 92 #define XILINX_CPM_PCIE_IDRN_SHIFT 16 93 94 /* Root Port Error FIFO Read Register definitions */ 95 #define XILINX_CPM_PCIE_RPEFR_ERR_VALID BIT(18) 96 #define XILINX_CPM_PCIE_RPEFR_REQ_ID GENMASK(15, 0) 97 #define XILINX_CPM_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF 98 99 /* Root Port Status/control Register definitions */ 100 #define XILINX_CPM_PCIE_REG_RPSC_BEN BIT(0) 101 102 /* Phy Status/Control Register definitions */ 103 #define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11) 104 105 enum xilinx_cpm_version { 106 CPM, 107 CPM5, 108 }; 109 110 /** 111 * struct xilinx_cpm_variant - CPM variant information 112 * @version: CPM version 113 */ 114 struct xilinx_cpm_variant { 115 enum xilinx_cpm_version version; 116 }; 117 118 /** 119 * struct xilinx_cpm_pcie - PCIe port information 120 * @dev: Device pointer 121 * @reg_base: Bridge Register Base 122 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base 123 * @intx_domain: Legacy IRQ domain pointer 124 * @cpm_domain: CPM IRQ domain pointer 125 * @cfg: Holds mappings of config space window 126 * @intx_irq: legacy interrupt number 127 * @irq: Error interrupt number 128 * @lock: lock protecting shared register access 129 * @variant: CPM version check pointer 130 */ 131 struct xilinx_cpm_pcie { 132 struct device *dev; 133 void __iomem *reg_base; 134 void __iomem *cpm_base; 135 struct irq_domain *intx_domain; 136 struct irq_domain *cpm_domain; 137 struct pci_config_window *cfg; 138 int intx_irq; 139 int irq; 140 raw_spinlock_t lock; 141 const struct xilinx_cpm_variant *variant; 142 }; 143 144 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) 145 { 146 return readl_relaxed(port->reg_base + reg); 147 } 148 149 static void pcie_write(struct xilinx_cpm_pcie *port, 150 u32 val, u32 reg) 151 { 152 writel_relaxed(val, port->reg_base + reg); 153 } 154 155 static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port) 156 { 157 return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) & 158 XILINX_CPM_PCIE_REG_PSCR_LNKUP); 159 } 160 161 static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port) 162 { 163 unsigned long val = pcie_read(port, XILINX_CPM_PCIE_REG_RPEFR); 164 165 if (val & XILINX_CPM_PCIE_RPEFR_ERR_VALID) { 166 dev_dbg(port->dev, "Requester ID %lu\n", 167 val & XILINX_CPM_PCIE_RPEFR_REQ_ID); 168 pcie_write(port, XILINX_CPM_PCIE_RPEFR_ALL_MASK, 169 XILINX_CPM_PCIE_REG_RPEFR); 170 } 171 } 172 173 static void xilinx_cpm_mask_leg_irq(struct irq_data *data) 174 { 175 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data); 176 unsigned long flags; 177 u32 mask; 178 u32 val; 179 180 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT); 181 raw_spin_lock_irqsave(&port->lock, flags); 182 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK); 183 pcie_write(port, (val & (~mask)), XILINX_CPM_PCIE_REG_IDRN_MASK); 184 raw_spin_unlock_irqrestore(&port->lock, flags); 185 } 186 187 static void xilinx_cpm_unmask_leg_irq(struct irq_data *data) 188 { 189 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data); 190 unsigned long flags; 191 u32 mask; 192 u32 val; 193 194 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT); 195 raw_spin_lock_irqsave(&port->lock, flags); 196 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK); 197 pcie_write(port, (val | mask), XILINX_CPM_PCIE_REG_IDRN_MASK); 198 raw_spin_unlock_irqrestore(&port->lock, flags); 199 } 200 201 static struct irq_chip xilinx_cpm_leg_irq_chip = { 202 .name = "INTx", 203 .irq_mask = xilinx_cpm_mask_leg_irq, 204 .irq_unmask = xilinx_cpm_unmask_leg_irq, 205 }; 206 207 /** 208 * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid 209 * @domain: IRQ domain 210 * @irq: Virtual IRQ number 211 * @hwirq: HW interrupt number 212 * 213 * Return: Always returns 0. 214 */ 215 static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain, 216 unsigned int irq, irq_hw_number_t hwirq) 217 { 218 irq_set_chip_and_handler(irq, &xilinx_cpm_leg_irq_chip, 219 handle_level_irq); 220 irq_set_chip_data(irq, domain->host_data); 221 irq_set_status_flags(irq, IRQ_LEVEL); 222 223 return 0; 224 } 225 226 /* INTx IRQ Domain operations */ 227 static const struct irq_domain_ops intx_domain_ops = { 228 .map = xilinx_cpm_pcie_intx_map, 229 }; 230 231 static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc) 232 { 233 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc); 234 struct irq_chip *chip = irq_desc_get_chip(desc); 235 unsigned long val; 236 int i; 237 238 chained_irq_enter(chip, desc); 239 240 val = FIELD_GET(XILINX_CPM_PCIE_IDRN_MASK, 241 pcie_read(port, XILINX_CPM_PCIE_REG_IDRN)); 242 243 for_each_set_bit(i, &val, PCI_NUM_INTX) 244 generic_handle_domain_irq(port->intx_domain, i); 245 246 chained_irq_exit(chip, desc); 247 } 248 249 static void xilinx_cpm_mask_event_irq(struct irq_data *d) 250 { 251 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d); 252 u32 val; 253 254 raw_spin_lock(&port->lock); 255 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR); 256 val &= ~BIT(d->hwirq); 257 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR); 258 raw_spin_unlock(&port->lock); 259 } 260 261 static void xilinx_cpm_unmask_event_irq(struct irq_data *d) 262 { 263 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d); 264 u32 val; 265 266 raw_spin_lock(&port->lock); 267 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR); 268 val |= BIT(d->hwirq); 269 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR); 270 raw_spin_unlock(&port->lock); 271 } 272 273 static struct irq_chip xilinx_cpm_event_irq_chip = { 274 .name = "RC-Event", 275 .irq_mask = xilinx_cpm_mask_event_irq, 276 .irq_unmask = xilinx_cpm_unmask_event_irq, 277 }; 278 279 static int xilinx_cpm_pcie_event_map(struct irq_domain *domain, 280 unsigned int irq, irq_hw_number_t hwirq) 281 { 282 irq_set_chip_and_handler(irq, &xilinx_cpm_event_irq_chip, 283 handle_level_irq); 284 irq_set_chip_data(irq, domain->host_data); 285 irq_set_status_flags(irq, IRQ_LEVEL); 286 return 0; 287 } 288 289 static const struct irq_domain_ops event_domain_ops = { 290 .map = xilinx_cpm_pcie_event_map, 291 }; 292 293 static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) 294 { 295 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc); 296 struct irq_chip *chip = irq_desc_get_chip(desc); 297 unsigned long val; 298 int i; 299 300 chained_irq_enter(chip, desc); 301 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR); 302 val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR); 303 for_each_set_bit(i, &val, 32) 304 generic_handle_domain_irq(port->cpm_domain, i); 305 pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); 306 307 if (port->variant->version == CPM5) { 308 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); 309 if (val) 310 writel_relaxed(val, port->cpm_base + 311 XILINX_CPM_PCIE_IR_STATUS); 312 } 313 314 /* 315 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to 316 * CPM SLCR block. 317 */ 318 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS); 319 if (val) 320 writel_relaxed(val, 321 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS); 322 323 chained_irq_exit(chip, desc); 324 } 325 326 #define _IC(x, s) \ 327 [XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s } 328 329 static const struct { 330 const char *sym; 331 const char *str; 332 } intr_cause[32] = { 333 _IC(LINK_DOWN, "Link Down"), 334 _IC(HOT_RESET, "Hot reset"), 335 _IC(CFG_TIMEOUT, "ECAM access timeout"), 336 _IC(CORRECTABLE, "Correctable error message"), 337 _IC(NONFATAL, "Non fatal error message"), 338 _IC(FATAL, "Fatal error message"), 339 _IC(SLV_UNSUPP, "Slave unsupported request"), 340 _IC(SLV_UNEXP, "Slave unexpected completion"), 341 _IC(SLV_COMPL, "Slave completion timeout"), 342 _IC(SLV_ERRP, "Slave Error Poison"), 343 _IC(SLV_CMPABT, "Slave Completer Abort"), 344 _IC(SLV_ILLBUR, "Slave Illegal Burst"), 345 _IC(MST_DECERR, "Master decode error"), 346 _IC(MST_SLVERR, "Master slave error"), 347 _IC(CFG_PCIE_TIMEOUT, "PCIe ECAM access timeout"), 348 _IC(CFG_ERR_POISON, "ECAM poisoned completion received"), 349 _IC(PME_TO_ACK_RCVD, "PME_TO_ACK message received"), 350 _IC(PM_PME_RCVD, "PM_PME message received"), 351 _IC(SLV_PCIE_TIMEOUT, "PCIe completion timeout received"), 352 }; 353 354 static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id) 355 { 356 struct xilinx_cpm_pcie *port = dev_id; 357 struct device *dev = port->dev; 358 struct irq_data *d; 359 360 d = irq_domain_get_irq_data(port->cpm_domain, irq); 361 362 switch (d->hwirq) { 363 case XILINX_CPM_PCIE_INTR_CORRECTABLE: 364 case XILINX_CPM_PCIE_INTR_NONFATAL: 365 case XILINX_CPM_PCIE_INTR_FATAL: 366 cpm_pcie_clear_err_interrupts(port); 367 fallthrough; 368 369 default: 370 if (intr_cause[d->hwirq].str) 371 dev_warn(dev, "%s\n", intr_cause[d->hwirq].str); 372 else 373 dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq); 374 } 375 376 return IRQ_HANDLED; 377 } 378 379 static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port) 380 { 381 if (port->intx_domain) { 382 irq_domain_remove(port->intx_domain); 383 port->intx_domain = NULL; 384 } 385 386 if (port->cpm_domain) { 387 irq_domain_remove(port->cpm_domain); 388 port->cpm_domain = NULL; 389 } 390 } 391 392 /** 393 * xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain 394 * @port: PCIe port information 395 * 396 * Return: '0' on success and error value on failure 397 */ 398 static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port) 399 { 400 struct device *dev = port->dev; 401 struct device_node *node = dev->of_node; 402 struct device_node *pcie_intc_node; 403 404 /* Setup INTx */ 405 pcie_intc_node = of_get_next_child(node, NULL); 406 if (!pcie_intc_node) { 407 dev_err(dev, "No PCIe Intc node found\n"); 408 return -EINVAL; 409 } 410 411 port->cpm_domain = irq_domain_add_linear(pcie_intc_node, 32, 412 &event_domain_ops, 413 port); 414 if (!port->cpm_domain) 415 goto out; 416 417 irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS); 418 419 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 420 &intx_domain_ops, 421 port); 422 if (!port->intx_domain) 423 goto out; 424 425 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); 426 427 of_node_put(pcie_intc_node); 428 raw_spin_lock_init(&port->lock); 429 430 return 0; 431 out: 432 xilinx_cpm_free_irq_domains(port); 433 of_node_put(pcie_intc_node); 434 dev_err(dev, "Failed to allocate IRQ domains\n"); 435 436 return -ENOMEM; 437 } 438 439 static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) 440 { 441 struct device *dev = port->dev; 442 struct platform_device *pdev = to_platform_device(dev); 443 int i, irq; 444 445 port->irq = platform_get_irq(pdev, 0); 446 if (port->irq < 0) 447 return port->irq; 448 449 for (i = 0; i < ARRAY_SIZE(intr_cause); i++) { 450 int err; 451 452 if (!intr_cause[i].str) 453 continue; 454 455 irq = irq_create_mapping(port->cpm_domain, i); 456 if (!irq) { 457 dev_err(dev, "Failed to map interrupt\n"); 458 return -ENXIO; 459 } 460 461 err = devm_request_irq(dev, irq, xilinx_cpm_pcie_intr_handler, 462 0, intr_cause[i].sym, port); 463 if (err) { 464 dev_err(dev, "Failed to request IRQ %d\n", irq); 465 return err; 466 } 467 } 468 469 port->intx_irq = irq_create_mapping(port->cpm_domain, 470 XILINX_CPM_PCIE_INTR_INTX); 471 if (!port->intx_irq) { 472 dev_err(dev, "Failed to map INTx interrupt\n"); 473 return -ENXIO; 474 } 475 476 /* Plug the INTx chained handler */ 477 irq_set_chained_handler_and_data(port->intx_irq, 478 xilinx_cpm_pcie_intx_flow, port); 479 480 /* Plug the main event chained handler */ 481 irq_set_chained_handler_and_data(port->irq, 482 xilinx_cpm_pcie_event_flow, port); 483 484 return 0; 485 } 486 487 /** 488 * xilinx_cpm_pcie_init_port - Initialize hardware 489 * @port: PCIe port information 490 */ 491 static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) 492 { 493 if (cpm_pcie_link_up(port)) 494 dev_info(port->dev, "PCIe Link is UP\n"); 495 else 496 dev_info(port->dev, "PCIe Link is DOWN\n"); 497 498 /* Disable all interrupts */ 499 pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK, 500 XILINX_CPM_PCIE_REG_IMR); 501 502 /* Clear pending interrupts */ 503 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) & 504 XILINX_CPM_PCIE_IMR_ALL_MASK, 505 XILINX_CPM_PCIE_REG_IDR); 506 507 /* 508 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to 509 * CPM SLCR block. 510 */ 511 writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, 512 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); 513 514 if (port->variant->version == CPM5) { 515 writel(XILINX_CPM_PCIE_IR_LOCAL, 516 port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); 517 } 518 519 /* Enable the Bridge enable bit */ 520 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | 521 XILINX_CPM_PCIE_REG_RPSC_BEN, 522 XILINX_CPM_PCIE_REG_RPSC); 523 } 524 525 /** 526 * xilinx_cpm_pcie_parse_dt - Parse Device tree 527 * @port: PCIe port information 528 * @bus_range: Bus resource 529 * 530 * Return: '0' on success and error value on failure 531 */ 532 static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, 533 struct resource *bus_range) 534 { 535 struct device *dev = port->dev; 536 struct platform_device *pdev = to_platform_device(dev); 537 struct resource *res; 538 539 port->cpm_base = devm_platform_ioremap_resource_byname(pdev, 540 "cpm_slcr"); 541 if (IS_ERR(port->cpm_base)) 542 return PTR_ERR(port->cpm_base); 543 544 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 545 if (!res) 546 return -ENXIO; 547 548 port->cfg = pci_ecam_create(dev, res, bus_range, 549 &pci_generic_ecam_ops); 550 if (IS_ERR(port->cfg)) 551 return PTR_ERR(port->cfg); 552 553 if (port->variant->version == CPM5) { 554 port->reg_base = devm_platform_ioremap_resource_byname(pdev, 555 "cpm_csr"); 556 if (IS_ERR(port->reg_base)) 557 return PTR_ERR(port->reg_base); 558 } else { 559 port->reg_base = port->cfg->win; 560 } 561 562 return 0; 563 } 564 565 static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port) 566 { 567 irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL); 568 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 569 } 570 571 /** 572 * xilinx_cpm_pcie_probe - Probe function 573 * @pdev: Platform device pointer 574 * 575 * Return: '0' on success and error value on failure 576 */ 577 static int xilinx_cpm_pcie_probe(struct platform_device *pdev) 578 { 579 struct xilinx_cpm_pcie *port; 580 struct device *dev = &pdev->dev; 581 struct pci_host_bridge *bridge; 582 struct resource_entry *bus; 583 int err; 584 585 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); 586 if (!bridge) 587 return -ENODEV; 588 589 port = pci_host_bridge_priv(bridge); 590 591 port->dev = dev; 592 593 err = xilinx_cpm_pcie_init_irq_domain(port); 594 if (err) 595 return err; 596 597 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); 598 if (!bus) 599 return -ENODEV; 600 601 port->variant = of_device_get_match_data(dev); 602 603 err = xilinx_cpm_pcie_parse_dt(port, bus->res); 604 if (err) { 605 dev_err(dev, "Parsing DT failed\n"); 606 goto err_parse_dt; 607 } 608 609 xilinx_cpm_pcie_init_port(port); 610 611 err = xilinx_cpm_setup_irq(port); 612 if (err) { 613 dev_err(dev, "Failed to set up interrupts\n"); 614 goto err_setup_irq; 615 } 616 617 bridge->sysdata = port->cfg; 618 bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; 619 620 err = pci_host_probe(bridge); 621 if (err < 0) 622 goto err_host_bridge; 623 624 return 0; 625 626 err_host_bridge: 627 xilinx_cpm_free_interrupts(port); 628 err_setup_irq: 629 pci_ecam_free(port->cfg); 630 err_parse_dt: 631 xilinx_cpm_free_irq_domains(port); 632 return err; 633 } 634 635 static const struct xilinx_cpm_variant cpm_host = { 636 .version = CPM, 637 }; 638 639 static const struct xilinx_cpm_variant cpm5_host = { 640 .version = CPM5, 641 }; 642 643 static const struct of_device_id xilinx_cpm_pcie_of_match[] = { 644 { 645 .compatible = "xlnx,versal-cpm-host-1.00", 646 .data = &cpm_host, 647 }, 648 { 649 .compatible = "xlnx,versal-cpm5-host", 650 .data = &cpm5_host, 651 }, 652 {} 653 }; 654 655 static struct platform_driver xilinx_cpm_pcie_driver = { 656 .driver = { 657 .name = "xilinx-cpm-pcie", 658 .of_match_table = xilinx_cpm_pcie_of_match, 659 .suppress_bind_attrs = true, 660 }, 661 .probe = xilinx_cpm_pcie_probe, 662 }; 663 664 builtin_platform_driver(xilinx_cpm_pcie_driver); 665