1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
4 *
5 * (C) Copyright 2019 - 2020, Xilinx, Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_platform.h>
19 #include <linux/pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci-ecam.h>
22
23 #include "../pci.h"
24
25 /* Register definitions */
26 #define XILINX_CPM_PCIE_REG_IDR 0x00000E10
27 #define XILINX_CPM_PCIE_REG_IMR 0x00000E14
28 #define XILINX_CPM_PCIE_REG_PSCR 0x00000E1C
29 #define XILINX_CPM_PCIE_REG_RPSC 0x00000E20
30 #define XILINX_CPM_PCIE_REG_RPEFR 0x00000E2C
31 #define XILINX_CPM_PCIE_REG_IDRN 0x00000E38
32 #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C
33 #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340
34 #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
35 #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)
36
37 #define XILINX_CPM_PCIE_IR_STATUS 0x000002A0
38 #define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
39 #define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
40
41 /* Interrupt registers definitions */
42 #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
43 #define XILINX_CPM_PCIE_INTR_HOT_RESET 3
44 #define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4
45 #define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
46 #define XILINX_CPM_PCIE_INTR_CORRECTABLE 9
47 #define XILINX_CPM_PCIE_INTR_NONFATAL 10
48 #define XILINX_CPM_PCIE_INTR_FATAL 11
49 #define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12
50 #define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15
51 #define XILINX_CPM_PCIE_INTR_INTX 16
52 #define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17
53 #define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20
54 #define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21
55 #define XILINX_CPM_PCIE_INTR_SLV_COMPL 22
56 #define XILINX_CPM_PCIE_INTR_SLV_ERRP 23
57 #define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24
58 #define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25
59 #define XILINX_CPM_PCIE_INTR_MST_DECERR 26
60 #define XILINX_CPM_PCIE_INTR_MST_SLVERR 27
61 #define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28
62
63 #define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x)
64
65 #define XILINX_CPM_PCIE_IMR_ALL_MASK \
66 ( \
67 IMR(LINK_DOWN) | \
68 IMR(HOT_RESET) | \
69 IMR(CFG_PCIE_TIMEOUT) | \
70 IMR(CFG_TIMEOUT) | \
71 IMR(CORRECTABLE) | \
72 IMR(NONFATAL) | \
73 IMR(FATAL) | \
74 IMR(CFG_ERR_POISON) | \
75 IMR(PME_TO_ACK_RCVD) | \
76 IMR(INTX) | \
77 IMR(PM_PME_RCVD) | \
78 IMR(SLV_UNSUPP) | \
79 IMR(SLV_UNEXP) | \
80 IMR(SLV_COMPL) | \
81 IMR(SLV_ERRP) | \
82 IMR(SLV_CMPABT) | \
83 IMR(SLV_ILLBUR) | \
84 IMR(MST_DECERR) | \
85 IMR(MST_SLVERR) | \
86 IMR(SLV_PCIE_TIMEOUT) \
87 )
88
89 #define XILINX_CPM_PCIE_IDR_ALL_MASK 0xFFFFFFFF
90 #define XILINX_CPM_PCIE_IDRN_MASK GENMASK(19, 16)
91 #define XILINX_CPM_PCIE_IDRN_SHIFT 16
92
93 /* Root Port Error FIFO Read Register definitions */
94 #define XILINX_CPM_PCIE_RPEFR_ERR_VALID BIT(18)
95 #define XILINX_CPM_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
96 #define XILINX_CPM_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
97
98 /* Root Port Status/control Register definitions */
99 #define XILINX_CPM_PCIE_REG_RPSC_BEN BIT(0)
100
101 /* Phy Status/Control Register definitions */
102 #define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11)
103
104 enum xilinx_cpm_version {
105 CPM,
106 CPM5,
107 };
108
109 /**
110 * struct xilinx_cpm_variant - CPM variant information
111 * @version: CPM version
112 */
113 struct xilinx_cpm_variant {
114 enum xilinx_cpm_version version;
115 };
116
117 /**
118 * struct xilinx_cpm_pcie - PCIe port information
119 * @dev: Device pointer
120 * @reg_base: Bridge Register Base
121 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
122 * @intx_domain: Legacy IRQ domain pointer
123 * @cpm_domain: CPM IRQ domain pointer
124 * @cfg: Holds mappings of config space window
125 * @intx_irq: legacy interrupt number
126 * @irq: Error interrupt number
127 * @lock: lock protecting shared register access
128 * @variant: CPM version check pointer
129 */
130 struct xilinx_cpm_pcie {
131 struct device *dev;
132 void __iomem *reg_base;
133 void __iomem *cpm_base;
134 struct irq_domain *intx_domain;
135 struct irq_domain *cpm_domain;
136 struct pci_config_window *cfg;
137 int intx_irq;
138 int irq;
139 raw_spinlock_t lock;
140 const struct xilinx_cpm_variant *variant;
141 };
142
pcie_read(struct xilinx_cpm_pcie * port,u32 reg)143 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
144 {
145 return readl_relaxed(port->reg_base + reg);
146 }
147
pcie_write(struct xilinx_cpm_pcie * port,u32 val,u32 reg)148 static void pcie_write(struct xilinx_cpm_pcie *port,
149 u32 val, u32 reg)
150 {
151 writel_relaxed(val, port->reg_base + reg);
152 }
153
cpm_pcie_link_up(struct xilinx_cpm_pcie * port)154 static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port)
155 {
156 return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
157 XILINX_CPM_PCIE_REG_PSCR_LNKUP);
158 }
159
cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie * port)160 static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port)
161 {
162 unsigned long val = pcie_read(port, XILINX_CPM_PCIE_REG_RPEFR);
163
164 if (val & XILINX_CPM_PCIE_RPEFR_ERR_VALID) {
165 dev_dbg(port->dev, "Requester ID %lu\n",
166 val & XILINX_CPM_PCIE_RPEFR_REQ_ID);
167 pcie_write(port, XILINX_CPM_PCIE_RPEFR_ALL_MASK,
168 XILINX_CPM_PCIE_REG_RPEFR);
169 }
170 }
171
xilinx_cpm_mask_leg_irq(struct irq_data * data)172 static void xilinx_cpm_mask_leg_irq(struct irq_data *data)
173 {
174 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
175 unsigned long flags;
176 u32 mask;
177 u32 val;
178
179 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
180 raw_spin_lock_irqsave(&port->lock, flags);
181 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
182 pcie_write(port, (val & (~mask)), XILINX_CPM_PCIE_REG_IDRN_MASK);
183 raw_spin_unlock_irqrestore(&port->lock, flags);
184 }
185
xilinx_cpm_unmask_leg_irq(struct irq_data * data)186 static void xilinx_cpm_unmask_leg_irq(struct irq_data *data)
187 {
188 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
189 unsigned long flags;
190 u32 mask;
191 u32 val;
192
193 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
194 raw_spin_lock_irqsave(&port->lock, flags);
195 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
196 pcie_write(port, (val | mask), XILINX_CPM_PCIE_REG_IDRN_MASK);
197 raw_spin_unlock_irqrestore(&port->lock, flags);
198 }
199
200 static struct irq_chip xilinx_cpm_leg_irq_chip = {
201 .name = "INTx",
202 .irq_mask = xilinx_cpm_mask_leg_irq,
203 .irq_unmask = xilinx_cpm_unmask_leg_irq,
204 };
205
206 /**
207 * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
208 * @domain: IRQ domain
209 * @irq: Virtual IRQ number
210 * @hwirq: HW interrupt number
211 *
212 * Return: Always returns 0.
213 */
xilinx_cpm_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)214 static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain,
215 unsigned int irq, irq_hw_number_t hwirq)
216 {
217 irq_set_chip_and_handler(irq, &xilinx_cpm_leg_irq_chip,
218 handle_level_irq);
219 irq_set_chip_data(irq, domain->host_data);
220 irq_set_status_flags(irq, IRQ_LEVEL);
221
222 return 0;
223 }
224
225 /* INTx IRQ Domain operations */
226 static const struct irq_domain_ops intx_domain_ops = {
227 .map = xilinx_cpm_pcie_intx_map,
228 };
229
xilinx_cpm_pcie_intx_flow(struct irq_desc * desc)230 static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc)
231 {
232 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
233 struct irq_chip *chip = irq_desc_get_chip(desc);
234 unsigned long val;
235 int i;
236
237 chained_irq_enter(chip, desc);
238
239 val = FIELD_GET(XILINX_CPM_PCIE_IDRN_MASK,
240 pcie_read(port, XILINX_CPM_PCIE_REG_IDRN));
241
242 for_each_set_bit(i, &val, PCI_NUM_INTX)
243 generic_handle_domain_irq(port->intx_domain, i);
244
245 chained_irq_exit(chip, desc);
246 }
247
xilinx_cpm_mask_event_irq(struct irq_data * d)248 static void xilinx_cpm_mask_event_irq(struct irq_data *d)
249 {
250 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
251 u32 val;
252
253 raw_spin_lock(&port->lock);
254 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
255 val &= ~BIT(d->hwirq);
256 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
257 raw_spin_unlock(&port->lock);
258 }
259
xilinx_cpm_unmask_event_irq(struct irq_data * d)260 static void xilinx_cpm_unmask_event_irq(struct irq_data *d)
261 {
262 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
263 u32 val;
264
265 raw_spin_lock(&port->lock);
266 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
267 val |= BIT(d->hwirq);
268 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
269 raw_spin_unlock(&port->lock);
270 }
271
272 static struct irq_chip xilinx_cpm_event_irq_chip = {
273 .name = "RC-Event",
274 .irq_mask = xilinx_cpm_mask_event_irq,
275 .irq_unmask = xilinx_cpm_unmask_event_irq,
276 };
277
xilinx_cpm_pcie_event_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)278 static int xilinx_cpm_pcie_event_map(struct irq_domain *domain,
279 unsigned int irq, irq_hw_number_t hwirq)
280 {
281 irq_set_chip_and_handler(irq, &xilinx_cpm_event_irq_chip,
282 handle_level_irq);
283 irq_set_chip_data(irq, domain->host_data);
284 irq_set_status_flags(irq, IRQ_LEVEL);
285 return 0;
286 }
287
288 static const struct irq_domain_ops event_domain_ops = {
289 .map = xilinx_cpm_pcie_event_map,
290 };
291
xilinx_cpm_pcie_event_flow(struct irq_desc * desc)292 static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
293 {
294 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
295 struct irq_chip *chip = irq_desc_get_chip(desc);
296 unsigned long val;
297 int i;
298
299 chained_irq_enter(chip, desc);
300 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR);
301 val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
302 for_each_set_bit(i, &val, 32)
303 generic_handle_domain_irq(port->cpm_domain, i);
304 pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
305
306 if (port->variant->version == CPM5) {
307 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
308 if (val)
309 writel_relaxed(val, port->cpm_base +
310 XILINX_CPM_PCIE_IR_STATUS);
311 }
312
313 /*
314 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
315 * CPM SLCR block.
316 */
317 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
318 if (val)
319 writel_relaxed(val,
320 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
321
322 chained_irq_exit(chip, desc);
323 }
324
325 #define _IC(x, s) \
326 [XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s }
327
328 static const struct {
329 const char *sym;
330 const char *str;
331 } intr_cause[32] = {
332 _IC(LINK_DOWN, "Link Down"),
333 _IC(HOT_RESET, "Hot reset"),
334 _IC(CFG_TIMEOUT, "ECAM access timeout"),
335 _IC(CORRECTABLE, "Correctable error message"),
336 _IC(NONFATAL, "Non fatal error message"),
337 _IC(FATAL, "Fatal error message"),
338 _IC(SLV_UNSUPP, "Slave unsupported request"),
339 _IC(SLV_UNEXP, "Slave unexpected completion"),
340 _IC(SLV_COMPL, "Slave completion timeout"),
341 _IC(SLV_ERRP, "Slave Error Poison"),
342 _IC(SLV_CMPABT, "Slave Completer Abort"),
343 _IC(SLV_ILLBUR, "Slave Illegal Burst"),
344 _IC(MST_DECERR, "Master decode error"),
345 _IC(MST_SLVERR, "Master slave error"),
346 _IC(CFG_PCIE_TIMEOUT, "PCIe ECAM access timeout"),
347 _IC(CFG_ERR_POISON, "ECAM poisoned completion received"),
348 _IC(PME_TO_ACK_RCVD, "PME_TO_ACK message received"),
349 _IC(PM_PME_RCVD, "PM_PME message received"),
350 _IC(SLV_PCIE_TIMEOUT, "PCIe completion timeout received"),
351 };
352
xilinx_cpm_pcie_intr_handler(int irq,void * dev_id)353 static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id)
354 {
355 struct xilinx_cpm_pcie *port = dev_id;
356 struct device *dev = port->dev;
357 struct irq_data *d;
358
359 d = irq_domain_get_irq_data(port->cpm_domain, irq);
360
361 switch (d->hwirq) {
362 case XILINX_CPM_PCIE_INTR_CORRECTABLE:
363 case XILINX_CPM_PCIE_INTR_NONFATAL:
364 case XILINX_CPM_PCIE_INTR_FATAL:
365 cpm_pcie_clear_err_interrupts(port);
366 fallthrough;
367
368 default:
369 if (intr_cause[d->hwirq].str)
370 dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
371 else
372 dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq);
373 }
374
375 return IRQ_HANDLED;
376 }
377
xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie * port)378 static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port)
379 {
380 if (port->intx_domain) {
381 irq_domain_remove(port->intx_domain);
382 port->intx_domain = NULL;
383 }
384
385 if (port->cpm_domain) {
386 irq_domain_remove(port->cpm_domain);
387 port->cpm_domain = NULL;
388 }
389 }
390
391 /**
392 * xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain
393 * @port: PCIe port information
394 *
395 * Return: '0' on success and error value on failure
396 */
xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie * port)397 static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port)
398 {
399 struct device *dev = port->dev;
400 struct device_node *node = dev->of_node;
401 struct device_node *pcie_intc_node;
402
403 /* Setup INTx */
404 pcie_intc_node = of_get_next_child(node, NULL);
405 if (!pcie_intc_node) {
406 dev_err(dev, "No PCIe Intc node found\n");
407 return -EINVAL;
408 }
409
410 port->cpm_domain = irq_domain_add_linear(pcie_intc_node, 32,
411 &event_domain_ops,
412 port);
413 if (!port->cpm_domain)
414 goto out;
415
416 irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS);
417
418 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
419 &intx_domain_ops,
420 port);
421 if (!port->intx_domain)
422 goto out;
423
424 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
425
426 of_node_put(pcie_intc_node);
427 raw_spin_lock_init(&port->lock);
428
429 return 0;
430 out:
431 xilinx_cpm_free_irq_domains(port);
432 of_node_put(pcie_intc_node);
433 dev_err(dev, "Failed to allocate IRQ domains\n");
434
435 return -ENOMEM;
436 }
437
xilinx_cpm_setup_irq(struct xilinx_cpm_pcie * port)438 static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port)
439 {
440 struct device *dev = port->dev;
441 struct platform_device *pdev = to_platform_device(dev);
442 int i, irq;
443
444 port->irq = platform_get_irq(pdev, 0);
445 if (port->irq < 0)
446 return port->irq;
447
448 for (i = 0; i < ARRAY_SIZE(intr_cause); i++) {
449 int err;
450
451 if (!intr_cause[i].str)
452 continue;
453
454 irq = irq_create_mapping(port->cpm_domain, i);
455 if (!irq) {
456 dev_err(dev, "Failed to map interrupt\n");
457 return -ENXIO;
458 }
459
460 err = devm_request_irq(dev, irq, xilinx_cpm_pcie_intr_handler,
461 0, intr_cause[i].sym, port);
462 if (err) {
463 dev_err(dev, "Failed to request IRQ %d\n", irq);
464 return err;
465 }
466 }
467
468 port->intx_irq = irq_create_mapping(port->cpm_domain,
469 XILINX_CPM_PCIE_INTR_INTX);
470 if (!port->intx_irq) {
471 dev_err(dev, "Failed to map INTx interrupt\n");
472 return -ENXIO;
473 }
474
475 /* Plug the INTx chained handler */
476 irq_set_chained_handler_and_data(port->intx_irq,
477 xilinx_cpm_pcie_intx_flow, port);
478
479 /* Plug the main event chained handler */
480 irq_set_chained_handler_and_data(port->irq,
481 xilinx_cpm_pcie_event_flow, port);
482
483 return 0;
484 }
485
486 /**
487 * xilinx_cpm_pcie_init_port - Initialize hardware
488 * @port: PCIe port information
489 */
xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie * port)490 static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
491 {
492 if (cpm_pcie_link_up(port))
493 dev_info(port->dev, "PCIe Link is UP\n");
494 else
495 dev_info(port->dev, "PCIe Link is DOWN\n");
496
497 /* Disable all interrupts */
498 pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
499 XILINX_CPM_PCIE_REG_IMR);
500
501 /* Clear pending interrupts */
502 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) &
503 XILINX_CPM_PCIE_IMR_ALL_MASK,
504 XILINX_CPM_PCIE_REG_IDR);
505
506 /*
507 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
508 * CPM SLCR block.
509 */
510 writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
511 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
512
513 if (port->variant->version == CPM5) {
514 writel(XILINX_CPM_PCIE_IR_LOCAL,
515 port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
516 }
517
518 /* Enable the Bridge enable bit */
519 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
520 XILINX_CPM_PCIE_REG_RPSC_BEN,
521 XILINX_CPM_PCIE_REG_RPSC);
522 }
523
524 /**
525 * xilinx_cpm_pcie_parse_dt - Parse Device tree
526 * @port: PCIe port information
527 * @bus_range: Bus resource
528 *
529 * Return: '0' on success and error value on failure
530 */
xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie * port,struct resource * bus_range)531 static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
532 struct resource *bus_range)
533 {
534 struct device *dev = port->dev;
535 struct platform_device *pdev = to_platform_device(dev);
536 struct resource *res;
537
538 port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
539 "cpm_slcr");
540 if (IS_ERR(port->cpm_base))
541 return PTR_ERR(port->cpm_base);
542
543 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
544 if (!res)
545 return -ENXIO;
546
547 port->cfg = pci_ecam_create(dev, res, bus_range,
548 &pci_generic_ecam_ops);
549 if (IS_ERR(port->cfg))
550 return PTR_ERR(port->cfg);
551
552 if (port->variant->version == CPM5) {
553 port->reg_base = devm_platform_ioremap_resource_byname(pdev,
554 "cpm_csr");
555 if (IS_ERR(port->reg_base))
556 return PTR_ERR(port->reg_base);
557 } else {
558 port->reg_base = port->cfg->win;
559 }
560
561 return 0;
562 }
563
xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie * port)564 static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port)
565 {
566 irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL);
567 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
568 }
569
570 /**
571 * xilinx_cpm_pcie_probe - Probe function
572 * @pdev: Platform device pointer
573 *
574 * Return: '0' on success and error value on failure
575 */
xilinx_cpm_pcie_probe(struct platform_device * pdev)576 static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
577 {
578 struct xilinx_cpm_pcie *port;
579 struct device *dev = &pdev->dev;
580 struct pci_host_bridge *bridge;
581 struct resource_entry *bus;
582 int err;
583
584 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
585 if (!bridge)
586 return -ENODEV;
587
588 port = pci_host_bridge_priv(bridge);
589
590 port->dev = dev;
591
592 err = xilinx_cpm_pcie_init_irq_domain(port);
593 if (err)
594 return err;
595
596 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
597 if (!bus)
598 return -ENODEV;
599
600 port->variant = of_device_get_match_data(dev);
601
602 err = xilinx_cpm_pcie_parse_dt(port, bus->res);
603 if (err) {
604 dev_err(dev, "Parsing DT failed\n");
605 goto err_parse_dt;
606 }
607
608 xilinx_cpm_pcie_init_port(port);
609
610 err = xilinx_cpm_setup_irq(port);
611 if (err) {
612 dev_err(dev, "Failed to set up interrupts\n");
613 goto err_setup_irq;
614 }
615
616 bridge->sysdata = port->cfg;
617 bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
618
619 err = pci_host_probe(bridge);
620 if (err < 0)
621 goto err_host_bridge;
622
623 return 0;
624
625 err_host_bridge:
626 xilinx_cpm_free_interrupts(port);
627 err_setup_irq:
628 pci_ecam_free(port->cfg);
629 err_parse_dt:
630 xilinx_cpm_free_irq_domains(port);
631 return err;
632 }
633
634 static const struct xilinx_cpm_variant cpm_host = {
635 .version = CPM,
636 };
637
638 static const struct xilinx_cpm_variant cpm5_host = {
639 .version = CPM5,
640 };
641
642 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
643 {
644 .compatible = "xlnx,versal-cpm-host-1.00",
645 .data = &cpm_host,
646 },
647 {
648 .compatible = "xlnx,versal-cpm5-host",
649 .data = &cpm5_host,
650 },
651 {}
652 };
653
654 static struct platform_driver xilinx_cpm_pcie_driver = {
655 .driver = {
656 .name = "xilinx-cpm-pcie",
657 .of_match_table = xilinx_cpm_pcie_of_match,
658 .suppress_bind_attrs = true,
659 },
660 .probe = xilinx_cpm_pcie_probe,
661 };
662
663 builtin_platform_driver(xilinx_cpm_pcie_driver);
664