1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/of_pci.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 22 #include "../pci.h" 23 #include "pcie-rockchip.h" 24 25 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 26 { 27 struct device *dev = rockchip->dev; 28 struct platform_device *pdev = to_platform_device(dev); 29 struct device_node *node = dev->of_node; 30 struct resource *regs; 31 int err; 32 33 if (rockchip->is_rc) { 34 regs = platform_get_resource_byname(pdev, 35 IORESOURCE_MEM, 36 "axi-base"); 37 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); 38 if (IS_ERR(rockchip->reg_base)) 39 return PTR_ERR(rockchip->reg_base); 40 } else { 41 rockchip->mem_res = 42 platform_get_resource_byname(pdev, IORESOURCE_MEM, 43 "mem-base"); 44 if (!rockchip->mem_res) 45 return -EINVAL; 46 } 47 48 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 49 "apb-base"); 50 rockchip->apb_base = devm_ioremap_resource(dev, regs); 51 if (IS_ERR(rockchip->apb_base)) 52 return PTR_ERR(rockchip->apb_base); 53 54 err = rockchip_pcie_get_phys(rockchip); 55 if (err) 56 return err; 57 58 rockchip->lanes = 1; 59 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); 60 if (!err && (rockchip->lanes == 0 || 61 rockchip->lanes == 3 || 62 rockchip->lanes > 4)) { 63 dev_warn(dev, "invalid num-lanes, default to use one lane\n"); 64 rockchip->lanes = 1; 65 } 66 67 rockchip->link_gen = of_pci_get_max_link_speed(node); 68 if (rockchip->link_gen < 0 || rockchip->link_gen > 2) 69 rockchip->link_gen = 2; 70 71 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); 72 if (IS_ERR(rockchip->core_rst)) { 73 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) 74 dev_err(dev, "missing core reset property in node\n"); 75 return PTR_ERR(rockchip->core_rst); 76 } 77 78 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); 79 if (IS_ERR(rockchip->mgmt_rst)) { 80 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) 81 dev_err(dev, "missing mgmt reset property in node\n"); 82 return PTR_ERR(rockchip->mgmt_rst); 83 } 84 85 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, 86 "mgmt-sticky"); 87 if (IS_ERR(rockchip->mgmt_sticky_rst)) { 88 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) 89 dev_err(dev, "missing mgmt-sticky reset property in node\n"); 90 return PTR_ERR(rockchip->mgmt_sticky_rst); 91 } 92 93 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); 94 if (IS_ERR(rockchip->pipe_rst)) { 95 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) 96 dev_err(dev, "missing pipe reset property in node\n"); 97 return PTR_ERR(rockchip->pipe_rst); 98 } 99 100 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); 101 if (IS_ERR(rockchip->pm_rst)) { 102 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) 103 dev_err(dev, "missing pm reset property in node\n"); 104 return PTR_ERR(rockchip->pm_rst); 105 } 106 107 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); 108 if (IS_ERR(rockchip->pclk_rst)) { 109 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) 110 dev_err(dev, "missing pclk reset property in node\n"); 111 return PTR_ERR(rockchip->pclk_rst); 112 } 113 114 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); 115 if (IS_ERR(rockchip->aclk_rst)) { 116 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) 117 dev_err(dev, "missing aclk reset property in node\n"); 118 return PTR_ERR(rockchip->aclk_rst); 119 } 120 121 if (rockchip->is_rc) { 122 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH); 123 if (IS_ERR(rockchip->ep_gpio)) { 124 dev_err(dev, "missing ep-gpios property in node\n"); 125 return PTR_ERR(rockchip->ep_gpio); 126 } 127 } 128 129 rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); 130 if (IS_ERR(rockchip->aclk_pcie)) { 131 dev_err(dev, "aclk clock not found\n"); 132 return PTR_ERR(rockchip->aclk_pcie); 133 } 134 135 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); 136 if (IS_ERR(rockchip->aclk_perf_pcie)) { 137 dev_err(dev, "aclk_perf clock not found\n"); 138 return PTR_ERR(rockchip->aclk_perf_pcie); 139 } 140 141 rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); 142 if (IS_ERR(rockchip->hclk_pcie)) { 143 dev_err(dev, "hclk clock not found\n"); 144 return PTR_ERR(rockchip->hclk_pcie); 145 } 146 147 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); 148 if (IS_ERR(rockchip->clk_pcie_pm)) { 149 dev_err(dev, "pm clock not found\n"); 150 return PTR_ERR(rockchip->clk_pcie_pm); 151 } 152 153 return 0; 154 } 155 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); 156 157 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 158 { 159 struct device *dev = rockchip->dev; 160 int err, i; 161 u32 regs; 162 163 err = reset_control_assert(rockchip->aclk_rst); 164 if (err) { 165 dev_err(dev, "assert aclk_rst err %d\n", err); 166 return err; 167 } 168 169 err = reset_control_assert(rockchip->pclk_rst); 170 if (err) { 171 dev_err(dev, "assert pclk_rst err %d\n", err); 172 return err; 173 } 174 175 err = reset_control_assert(rockchip->pm_rst); 176 if (err) { 177 dev_err(dev, "assert pm_rst err %d\n", err); 178 return err; 179 } 180 181 for (i = 0; i < MAX_LANE_NUM; i++) { 182 err = phy_init(rockchip->phys[i]); 183 if (err) { 184 dev_err(dev, "init phy%d err %d\n", i, err); 185 goto err_exit_phy; 186 } 187 } 188 189 err = reset_control_assert(rockchip->core_rst); 190 if (err) { 191 dev_err(dev, "assert core_rst err %d\n", err); 192 goto err_exit_phy; 193 } 194 195 err = reset_control_assert(rockchip->mgmt_rst); 196 if (err) { 197 dev_err(dev, "assert mgmt_rst err %d\n", err); 198 goto err_exit_phy; 199 } 200 201 err = reset_control_assert(rockchip->mgmt_sticky_rst); 202 if (err) { 203 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); 204 goto err_exit_phy; 205 } 206 207 err = reset_control_assert(rockchip->pipe_rst); 208 if (err) { 209 dev_err(dev, "assert pipe_rst err %d\n", err); 210 goto err_exit_phy; 211 } 212 213 udelay(10); 214 215 err = reset_control_deassert(rockchip->pm_rst); 216 if (err) { 217 dev_err(dev, "deassert pm_rst err %d\n", err); 218 goto err_exit_phy; 219 } 220 221 err = reset_control_deassert(rockchip->aclk_rst); 222 if (err) { 223 dev_err(dev, "deassert aclk_rst err %d\n", err); 224 goto err_exit_phy; 225 } 226 227 err = reset_control_deassert(rockchip->pclk_rst); 228 if (err) { 229 dev_err(dev, "deassert pclk_rst err %d\n", err); 230 goto err_exit_phy; 231 } 232 233 if (rockchip->link_gen == 2) 234 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, 235 PCIE_CLIENT_CONFIG); 236 else 237 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, 238 PCIE_CLIENT_CONFIG); 239 240 regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | 241 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); 242 243 if (rockchip->is_rc) 244 regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; 245 else 246 regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; 247 248 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); 249 250 for (i = 0; i < MAX_LANE_NUM; i++) { 251 err = phy_power_on(rockchip->phys[i]); 252 if (err) { 253 dev_err(dev, "power on phy%d err %d\n", i, err); 254 goto err_power_off_phy; 255 } 256 } 257 258 /* 259 * Please don't reorder the deassert sequence of the following 260 * four reset pins. 261 */ 262 err = reset_control_deassert(rockchip->mgmt_sticky_rst); 263 if (err) { 264 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); 265 goto err_power_off_phy; 266 } 267 268 err = reset_control_deassert(rockchip->core_rst); 269 if (err) { 270 dev_err(dev, "deassert core_rst err %d\n", err); 271 goto err_power_off_phy; 272 } 273 274 err = reset_control_deassert(rockchip->mgmt_rst); 275 if (err) { 276 dev_err(dev, "deassert mgmt_rst err %d\n", err); 277 goto err_power_off_phy; 278 } 279 280 err = reset_control_deassert(rockchip->pipe_rst); 281 if (err) { 282 dev_err(dev, "deassert pipe_rst err %d\n", err); 283 goto err_power_off_phy; 284 } 285 286 return 0; 287 err_power_off_phy: 288 while (i--) 289 phy_power_off(rockchip->phys[i]); 290 i = MAX_LANE_NUM; 291 err_exit_phy: 292 while (i--) 293 phy_exit(rockchip->phys[i]); 294 return err; 295 } 296 EXPORT_SYMBOL_GPL(rockchip_pcie_init_port); 297 298 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) 299 { 300 struct device *dev = rockchip->dev; 301 struct phy *phy; 302 char *name; 303 u32 i; 304 305 phy = devm_phy_get(dev, "pcie-phy"); 306 if (!IS_ERR(phy)) { 307 rockchip->legacy_phy = true; 308 rockchip->phys[0] = phy; 309 dev_warn(dev, "legacy phy model is deprecated!\n"); 310 return 0; 311 } 312 313 if (PTR_ERR(phy) == -EPROBE_DEFER) 314 return PTR_ERR(phy); 315 316 dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n"); 317 318 for (i = 0; i < MAX_LANE_NUM; i++) { 319 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i); 320 if (!name) 321 return -ENOMEM; 322 323 phy = devm_of_phy_get(dev, dev->of_node, name); 324 kfree(name); 325 326 if (IS_ERR(phy)) { 327 if (PTR_ERR(phy) != -EPROBE_DEFER) 328 dev_err(dev, "missing phy for lane %d: %ld\n", 329 i, PTR_ERR(phy)); 330 return PTR_ERR(phy); 331 } 332 333 rockchip->phys[i] = phy; 334 } 335 336 return 0; 337 } 338 EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys); 339 340 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) 341 { 342 int i; 343 344 for (i = 0; i < MAX_LANE_NUM; i++) { 345 /* inactive lanes are already powered off */ 346 if (rockchip->lanes_map & BIT(i)) 347 phy_power_off(rockchip->phys[i]); 348 phy_exit(rockchip->phys[i]); 349 } 350 } 351 EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys); 352 353 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) 354 { 355 struct device *dev = rockchip->dev; 356 int err; 357 358 err = clk_prepare_enable(rockchip->aclk_pcie); 359 if (err) { 360 dev_err(dev, "unable to enable aclk_pcie clock\n"); 361 return err; 362 } 363 364 err = clk_prepare_enable(rockchip->aclk_perf_pcie); 365 if (err) { 366 dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); 367 goto err_aclk_perf_pcie; 368 } 369 370 err = clk_prepare_enable(rockchip->hclk_pcie); 371 if (err) { 372 dev_err(dev, "unable to enable hclk_pcie clock\n"); 373 goto err_hclk_pcie; 374 } 375 376 err = clk_prepare_enable(rockchip->clk_pcie_pm); 377 if (err) { 378 dev_err(dev, "unable to enable clk_pcie_pm clock\n"); 379 goto err_clk_pcie_pm; 380 } 381 382 return 0; 383 384 err_clk_pcie_pm: 385 clk_disable_unprepare(rockchip->hclk_pcie); 386 err_hclk_pcie: 387 clk_disable_unprepare(rockchip->aclk_perf_pcie); 388 err_aclk_perf_pcie: 389 clk_disable_unprepare(rockchip->aclk_pcie); 390 return err; 391 } 392 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); 393 394 void rockchip_pcie_disable_clocks(void *data) 395 { 396 struct rockchip_pcie *rockchip = data; 397 398 clk_disable_unprepare(rockchip->clk_pcie_pm); 399 clk_disable_unprepare(rockchip->hclk_pcie); 400 clk_disable_unprepare(rockchip->aclk_perf_pcie); 401 clk_disable_unprepare(rockchip->aclk_pcie); 402 } 403 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); 404 405 void rockchip_pcie_cfg_configuration_accesses( 406 struct rockchip_pcie *rockchip, u32 type) 407 { 408 u32 ob_desc_0; 409 410 /* Configuration Accesses for region 0 */ 411 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); 412 413 rockchip_pcie_write(rockchip, 414 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), 415 PCIE_CORE_OB_REGION_ADDR0); 416 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, 417 PCIE_CORE_OB_REGION_ADDR1); 418 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0); 419 ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK); 420 ob_desc_0 |= (type | (0x1 << 23)); 421 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); 422 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); 423 } 424 EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses); 425