1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14 #include <linux/bitrev.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/of_pci.h> 30 #include <linux/of_platform.h> 31 #include <linux/of_irq.h> 32 #include <linux/pci.h> 33 #include <linux/pci_ids.h> 34 #include <linux/phy/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/reset.h> 37 #include <linux/regmap.h> 38 39 #include "../pci.h" 40 #include "pcie-rockchip.h" 41 42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) 43 { 44 u32 status; 45 46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 47 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); 48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 49 } 50 51 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) 52 { 53 u32 status; 54 55 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 56 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; 57 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 58 } 59 60 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) 61 { 62 u32 val; 63 64 /* Update Tx credit maximum update interval */ 65 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); 66 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; 67 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ 68 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); 69 } 70 71 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, 72 struct pci_bus *bus, int dev) 73 { 74 /* access only one slot on each root port */ 75 if (bus->number == rockchip->root_bus_nr && dev > 0) 76 return 0; 77 78 /* 79 * do not read more than one device on the bus directly attached 80 * to RC's downstream side. 81 */ 82 if (bus->primary == rockchip->root_bus_nr && dev > 0) 83 return 0; 84 85 return 1; 86 } 87 88 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip) 89 { 90 u32 val; 91 u8 map; 92 93 if (rockchip->legacy_phy) 94 return GENMASK(MAX_LANE_NUM - 1, 0); 95 96 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP); 97 map = val & PCIE_CORE_LANE_MAP_MASK; 98 99 /* The link may be using a reverse-indexed mapping. */ 100 if (val & PCIE_CORE_LANE_MAP_REVERSE) 101 map = bitrev8(map) >> 4; 102 103 return map; 104 } 105 106 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip, 107 int where, int size, u32 *val) 108 { 109 void __iomem *addr; 110 111 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; 112 113 if (!IS_ALIGNED((uintptr_t)addr, size)) { 114 *val = 0; 115 return PCIBIOS_BAD_REGISTER_NUMBER; 116 } 117 118 if (size == 4) { 119 *val = readl(addr); 120 } else if (size == 2) { 121 *val = readw(addr); 122 } else if (size == 1) { 123 *val = readb(addr); 124 } else { 125 *val = 0; 126 return PCIBIOS_BAD_REGISTER_NUMBER; 127 } 128 return PCIBIOS_SUCCESSFUL; 129 } 130 131 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, 132 int where, int size, u32 val) 133 { 134 u32 mask, tmp, offset; 135 void __iomem *addr; 136 137 offset = where & ~0x3; 138 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; 139 140 if (size == 4) { 141 writel(val, addr); 142 return PCIBIOS_SUCCESSFUL; 143 } 144 145 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); 146 147 /* 148 * N.B. This read/modify/write isn't safe in general because it can 149 * corrupt RW1C bits in adjacent registers. But the hardware 150 * doesn't support smaller writes. 151 */ 152 tmp = readl(addr) & mask; 153 tmp |= val << ((where & 0x3) * 8); 154 writel(tmp, addr); 155 156 return PCIBIOS_SUCCESSFUL; 157 } 158 159 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, 160 struct pci_bus *bus, u32 devfn, 161 int where, int size, u32 *val) 162 { 163 u32 busdev; 164 165 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 166 PCI_FUNC(devfn), where); 167 168 if (!IS_ALIGNED(busdev, size)) { 169 *val = 0; 170 return PCIBIOS_BAD_REGISTER_NUMBER; 171 } 172 173 if (bus->parent->number == rockchip->root_bus_nr) 174 rockchip_pcie_cfg_configuration_accesses(rockchip, 175 AXI_WRAPPER_TYPE0_CFG); 176 else 177 rockchip_pcie_cfg_configuration_accesses(rockchip, 178 AXI_WRAPPER_TYPE1_CFG); 179 180 if (size == 4) { 181 *val = readl(rockchip->reg_base + busdev); 182 } else if (size == 2) { 183 *val = readw(rockchip->reg_base + busdev); 184 } else if (size == 1) { 185 *val = readb(rockchip->reg_base + busdev); 186 } else { 187 *val = 0; 188 return PCIBIOS_BAD_REGISTER_NUMBER; 189 } 190 return PCIBIOS_SUCCESSFUL; 191 } 192 193 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, 194 struct pci_bus *bus, u32 devfn, 195 int where, int size, u32 val) 196 { 197 u32 busdev; 198 199 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 200 PCI_FUNC(devfn), where); 201 if (!IS_ALIGNED(busdev, size)) 202 return PCIBIOS_BAD_REGISTER_NUMBER; 203 204 if (bus->parent->number == rockchip->root_bus_nr) 205 rockchip_pcie_cfg_configuration_accesses(rockchip, 206 AXI_WRAPPER_TYPE0_CFG); 207 else 208 rockchip_pcie_cfg_configuration_accesses(rockchip, 209 AXI_WRAPPER_TYPE1_CFG); 210 211 if (size == 4) 212 writel(val, rockchip->reg_base + busdev); 213 else if (size == 2) 214 writew(val, rockchip->reg_base + busdev); 215 else if (size == 1) 216 writeb(val, rockchip->reg_base + busdev); 217 else 218 return PCIBIOS_BAD_REGISTER_NUMBER; 219 220 return PCIBIOS_SUCCESSFUL; 221 } 222 223 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 224 int size, u32 *val) 225 { 226 struct rockchip_pcie *rockchip = bus->sysdata; 227 228 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) { 229 *val = 0xffffffff; 230 return PCIBIOS_DEVICE_NOT_FOUND; 231 } 232 233 if (bus->number == rockchip->root_bus_nr) 234 return rockchip_pcie_rd_own_conf(rockchip, where, size, val); 235 236 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, 237 val); 238 } 239 240 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 241 int where, int size, u32 val) 242 { 243 struct rockchip_pcie *rockchip = bus->sysdata; 244 245 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) 246 return PCIBIOS_DEVICE_NOT_FOUND; 247 248 if (bus->number == rockchip->root_bus_nr) 249 return rockchip_pcie_wr_own_conf(rockchip, where, size, val); 250 251 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, 252 val); 253 } 254 255 static struct pci_ops rockchip_pcie_ops = { 256 .read = rockchip_pcie_rd_conf, 257 .write = rockchip_pcie_wr_conf, 258 }; 259 260 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) 261 { 262 int curr; 263 u32 status, scale, power; 264 265 if (IS_ERR(rockchip->vpcie3v3)) 266 return; 267 268 /* 269 * Set RC's captured slot power limit and scale if 270 * vpcie3v3 available. The default values are both zero 271 * which means the software should set these two according 272 * to the actual power supply. 273 */ 274 curr = regulator_get_current_limit(rockchip->vpcie3v3); 275 if (curr <= 0) 276 return; 277 278 scale = 3; /* 0.001x */ 279 curr = curr / 1000; /* convert to mA */ 280 power = (curr * 3300) / 1000; /* milliwatt */ 281 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { 282 if (!scale) { 283 dev_warn(rockchip->dev, "invalid power supply\n"); 284 return; 285 } 286 scale--; 287 power = power / 10; 288 } 289 290 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); 291 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | 292 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); 293 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); 294 } 295 296 /** 297 * rockchip_pcie_host_init_port - Initialize hardware 298 * @rockchip: PCIe port information 299 */ 300 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 301 { 302 struct device *dev = rockchip->dev; 303 int err, i = MAX_LANE_NUM; 304 u32 status; 305 306 gpiod_set_value_cansleep(rockchip->ep_gpio, 0); 307 308 err = rockchip_pcie_init_port(rockchip); 309 if (err) 310 return err; 311 312 /* Fix the transmitted FTS count desired to exit from L0s. */ 313 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); 314 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) | 315 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT); 316 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1); 317 318 rockchip_pcie_set_power_limit(rockchip); 319 320 /* Set RC's clock architecture as common clock */ 321 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 322 status |= PCI_EXP_LNKSTA_SLC << 16; 323 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 324 325 /* Set RC's RCB to 128 */ 326 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 327 status |= PCI_EXP_LNKCTL_RCB; 328 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 329 330 /* Enable Gen1 training */ 331 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, 332 PCIE_CLIENT_CONFIG); 333 334 gpiod_set_value_cansleep(rockchip->ep_gpio, 1); 335 336 /* 500ms timeout value should be enough for Gen1/2 training */ 337 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, 338 status, PCIE_LINK_UP(status), 20, 339 500 * USEC_PER_MSEC); 340 if (err) { 341 dev_err(dev, "PCIe link training gen1 timeout!\n"); 342 goto err_power_off_phy; 343 } 344 345 if (rockchip->link_gen == 2) { 346 /* 347 * Enable retrain for gen2. This should be configured only after 348 * gen1 finished. 349 */ 350 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 351 status |= PCI_EXP_LNKCTL_RL; 352 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 353 354 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, 355 status, PCIE_LINK_IS_GEN2(status), 20, 356 500 * USEC_PER_MSEC); 357 if (err) 358 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n"); 359 } 360 361 /* Check the final link width from negotiated lane counter from MGMT */ 362 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); 363 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >> 364 PCIE_CORE_PL_CONF_LANE_SHIFT); 365 dev_dbg(dev, "current link width is x%d\n", status); 366 367 /* Power off unused lane(s) */ 368 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip); 369 for (i = 0; i < MAX_LANE_NUM; i++) { 370 if (!(rockchip->lanes_map & BIT(i))) { 371 dev_dbg(dev, "idling lane %d\n", i); 372 phy_power_off(rockchip->phys[i]); 373 } 374 } 375 376 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, 377 PCIE_CORE_CONFIG_VENDOR); 378 rockchip_pcie_write(rockchip, 379 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT, 380 PCIE_RC_CONFIG_RID_CCR); 381 382 /* Clear THP cap's next cap pointer to remove L1 substate cap */ 383 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP); 384 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 385 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP); 386 387 /* Clear L0s from RC's link cap */ 388 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { 389 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); 390 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; 391 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); 392 } 393 394 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); 395 status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; 396 status |= PCIE_RC_CONFIG_DCSR_MPS_256; 397 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); 398 399 return 0; 400 err_power_off_phy: 401 while (i--) 402 phy_power_off(rockchip->phys[i]); 403 i = MAX_LANE_NUM; 404 while (i--) 405 phy_exit(rockchip->phys[i]); 406 return err; 407 } 408 409 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) 410 { 411 struct rockchip_pcie *rockchip = arg; 412 struct device *dev = rockchip->dev; 413 u32 reg; 414 u32 sub_reg; 415 416 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 417 if (reg & PCIE_CLIENT_INT_LOCAL) { 418 dev_dbg(dev, "local interrupt received\n"); 419 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS); 420 if (sub_reg & PCIE_CORE_INT_PRFPE) 421 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n"); 422 423 if (sub_reg & PCIE_CORE_INT_CRFPE) 424 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n"); 425 426 if (sub_reg & PCIE_CORE_INT_RRPE) 427 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n"); 428 429 if (sub_reg & PCIE_CORE_INT_PRFO) 430 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n"); 431 432 if (sub_reg & PCIE_CORE_INT_CRFO) 433 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n"); 434 435 if (sub_reg & PCIE_CORE_INT_RT) 436 dev_dbg(dev, "replay timer timed out\n"); 437 438 if (sub_reg & PCIE_CORE_INT_RTR) 439 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n"); 440 441 if (sub_reg & PCIE_CORE_INT_PE) 442 dev_dbg(dev, "phy error detected on receive side\n"); 443 444 if (sub_reg & PCIE_CORE_INT_MTR) 445 dev_dbg(dev, "malformed TLP received from the link\n"); 446 447 if (sub_reg & PCIE_CORE_INT_UCR) 448 dev_dbg(dev, "malformed TLP received from the link\n"); 449 450 if (sub_reg & PCIE_CORE_INT_FCE) 451 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n"); 452 453 if (sub_reg & PCIE_CORE_INT_CT) 454 dev_dbg(dev, "a request timed out waiting for completion\n"); 455 456 if (sub_reg & PCIE_CORE_INT_UTC) 457 dev_dbg(dev, "unmapped TC error\n"); 458 459 if (sub_reg & PCIE_CORE_INT_MMVC) 460 dev_dbg(dev, "MSI mask register changes\n"); 461 462 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS); 463 } else if (reg & PCIE_CLIENT_INT_PHY) { 464 dev_dbg(dev, "phy link changes\n"); 465 rockchip_pcie_update_txcredit_mui(rockchip); 466 rockchip_pcie_clr_bw_int(rockchip); 467 } 468 469 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL, 470 PCIE_CLIENT_INT_STATUS); 471 472 return IRQ_HANDLED; 473 } 474 475 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg) 476 { 477 struct rockchip_pcie *rockchip = arg; 478 struct device *dev = rockchip->dev; 479 u32 reg; 480 481 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 482 if (reg & PCIE_CLIENT_INT_LEGACY_DONE) 483 dev_dbg(dev, "legacy done interrupt received\n"); 484 485 if (reg & PCIE_CLIENT_INT_MSG) 486 dev_dbg(dev, "message done interrupt received\n"); 487 488 if (reg & PCIE_CLIENT_INT_HOT_RST) 489 dev_dbg(dev, "hot reset interrupt received\n"); 490 491 if (reg & PCIE_CLIENT_INT_DPA) 492 dev_dbg(dev, "dpa interrupt received\n"); 493 494 if (reg & PCIE_CLIENT_INT_FATAL_ERR) 495 dev_dbg(dev, "fatal error interrupt received\n"); 496 497 if (reg & PCIE_CLIENT_INT_NFATAL_ERR) 498 dev_dbg(dev, "no fatal error interrupt received\n"); 499 500 if (reg & PCIE_CLIENT_INT_CORR_ERR) 501 dev_dbg(dev, "correctable error interrupt received\n"); 502 503 if (reg & PCIE_CLIENT_INT_PHY) 504 dev_dbg(dev, "phy interrupt received\n"); 505 506 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE | 507 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST | 508 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR | 509 PCIE_CLIENT_INT_NFATAL_ERR | 510 PCIE_CLIENT_INT_CORR_ERR | 511 PCIE_CLIENT_INT_PHY), 512 PCIE_CLIENT_INT_STATUS); 513 514 return IRQ_HANDLED; 515 } 516 517 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) 518 { 519 struct irq_chip *chip = irq_desc_get_chip(desc); 520 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); 521 struct device *dev = rockchip->dev; 522 u32 reg; 523 u32 hwirq; 524 u32 virq; 525 526 chained_irq_enter(chip, desc); 527 528 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 529 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT; 530 531 while (reg) { 532 hwirq = ffs(reg) - 1; 533 reg &= ~BIT(hwirq); 534 535 virq = irq_find_mapping(rockchip->irq_domain, hwirq); 536 if (virq) 537 generic_handle_irq(virq); 538 else 539 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); 540 } 541 542 chained_irq_exit(chip, desc); 543 } 544 545 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip) 546 { 547 int irq, err; 548 struct device *dev = rockchip->dev; 549 struct platform_device *pdev = to_platform_device(dev); 550 551 irq = platform_get_irq_byname(pdev, "sys"); 552 if (irq < 0) { 553 dev_err(dev, "missing sys IRQ resource\n"); 554 return irq; 555 } 556 557 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler, 558 IRQF_SHARED, "pcie-sys", rockchip); 559 if (err) { 560 dev_err(dev, "failed to request PCIe subsystem IRQ\n"); 561 return err; 562 } 563 564 irq = platform_get_irq_byname(pdev, "legacy"); 565 if (irq < 0) { 566 dev_err(dev, "missing legacy IRQ resource\n"); 567 return irq; 568 } 569 570 irq_set_chained_handler_and_data(irq, 571 rockchip_pcie_legacy_int_handler, 572 rockchip); 573 574 irq = platform_get_irq_byname(pdev, "client"); 575 if (irq < 0) { 576 dev_err(dev, "missing client IRQ resource\n"); 577 return irq; 578 } 579 580 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler, 581 IRQF_SHARED, "pcie-client", rockchip); 582 if (err) { 583 dev_err(dev, "failed to request PCIe client IRQ\n"); 584 return err; 585 } 586 587 return 0; 588 } 589 590 /** 591 * rockchip_pcie_parse_host_dt - Parse Device Tree 592 * @rockchip: PCIe port information 593 * 594 * Return: '0' on success and error value on failure 595 */ 596 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip) 597 { 598 struct device *dev = rockchip->dev; 599 int err; 600 601 err = rockchip_pcie_parse_dt(rockchip); 602 if (err) 603 return err; 604 605 err = rockchip_pcie_setup_irq(rockchip); 606 if (err) 607 return err; 608 609 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v"); 610 if (IS_ERR(rockchip->vpcie12v)) { 611 if (PTR_ERR(rockchip->vpcie12v) == -EPROBE_DEFER) 612 return -EPROBE_DEFER; 613 dev_info(dev, "no vpcie12v regulator found\n"); 614 } 615 616 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); 617 if (IS_ERR(rockchip->vpcie3v3)) { 618 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER) 619 return -EPROBE_DEFER; 620 dev_info(dev, "no vpcie3v3 regulator found\n"); 621 } 622 623 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8"); 624 if (IS_ERR(rockchip->vpcie1v8)) { 625 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER) 626 return -EPROBE_DEFER; 627 dev_info(dev, "no vpcie1v8 regulator found\n"); 628 } 629 630 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9"); 631 if (IS_ERR(rockchip->vpcie0v9)) { 632 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER) 633 return -EPROBE_DEFER; 634 dev_info(dev, "no vpcie0v9 regulator found\n"); 635 } 636 637 return 0; 638 } 639 640 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) 641 { 642 struct device *dev = rockchip->dev; 643 int err; 644 645 if (!IS_ERR(rockchip->vpcie12v)) { 646 err = regulator_enable(rockchip->vpcie12v); 647 if (err) { 648 dev_err(dev, "fail to enable vpcie12v regulator\n"); 649 goto err_out; 650 } 651 } 652 653 if (!IS_ERR(rockchip->vpcie3v3)) { 654 err = regulator_enable(rockchip->vpcie3v3); 655 if (err) { 656 dev_err(dev, "fail to enable vpcie3v3 regulator\n"); 657 goto err_disable_12v; 658 } 659 } 660 661 if (!IS_ERR(rockchip->vpcie1v8)) { 662 err = regulator_enable(rockchip->vpcie1v8); 663 if (err) { 664 dev_err(dev, "fail to enable vpcie1v8 regulator\n"); 665 goto err_disable_3v3; 666 } 667 } 668 669 if (!IS_ERR(rockchip->vpcie0v9)) { 670 err = regulator_enable(rockchip->vpcie0v9); 671 if (err) { 672 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 673 goto err_disable_1v8; 674 } 675 } 676 677 return 0; 678 679 err_disable_1v8: 680 if (!IS_ERR(rockchip->vpcie1v8)) 681 regulator_disable(rockchip->vpcie1v8); 682 err_disable_3v3: 683 if (!IS_ERR(rockchip->vpcie3v3)) 684 regulator_disable(rockchip->vpcie3v3); 685 err_disable_12v: 686 if (!IS_ERR(rockchip->vpcie12v)) 687 regulator_disable(rockchip->vpcie12v); 688 err_out: 689 return err; 690 } 691 692 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip) 693 { 694 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) & 695 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK); 696 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT), 697 PCIE_CORE_INT_MASK); 698 699 rockchip_pcie_enable_bw_int(rockchip); 700 } 701 702 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 703 irq_hw_number_t hwirq) 704 { 705 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 706 irq_set_chip_data(irq, domain->host_data); 707 708 return 0; 709 } 710 711 static const struct irq_domain_ops intx_domain_ops = { 712 .map = rockchip_pcie_intx_map, 713 }; 714 715 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) 716 { 717 struct device *dev = rockchip->dev; 718 struct device_node *intc = of_get_next_child(dev->of_node, NULL); 719 720 if (!intc) { 721 dev_err(dev, "missing child interrupt-controller node\n"); 722 return -EINVAL; 723 } 724 725 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, 726 &intx_domain_ops, rockchip); 727 if (!rockchip->irq_domain) { 728 dev_err(dev, "failed to get a INTx IRQ domain\n"); 729 return -EINVAL; 730 } 731 732 return 0; 733 } 734 735 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, 736 int region_no, int type, u8 num_pass_bits, 737 u32 lower_addr, u32 upper_addr) 738 { 739 u32 ob_addr_0; 740 u32 ob_addr_1; 741 u32 ob_desc_0; 742 u32 aw_offset; 743 744 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM) 745 return -EINVAL; 746 if (num_pass_bits + 1 < 8) 747 return -EINVAL; 748 if (num_pass_bits > 63) 749 return -EINVAL; 750 if (region_no == 0) { 751 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits)) 752 return -EINVAL; 753 } 754 if (region_no != 0) { 755 if (AXI_REGION_SIZE < (2ULL << num_pass_bits)) 756 return -EINVAL; 757 } 758 759 aw_offset = (region_no << OB_REG_SIZE_SHIFT); 760 761 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS; 762 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR; 763 ob_addr_1 = upper_addr; 764 ob_desc_0 = (1 << 23 | type); 765 766 rockchip_pcie_write(rockchip, ob_addr_0, 767 PCIE_CORE_OB_REGION_ADDR0 + aw_offset); 768 rockchip_pcie_write(rockchip, ob_addr_1, 769 PCIE_CORE_OB_REGION_ADDR1 + aw_offset); 770 rockchip_pcie_write(rockchip, ob_desc_0, 771 PCIE_CORE_OB_REGION_DESC0 + aw_offset); 772 rockchip_pcie_write(rockchip, 0, 773 PCIE_CORE_OB_REGION_DESC1 + aw_offset); 774 775 return 0; 776 } 777 778 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, 779 int region_no, u8 num_pass_bits, 780 u32 lower_addr, u32 upper_addr) 781 { 782 u32 ib_addr_0; 783 u32 ib_addr_1; 784 u32 aw_offset; 785 786 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM) 787 return -EINVAL; 788 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED) 789 return -EINVAL; 790 if (num_pass_bits > 63) 791 return -EINVAL; 792 793 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT); 794 795 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS; 796 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR; 797 ib_addr_1 = upper_addr; 798 799 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset); 800 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset); 801 802 return 0; 803 } 804 805 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip) 806 { 807 struct device *dev = rockchip->dev; 808 int offset; 809 int err; 810 int reg_no; 811 812 rockchip_pcie_cfg_configuration_accesses(rockchip, 813 AXI_WRAPPER_TYPE0_CFG); 814 815 for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) { 816 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1, 817 AXI_WRAPPER_MEM_WRITE, 818 20 - 1, 819 rockchip->mem_bus_addr + 820 (reg_no << 20), 821 0); 822 if (err) { 823 dev_err(dev, "program RC mem outbound ATU failed\n"); 824 return err; 825 } 826 } 827 828 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0); 829 if (err) { 830 dev_err(dev, "program RC mem inbound ATU failed\n"); 831 return err; 832 } 833 834 offset = rockchip->mem_size >> 20; 835 for (reg_no = 0; reg_no < (rockchip->io_size >> 20); reg_no++) { 836 err = rockchip_pcie_prog_ob_atu(rockchip, 837 reg_no + 1 + offset, 838 AXI_WRAPPER_IO_WRITE, 839 20 - 1, 840 rockchip->io_bus_addr + 841 (reg_no << 20), 842 0); 843 if (err) { 844 dev_err(dev, "program RC io outbound ATU failed\n"); 845 return err; 846 } 847 } 848 849 /* assign message regions */ 850 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset, 851 AXI_WRAPPER_NOR_MSG, 852 20 - 1, 0, 0); 853 854 rockchip->msg_bus_addr = rockchip->mem_bus_addr + 855 ((reg_no + offset) << 20); 856 return err; 857 } 858 859 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip) 860 { 861 u32 value; 862 int err; 863 864 /* send PME_TURN_OFF message */ 865 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF); 866 867 /* read LTSSM and wait for falling into L2 link state */ 868 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0, 869 value, PCIE_LINK_IS_L2(value), 20, 870 jiffies_to_usecs(5 * HZ)); 871 if (err) { 872 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n"); 873 return err; 874 } 875 876 return 0; 877 } 878 879 static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) 880 { 881 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 882 int ret; 883 884 /* disable core and cli int since we don't need to ack PME_ACK */ 885 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) | 886 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK); 887 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK); 888 889 ret = rockchip_pcie_wait_l2(rockchip); 890 if (ret) { 891 rockchip_pcie_enable_interrupts(rockchip); 892 return ret; 893 } 894 895 rockchip_pcie_deinit_phys(rockchip); 896 897 rockchip_pcie_disable_clocks(rockchip); 898 899 if (!IS_ERR(rockchip->vpcie0v9)) 900 regulator_disable(rockchip->vpcie0v9); 901 902 return ret; 903 } 904 905 static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) 906 { 907 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 908 int err; 909 910 if (!IS_ERR(rockchip->vpcie0v9)) { 911 err = regulator_enable(rockchip->vpcie0v9); 912 if (err) { 913 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 914 return err; 915 } 916 } 917 918 err = rockchip_pcie_enable_clocks(rockchip); 919 if (err) 920 goto err_disable_0v9; 921 922 err = rockchip_pcie_host_init_port(rockchip); 923 if (err) 924 goto err_pcie_resume; 925 926 err = rockchip_pcie_cfg_atu(rockchip); 927 if (err) 928 goto err_err_deinit_port; 929 930 /* Need this to enter L1 again */ 931 rockchip_pcie_update_txcredit_mui(rockchip); 932 rockchip_pcie_enable_interrupts(rockchip); 933 934 return 0; 935 936 err_err_deinit_port: 937 rockchip_pcie_deinit_phys(rockchip); 938 err_pcie_resume: 939 rockchip_pcie_disable_clocks(rockchip); 940 err_disable_0v9: 941 if (!IS_ERR(rockchip->vpcie0v9)) 942 regulator_disable(rockchip->vpcie0v9); 943 return err; 944 } 945 946 static int rockchip_pcie_probe(struct platform_device *pdev) 947 { 948 struct rockchip_pcie *rockchip; 949 struct device *dev = &pdev->dev; 950 struct pci_bus *bus, *child; 951 struct pci_host_bridge *bridge; 952 struct resource_entry *win; 953 resource_size_t io_base; 954 struct resource *mem; 955 struct resource *io; 956 int err; 957 958 LIST_HEAD(res); 959 960 if (!dev->of_node) 961 return -ENODEV; 962 963 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip)); 964 if (!bridge) 965 return -ENOMEM; 966 967 rockchip = pci_host_bridge_priv(bridge); 968 969 platform_set_drvdata(pdev, rockchip); 970 rockchip->dev = dev; 971 rockchip->is_rc = true; 972 973 err = rockchip_pcie_parse_host_dt(rockchip); 974 if (err) 975 return err; 976 977 err = rockchip_pcie_enable_clocks(rockchip); 978 if (err) 979 return err; 980 981 err = rockchip_pcie_set_vpcie(rockchip); 982 if (err) { 983 dev_err(dev, "failed to set vpcie regulator\n"); 984 goto err_set_vpcie; 985 } 986 987 err = rockchip_pcie_host_init_port(rockchip); 988 if (err) 989 goto err_vpcie; 990 991 rockchip_pcie_enable_interrupts(rockchip); 992 993 err = rockchip_pcie_init_irq_domain(rockchip); 994 if (err < 0) 995 goto err_deinit_port; 996 997 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 998 &res, &io_base); 999 if (err) 1000 goto err_remove_irq_domain; 1001 1002 err = devm_request_pci_bus_resources(dev, &res); 1003 if (err) 1004 goto err_free_res; 1005 1006 /* Get the I/O and memory ranges from DT */ 1007 resource_list_for_each_entry(win, &res) { 1008 switch (resource_type(win->res)) { 1009 case IORESOURCE_IO: 1010 io = win->res; 1011 io->name = "I/O"; 1012 rockchip->io_size = resource_size(io); 1013 rockchip->io_bus_addr = io->start - win->offset; 1014 err = pci_remap_iospace(io, io_base); 1015 if (err) { 1016 dev_warn(dev, "error %d: failed to map resource %pR\n", 1017 err, io); 1018 continue; 1019 } 1020 rockchip->io = io; 1021 break; 1022 case IORESOURCE_MEM: 1023 mem = win->res; 1024 mem->name = "MEM"; 1025 rockchip->mem_size = resource_size(mem); 1026 rockchip->mem_bus_addr = mem->start - win->offset; 1027 break; 1028 case IORESOURCE_BUS: 1029 rockchip->root_bus_nr = win->res->start; 1030 break; 1031 default: 1032 continue; 1033 } 1034 } 1035 1036 err = rockchip_pcie_cfg_atu(rockchip); 1037 if (err) 1038 goto err_unmap_iospace; 1039 1040 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M); 1041 if (!rockchip->msg_region) { 1042 err = -ENOMEM; 1043 goto err_unmap_iospace; 1044 } 1045 1046 list_splice_init(&res, &bridge->windows); 1047 bridge->dev.parent = dev; 1048 bridge->sysdata = rockchip; 1049 bridge->busnr = 0; 1050 bridge->ops = &rockchip_pcie_ops; 1051 bridge->map_irq = of_irq_parse_and_map_pci; 1052 bridge->swizzle_irq = pci_common_swizzle; 1053 1054 err = pci_scan_root_bus_bridge(bridge); 1055 if (err < 0) 1056 goto err_unmap_iospace; 1057 1058 bus = bridge->bus; 1059 1060 rockchip->root_bus = bus; 1061 1062 pci_bus_size_bridges(bus); 1063 pci_bus_assign_resources(bus); 1064 list_for_each_entry(child, &bus->children, node) 1065 pcie_bus_configure_settings(child); 1066 1067 pci_bus_add_devices(bus); 1068 return 0; 1069 1070 err_unmap_iospace: 1071 pci_unmap_iospace(rockchip->io); 1072 err_free_res: 1073 pci_free_resource_list(&res); 1074 err_remove_irq_domain: 1075 irq_domain_remove(rockchip->irq_domain); 1076 err_deinit_port: 1077 rockchip_pcie_deinit_phys(rockchip); 1078 err_vpcie: 1079 if (!IS_ERR(rockchip->vpcie12v)) 1080 regulator_disable(rockchip->vpcie12v); 1081 if (!IS_ERR(rockchip->vpcie3v3)) 1082 regulator_disable(rockchip->vpcie3v3); 1083 if (!IS_ERR(rockchip->vpcie1v8)) 1084 regulator_disable(rockchip->vpcie1v8); 1085 if (!IS_ERR(rockchip->vpcie0v9)) 1086 regulator_disable(rockchip->vpcie0v9); 1087 err_set_vpcie: 1088 rockchip_pcie_disable_clocks(rockchip); 1089 return err; 1090 } 1091 1092 static int rockchip_pcie_remove(struct platform_device *pdev) 1093 { 1094 struct device *dev = &pdev->dev; 1095 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 1096 1097 pci_stop_root_bus(rockchip->root_bus); 1098 pci_remove_root_bus(rockchip->root_bus); 1099 pci_unmap_iospace(rockchip->io); 1100 irq_domain_remove(rockchip->irq_domain); 1101 1102 rockchip_pcie_deinit_phys(rockchip); 1103 1104 rockchip_pcie_disable_clocks(rockchip); 1105 1106 if (!IS_ERR(rockchip->vpcie12v)) 1107 regulator_disable(rockchip->vpcie12v); 1108 if (!IS_ERR(rockchip->vpcie3v3)) 1109 regulator_disable(rockchip->vpcie3v3); 1110 if (!IS_ERR(rockchip->vpcie1v8)) 1111 regulator_disable(rockchip->vpcie1v8); 1112 if (!IS_ERR(rockchip->vpcie0v9)) 1113 regulator_disable(rockchip->vpcie0v9); 1114 1115 return 0; 1116 } 1117 1118 static const struct dev_pm_ops rockchip_pcie_pm_ops = { 1119 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq, 1120 rockchip_pcie_resume_noirq) 1121 }; 1122 1123 static const struct of_device_id rockchip_pcie_of_match[] = { 1124 { .compatible = "rockchip,rk3399-pcie", }, 1125 {} 1126 }; 1127 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match); 1128 1129 static struct platform_driver rockchip_pcie_driver = { 1130 .driver = { 1131 .name = "rockchip-pcie", 1132 .of_match_table = rockchip_pcie_of_match, 1133 .pm = &rockchip_pcie_pm_ops, 1134 }, 1135 .probe = rockchip_pcie_probe, 1136 .remove = rockchip_pcie_remove, 1137 }; 1138 module_platform_driver(rockchip_pcie_driver); 1139 1140 MODULE_AUTHOR("Rockchip Inc"); 1141 MODULE_DESCRIPTION("Rockchip AXI PCIe driver"); 1142 MODULE_LICENSE("GPL v2"); 1143