1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14 #include <linux/bitrev.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/of_pci.h> 30 #include <linux/of_platform.h> 31 #include <linux/of_irq.h> 32 #include <linux/pci.h> 33 #include <linux/pci_ids.h> 34 #include <linux/phy/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/reset.h> 37 #include <linux/regmap.h> 38 39 #include "../pci.h" 40 #include "pcie-rockchip.h" 41 42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) 43 { 44 u32 status; 45 46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 47 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); 48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 49 } 50 51 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) 52 { 53 u32 status; 54 55 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 56 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; 57 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 58 } 59 60 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) 61 { 62 u32 val; 63 64 /* Update Tx credit maximum update interval */ 65 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); 66 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; 67 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ 68 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); 69 } 70 71 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, 72 struct pci_bus *bus, int dev) 73 { 74 /* 75 * Access only one slot on each root port. 76 * Do not read more than one device on the bus directly attached 77 * to RC's downstream side. 78 */ 79 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) 80 return dev == 0; 81 82 return 1; 83 } 84 85 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip) 86 { 87 u32 val; 88 u8 map; 89 90 if (rockchip->legacy_phy) 91 return GENMASK(MAX_LANE_NUM - 1, 0); 92 93 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP); 94 map = val & PCIE_CORE_LANE_MAP_MASK; 95 96 /* The link may be using a reverse-indexed mapping. */ 97 if (val & PCIE_CORE_LANE_MAP_REVERSE) 98 map = bitrev8(map) >> 4; 99 100 return map; 101 } 102 103 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip, 104 int where, int size, u32 *val) 105 { 106 void __iomem *addr; 107 108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; 109 110 if (!IS_ALIGNED((uintptr_t)addr, size)) { 111 *val = 0; 112 return PCIBIOS_BAD_REGISTER_NUMBER; 113 } 114 115 if (size == 4) { 116 *val = readl(addr); 117 } else if (size == 2) { 118 *val = readw(addr); 119 } else if (size == 1) { 120 *val = readb(addr); 121 } else { 122 *val = 0; 123 return PCIBIOS_BAD_REGISTER_NUMBER; 124 } 125 return PCIBIOS_SUCCESSFUL; 126 } 127 128 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, 129 int where, int size, u32 val) 130 { 131 u32 mask, tmp, offset; 132 void __iomem *addr; 133 134 offset = where & ~0x3; 135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; 136 137 if (size == 4) { 138 writel(val, addr); 139 return PCIBIOS_SUCCESSFUL; 140 } 141 142 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); 143 144 /* 145 * N.B. This read/modify/write isn't safe in general because it can 146 * corrupt RW1C bits in adjacent registers. But the hardware 147 * doesn't support smaller writes. 148 */ 149 tmp = readl(addr) & mask; 150 tmp |= val << ((where & 0x3) * 8); 151 writel(tmp, addr); 152 153 return PCIBIOS_SUCCESSFUL; 154 } 155 156 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, 157 struct pci_bus *bus, u32 devfn, 158 int where, int size, u32 *val) 159 { 160 void __iomem *addr; 161 162 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 163 164 if (!IS_ALIGNED((uintptr_t)addr, size)) { 165 *val = 0; 166 return PCIBIOS_BAD_REGISTER_NUMBER; 167 } 168 169 if (pci_is_root_bus(bus->parent)) 170 rockchip_pcie_cfg_configuration_accesses(rockchip, 171 AXI_WRAPPER_TYPE0_CFG); 172 else 173 rockchip_pcie_cfg_configuration_accesses(rockchip, 174 AXI_WRAPPER_TYPE1_CFG); 175 176 if (size == 4) { 177 *val = readl(addr); 178 } else if (size == 2) { 179 *val = readw(addr); 180 } else if (size == 1) { 181 *val = readb(addr); 182 } else { 183 *val = 0; 184 return PCIBIOS_BAD_REGISTER_NUMBER; 185 } 186 return PCIBIOS_SUCCESSFUL; 187 } 188 189 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, 190 struct pci_bus *bus, u32 devfn, 191 int where, int size, u32 val) 192 { 193 void __iomem *addr; 194 195 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 196 197 if (!IS_ALIGNED((uintptr_t)addr, size)) 198 return PCIBIOS_BAD_REGISTER_NUMBER; 199 200 if (pci_is_root_bus(bus->parent)) 201 rockchip_pcie_cfg_configuration_accesses(rockchip, 202 AXI_WRAPPER_TYPE0_CFG); 203 else 204 rockchip_pcie_cfg_configuration_accesses(rockchip, 205 AXI_WRAPPER_TYPE1_CFG); 206 207 if (size == 4) 208 writel(val, addr); 209 else if (size == 2) 210 writew(val, addr); 211 else if (size == 1) 212 writeb(val, addr); 213 else 214 return PCIBIOS_BAD_REGISTER_NUMBER; 215 216 return PCIBIOS_SUCCESSFUL; 217 } 218 219 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 220 int size, u32 *val) 221 { 222 struct rockchip_pcie *rockchip = bus->sysdata; 223 224 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) { 225 *val = 0xffffffff; 226 return PCIBIOS_DEVICE_NOT_FOUND; 227 } 228 229 if (pci_is_root_bus(bus)) 230 return rockchip_pcie_rd_own_conf(rockchip, where, size, val); 231 232 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, 233 val); 234 } 235 236 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 237 int where, int size, u32 val) 238 { 239 struct rockchip_pcie *rockchip = bus->sysdata; 240 241 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) 242 return PCIBIOS_DEVICE_NOT_FOUND; 243 244 if (pci_is_root_bus(bus)) 245 return rockchip_pcie_wr_own_conf(rockchip, where, size, val); 246 247 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, 248 val); 249 } 250 251 static struct pci_ops rockchip_pcie_ops = { 252 .read = rockchip_pcie_rd_conf, 253 .write = rockchip_pcie_wr_conf, 254 }; 255 256 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) 257 { 258 int curr; 259 u32 status, scale, power; 260 261 if (IS_ERR(rockchip->vpcie3v3)) 262 return; 263 264 /* 265 * Set RC's captured slot power limit and scale if 266 * vpcie3v3 available. The default values are both zero 267 * which means the software should set these two according 268 * to the actual power supply. 269 */ 270 curr = regulator_get_current_limit(rockchip->vpcie3v3); 271 if (curr <= 0) 272 return; 273 274 scale = 3; /* 0.001x */ 275 curr = curr / 1000; /* convert to mA */ 276 power = (curr * 3300) / 1000; /* milliwatt */ 277 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { 278 if (!scale) { 279 dev_warn(rockchip->dev, "invalid power supply\n"); 280 return; 281 } 282 scale--; 283 power = power / 10; 284 } 285 286 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); 287 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | 288 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); 289 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); 290 } 291 292 /** 293 * rockchip_pcie_host_init_port - Initialize hardware 294 * @rockchip: PCIe port information 295 */ 296 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 297 { 298 struct device *dev = rockchip->dev; 299 int err, i = MAX_LANE_NUM; 300 u32 status; 301 302 gpiod_set_value_cansleep(rockchip->ep_gpio, 0); 303 304 err = rockchip_pcie_init_port(rockchip); 305 if (err) 306 return err; 307 308 /* Fix the transmitted FTS count desired to exit from L0s. */ 309 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); 310 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) | 311 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT); 312 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1); 313 314 rockchip_pcie_set_power_limit(rockchip); 315 316 /* Set RC's clock architecture as common clock */ 317 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 318 status |= PCI_EXP_LNKSTA_SLC << 16; 319 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 320 321 /* Set RC's RCB to 128 */ 322 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 323 status |= PCI_EXP_LNKCTL_RCB; 324 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 325 326 /* Enable Gen1 training */ 327 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, 328 PCIE_CLIENT_CONFIG); 329 330 gpiod_set_value_cansleep(rockchip->ep_gpio, 1); 331 332 /* 500ms timeout value should be enough for Gen1/2 training */ 333 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, 334 status, PCIE_LINK_UP(status), 20, 335 500 * USEC_PER_MSEC); 336 if (err) { 337 dev_err(dev, "PCIe link training gen1 timeout!\n"); 338 goto err_power_off_phy; 339 } 340 341 if (rockchip->link_gen == 2) { 342 /* 343 * Enable retrain for gen2. This should be configured only after 344 * gen1 finished. 345 */ 346 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 347 status |= PCI_EXP_LNKCTL_RL; 348 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 349 350 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, 351 status, PCIE_LINK_IS_GEN2(status), 20, 352 500 * USEC_PER_MSEC); 353 if (err) 354 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n"); 355 } 356 357 /* Check the final link width from negotiated lane counter from MGMT */ 358 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); 359 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >> 360 PCIE_CORE_PL_CONF_LANE_SHIFT); 361 dev_dbg(dev, "current link width is x%d\n", status); 362 363 /* Power off unused lane(s) */ 364 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip); 365 for (i = 0; i < MAX_LANE_NUM; i++) { 366 if (!(rockchip->lanes_map & BIT(i))) { 367 dev_dbg(dev, "idling lane %d\n", i); 368 phy_power_off(rockchip->phys[i]); 369 } 370 } 371 372 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, 373 PCIE_CORE_CONFIG_VENDOR); 374 rockchip_pcie_write(rockchip, 375 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT, 376 PCIE_RC_CONFIG_RID_CCR); 377 378 /* Clear THP cap's next cap pointer to remove L1 substate cap */ 379 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP); 380 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 381 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP); 382 383 /* Clear L0s from RC's link cap */ 384 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { 385 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); 386 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; 387 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); 388 } 389 390 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); 391 status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; 392 status |= PCIE_RC_CONFIG_DCSR_MPS_256; 393 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); 394 395 return 0; 396 err_power_off_phy: 397 while (i--) 398 phy_power_off(rockchip->phys[i]); 399 i = MAX_LANE_NUM; 400 while (i--) 401 phy_exit(rockchip->phys[i]); 402 return err; 403 } 404 405 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) 406 { 407 struct rockchip_pcie *rockchip = arg; 408 struct device *dev = rockchip->dev; 409 u32 reg; 410 u32 sub_reg; 411 412 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 413 if (reg & PCIE_CLIENT_INT_LOCAL) { 414 dev_dbg(dev, "local interrupt received\n"); 415 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS); 416 if (sub_reg & PCIE_CORE_INT_PRFPE) 417 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n"); 418 419 if (sub_reg & PCIE_CORE_INT_CRFPE) 420 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n"); 421 422 if (sub_reg & PCIE_CORE_INT_RRPE) 423 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n"); 424 425 if (sub_reg & PCIE_CORE_INT_PRFO) 426 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n"); 427 428 if (sub_reg & PCIE_CORE_INT_CRFO) 429 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n"); 430 431 if (sub_reg & PCIE_CORE_INT_RT) 432 dev_dbg(dev, "replay timer timed out\n"); 433 434 if (sub_reg & PCIE_CORE_INT_RTR) 435 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n"); 436 437 if (sub_reg & PCIE_CORE_INT_PE) 438 dev_dbg(dev, "phy error detected on receive side\n"); 439 440 if (sub_reg & PCIE_CORE_INT_MTR) 441 dev_dbg(dev, "malformed TLP received from the link\n"); 442 443 if (sub_reg & PCIE_CORE_INT_UCR) 444 dev_dbg(dev, "malformed TLP received from the link\n"); 445 446 if (sub_reg & PCIE_CORE_INT_FCE) 447 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n"); 448 449 if (sub_reg & PCIE_CORE_INT_CT) 450 dev_dbg(dev, "a request timed out waiting for completion\n"); 451 452 if (sub_reg & PCIE_CORE_INT_UTC) 453 dev_dbg(dev, "unmapped TC error\n"); 454 455 if (sub_reg & PCIE_CORE_INT_MMVC) 456 dev_dbg(dev, "MSI mask register changes\n"); 457 458 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS); 459 } else if (reg & PCIE_CLIENT_INT_PHY) { 460 dev_dbg(dev, "phy link changes\n"); 461 rockchip_pcie_update_txcredit_mui(rockchip); 462 rockchip_pcie_clr_bw_int(rockchip); 463 } 464 465 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL, 466 PCIE_CLIENT_INT_STATUS); 467 468 return IRQ_HANDLED; 469 } 470 471 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg) 472 { 473 struct rockchip_pcie *rockchip = arg; 474 struct device *dev = rockchip->dev; 475 u32 reg; 476 477 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 478 if (reg & PCIE_CLIENT_INT_LEGACY_DONE) 479 dev_dbg(dev, "legacy done interrupt received\n"); 480 481 if (reg & PCIE_CLIENT_INT_MSG) 482 dev_dbg(dev, "message done interrupt received\n"); 483 484 if (reg & PCIE_CLIENT_INT_HOT_RST) 485 dev_dbg(dev, "hot reset interrupt received\n"); 486 487 if (reg & PCIE_CLIENT_INT_DPA) 488 dev_dbg(dev, "dpa interrupt received\n"); 489 490 if (reg & PCIE_CLIENT_INT_FATAL_ERR) 491 dev_dbg(dev, "fatal error interrupt received\n"); 492 493 if (reg & PCIE_CLIENT_INT_NFATAL_ERR) 494 dev_dbg(dev, "no fatal error interrupt received\n"); 495 496 if (reg & PCIE_CLIENT_INT_CORR_ERR) 497 dev_dbg(dev, "correctable error interrupt received\n"); 498 499 if (reg & PCIE_CLIENT_INT_PHY) 500 dev_dbg(dev, "phy interrupt received\n"); 501 502 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE | 503 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST | 504 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR | 505 PCIE_CLIENT_INT_NFATAL_ERR | 506 PCIE_CLIENT_INT_CORR_ERR | 507 PCIE_CLIENT_INT_PHY), 508 PCIE_CLIENT_INT_STATUS); 509 510 return IRQ_HANDLED; 511 } 512 513 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) 514 { 515 struct irq_chip *chip = irq_desc_get_chip(desc); 516 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); 517 struct device *dev = rockchip->dev; 518 u32 reg; 519 u32 hwirq; 520 int ret; 521 522 chained_irq_enter(chip, desc); 523 524 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 525 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT; 526 527 while (reg) { 528 hwirq = ffs(reg) - 1; 529 reg &= ~BIT(hwirq); 530 531 ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq); 532 if (ret) 533 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); 534 } 535 536 chained_irq_exit(chip, desc); 537 } 538 539 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip) 540 { 541 int irq, err; 542 struct device *dev = rockchip->dev; 543 struct platform_device *pdev = to_platform_device(dev); 544 545 irq = platform_get_irq_byname(pdev, "sys"); 546 if (irq < 0) 547 return irq; 548 549 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler, 550 IRQF_SHARED, "pcie-sys", rockchip); 551 if (err) { 552 dev_err(dev, "failed to request PCIe subsystem IRQ\n"); 553 return err; 554 } 555 556 irq = platform_get_irq_byname(pdev, "legacy"); 557 if (irq < 0) 558 return irq; 559 560 irq_set_chained_handler_and_data(irq, 561 rockchip_pcie_legacy_int_handler, 562 rockchip); 563 564 irq = platform_get_irq_byname(pdev, "client"); 565 if (irq < 0) 566 return irq; 567 568 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler, 569 IRQF_SHARED, "pcie-client", rockchip); 570 if (err) { 571 dev_err(dev, "failed to request PCIe client IRQ\n"); 572 return err; 573 } 574 575 return 0; 576 } 577 578 /** 579 * rockchip_pcie_parse_host_dt - Parse Device Tree 580 * @rockchip: PCIe port information 581 * 582 * Return: '0' on success and error value on failure 583 */ 584 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip) 585 { 586 struct device *dev = rockchip->dev; 587 int err; 588 589 err = rockchip_pcie_parse_dt(rockchip); 590 if (err) 591 return err; 592 593 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v"); 594 if (IS_ERR(rockchip->vpcie12v)) { 595 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV) 596 return PTR_ERR(rockchip->vpcie12v); 597 dev_info(dev, "no vpcie12v regulator found\n"); 598 } 599 600 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); 601 if (IS_ERR(rockchip->vpcie3v3)) { 602 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV) 603 return PTR_ERR(rockchip->vpcie3v3); 604 dev_info(dev, "no vpcie3v3 regulator found\n"); 605 } 606 607 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8"); 608 if (IS_ERR(rockchip->vpcie1v8)) 609 return PTR_ERR(rockchip->vpcie1v8); 610 611 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9"); 612 if (IS_ERR(rockchip->vpcie0v9)) 613 return PTR_ERR(rockchip->vpcie0v9); 614 615 return 0; 616 } 617 618 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) 619 { 620 struct device *dev = rockchip->dev; 621 int err; 622 623 if (!IS_ERR(rockchip->vpcie12v)) { 624 err = regulator_enable(rockchip->vpcie12v); 625 if (err) { 626 dev_err(dev, "fail to enable vpcie12v regulator\n"); 627 goto err_out; 628 } 629 } 630 631 if (!IS_ERR(rockchip->vpcie3v3)) { 632 err = regulator_enable(rockchip->vpcie3v3); 633 if (err) { 634 dev_err(dev, "fail to enable vpcie3v3 regulator\n"); 635 goto err_disable_12v; 636 } 637 } 638 639 err = regulator_enable(rockchip->vpcie1v8); 640 if (err) { 641 dev_err(dev, "fail to enable vpcie1v8 regulator\n"); 642 goto err_disable_3v3; 643 } 644 645 err = regulator_enable(rockchip->vpcie0v9); 646 if (err) { 647 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 648 goto err_disable_1v8; 649 } 650 651 return 0; 652 653 err_disable_1v8: 654 regulator_disable(rockchip->vpcie1v8); 655 err_disable_3v3: 656 if (!IS_ERR(rockchip->vpcie3v3)) 657 regulator_disable(rockchip->vpcie3v3); 658 err_disable_12v: 659 if (!IS_ERR(rockchip->vpcie12v)) 660 regulator_disable(rockchip->vpcie12v); 661 err_out: 662 return err; 663 } 664 665 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip) 666 { 667 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) & 668 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK); 669 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT), 670 PCIE_CORE_INT_MASK); 671 672 rockchip_pcie_enable_bw_int(rockchip); 673 } 674 675 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 676 irq_hw_number_t hwirq) 677 { 678 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 679 irq_set_chip_data(irq, domain->host_data); 680 681 return 0; 682 } 683 684 static const struct irq_domain_ops intx_domain_ops = { 685 .map = rockchip_pcie_intx_map, 686 }; 687 688 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) 689 { 690 struct device *dev = rockchip->dev; 691 struct device_node *intc = of_get_next_child(dev->of_node, NULL); 692 693 if (!intc) { 694 dev_err(dev, "missing child interrupt-controller node\n"); 695 return -EINVAL; 696 } 697 698 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, 699 &intx_domain_ops, rockchip); 700 of_node_put(intc); 701 if (!rockchip->irq_domain) { 702 dev_err(dev, "failed to get a INTx IRQ domain\n"); 703 return -EINVAL; 704 } 705 706 return 0; 707 } 708 709 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, 710 int region_no, int type, u8 num_pass_bits, 711 u32 lower_addr, u32 upper_addr) 712 { 713 u32 ob_addr_0; 714 u32 ob_addr_1; 715 u32 ob_desc_0; 716 u32 aw_offset; 717 718 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM) 719 return -EINVAL; 720 if (num_pass_bits + 1 < 8) 721 return -EINVAL; 722 if (num_pass_bits > 63) 723 return -EINVAL; 724 if (region_no == 0) { 725 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits)) 726 return -EINVAL; 727 } 728 if (region_no != 0) { 729 if (AXI_REGION_SIZE < (2ULL << num_pass_bits)) 730 return -EINVAL; 731 } 732 733 aw_offset = (region_no << OB_REG_SIZE_SHIFT); 734 735 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS; 736 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR; 737 ob_addr_1 = upper_addr; 738 ob_desc_0 = (1 << 23 | type); 739 740 rockchip_pcie_write(rockchip, ob_addr_0, 741 PCIE_CORE_OB_REGION_ADDR0 + aw_offset); 742 rockchip_pcie_write(rockchip, ob_addr_1, 743 PCIE_CORE_OB_REGION_ADDR1 + aw_offset); 744 rockchip_pcie_write(rockchip, ob_desc_0, 745 PCIE_CORE_OB_REGION_DESC0 + aw_offset); 746 rockchip_pcie_write(rockchip, 0, 747 PCIE_CORE_OB_REGION_DESC1 + aw_offset); 748 749 return 0; 750 } 751 752 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, 753 int region_no, u8 num_pass_bits, 754 u32 lower_addr, u32 upper_addr) 755 { 756 u32 ib_addr_0; 757 u32 ib_addr_1; 758 u32 aw_offset; 759 760 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM) 761 return -EINVAL; 762 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED) 763 return -EINVAL; 764 if (num_pass_bits > 63) 765 return -EINVAL; 766 767 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT); 768 769 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS; 770 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR; 771 ib_addr_1 = upper_addr; 772 773 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset); 774 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset); 775 776 return 0; 777 } 778 779 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip) 780 { 781 struct device *dev = rockchip->dev; 782 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip); 783 struct resource_entry *entry; 784 u64 pci_addr, size; 785 int offset; 786 int err; 787 int reg_no; 788 789 rockchip_pcie_cfg_configuration_accesses(rockchip, 790 AXI_WRAPPER_TYPE0_CFG); 791 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 792 if (!entry) 793 return -ENODEV; 794 795 size = resource_size(entry->res); 796 pci_addr = entry->res->start - entry->offset; 797 rockchip->msg_bus_addr = pci_addr; 798 799 for (reg_no = 0; reg_no < (size >> 20); reg_no++) { 800 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1, 801 AXI_WRAPPER_MEM_WRITE, 802 20 - 1, 803 pci_addr + (reg_no << 20), 804 0); 805 if (err) { 806 dev_err(dev, "program RC mem outbound ATU failed\n"); 807 return err; 808 } 809 } 810 811 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0); 812 if (err) { 813 dev_err(dev, "program RC mem inbound ATU failed\n"); 814 return err; 815 } 816 817 entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 818 if (!entry) 819 return -ENODEV; 820 821 /* store the register number offset to program RC io outbound ATU */ 822 offset = size >> 20; 823 824 size = resource_size(entry->res); 825 pci_addr = entry->res->start - entry->offset; 826 827 for (reg_no = 0; reg_no < (size >> 20); reg_no++) { 828 err = rockchip_pcie_prog_ob_atu(rockchip, 829 reg_no + 1 + offset, 830 AXI_WRAPPER_IO_WRITE, 831 20 - 1, 832 pci_addr + (reg_no << 20), 833 0); 834 if (err) { 835 dev_err(dev, "program RC io outbound ATU failed\n"); 836 return err; 837 } 838 } 839 840 /* assign message regions */ 841 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset, 842 AXI_WRAPPER_NOR_MSG, 843 20 - 1, 0, 0); 844 845 rockchip->msg_bus_addr += ((reg_no + offset) << 20); 846 return err; 847 } 848 849 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip) 850 { 851 u32 value; 852 int err; 853 854 /* send PME_TURN_OFF message */ 855 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF); 856 857 /* read LTSSM and wait for falling into L2 link state */ 858 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0, 859 value, PCIE_LINK_IS_L2(value), 20, 860 jiffies_to_usecs(5 * HZ)); 861 if (err) { 862 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n"); 863 return err; 864 } 865 866 return 0; 867 } 868 869 static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) 870 { 871 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 872 int ret; 873 874 /* disable core and cli int since we don't need to ack PME_ACK */ 875 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) | 876 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK); 877 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK); 878 879 ret = rockchip_pcie_wait_l2(rockchip); 880 if (ret) { 881 rockchip_pcie_enable_interrupts(rockchip); 882 return ret; 883 } 884 885 rockchip_pcie_deinit_phys(rockchip); 886 887 rockchip_pcie_disable_clocks(rockchip); 888 889 regulator_disable(rockchip->vpcie0v9); 890 891 return ret; 892 } 893 894 static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) 895 { 896 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 897 int err; 898 899 err = regulator_enable(rockchip->vpcie0v9); 900 if (err) { 901 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 902 return err; 903 } 904 905 err = rockchip_pcie_enable_clocks(rockchip); 906 if (err) 907 goto err_disable_0v9; 908 909 err = rockchip_pcie_host_init_port(rockchip); 910 if (err) 911 goto err_pcie_resume; 912 913 err = rockchip_pcie_cfg_atu(rockchip); 914 if (err) 915 goto err_err_deinit_port; 916 917 /* Need this to enter L1 again */ 918 rockchip_pcie_update_txcredit_mui(rockchip); 919 rockchip_pcie_enable_interrupts(rockchip); 920 921 return 0; 922 923 err_err_deinit_port: 924 rockchip_pcie_deinit_phys(rockchip); 925 err_pcie_resume: 926 rockchip_pcie_disable_clocks(rockchip); 927 err_disable_0v9: 928 regulator_disable(rockchip->vpcie0v9); 929 return err; 930 } 931 932 static int rockchip_pcie_probe(struct platform_device *pdev) 933 { 934 struct rockchip_pcie *rockchip; 935 struct device *dev = &pdev->dev; 936 struct pci_host_bridge *bridge; 937 int err; 938 939 if (!dev->of_node) 940 return -ENODEV; 941 942 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip)); 943 if (!bridge) 944 return -ENOMEM; 945 946 rockchip = pci_host_bridge_priv(bridge); 947 948 platform_set_drvdata(pdev, rockchip); 949 rockchip->dev = dev; 950 rockchip->is_rc = true; 951 952 err = rockchip_pcie_parse_host_dt(rockchip); 953 if (err) 954 return err; 955 956 err = rockchip_pcie_enable_clocks(rockchip); 957 if (err) 958 return err; 959 960 err = rockchip_pcie_set_vpcie(rockchip); 961 if (err) { 962 dev_err(dev, "failed to set vpcie regulator\n"); 963 goto err_set_vpcie; 964 } 965 966 err = rockchip_pcie_host_init_port(rockchip); 967 if (err) 968 goto err_vpcie; 969 970 err = rockchip_pcie_init_irq_domain(rockchip); 971 if (err < 0) 972 goto err_deinit_port; 973 974 err = rockchip_pcie_cfg_atu(rockchip); 975 if (err) 976 goto err_remove_irq_domain; 977 978 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M); 979 if (!rockchip->msg_region) { 980 err = -ENOMEM; 981 goto err_remove_irq_domain; 982 } 983 984 bridge->sysdata = rockchip; 985 bridge->ops = &rockchip_pcie_ops; 986 987 err = rockchip_pcie_setup_irq(rockchip); 988 if (err) 989 goto err_remove_irq_domain; 990 991 rockchip_pcie_enable_interrupts(rockchip); 992 993 err = pci_host_probe(bridge); 994 if (err < 0) 995 goto err_remove_irq_domain; 996 997 return 0; 998 999 err_remove_irq_domain: 1000 irq_domain_remove(rockchip->irq_domain); 1001 err_deinit_port: 1002 rockchip_pcie_deinit_phys(rockchip); 1003 err_vpcie: 1004 if (!IS_ERR(rockchip->vpcie12v)) 1005 regulator_disable(rockchip->vpcie12v); 1006 if (!IS_ERR(rockchip->vpcie3v3)) 1007 regulator_disable(rockchip->vpcie3v3); 1008 regulator_disable(rockchip->vpcie1v8); 1009 regulator_disable(rockchip->vpcie0v9); 1010 err_set_vpcie: 1011 rockchip_pcie_disable_clocks(rockchip); 1012 return err; 1013 } 1014 1015 static int rockchip_pcie_remove(struct platform_device *pdev) 1016 { 1017 struct device *dev = &pdev->dev; 1018 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 1019 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip); 1020 1021 pci_stop_root_bus(bridge->bus); 1022 pci_remove_root_bus(bridge->bus); 1023 irq_domain_remove(rockchip->irq_domain); 1024 1025 rockchip_pcie_deinit_phys(rockchip); 1026 1027 rockchip_pcie_disable_clocks(rockchip); 1028 1029 if (!IS_ERR(rockchip->vpcie12v)) 1030 regulator_disable(rockchip->vpcie12v); 1031 if (!IS_ERR(rockchip->vpcie3v3)) 1032 regulator_disable(rockchip->vpcie3v3); 1033 regulator_disable(rockchip->vpcie1v8); 1034 regulator_disable(rockchip->vpcie0v9); 1035 1036 return 0; 1037 } 1038 1039 static const struct dev_pm_ops rockchip_pcie_pm_ops = { 1040 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq, 1041 rockchip_pcie_resume_noirq) 1042 }; 1043 1044 static const struct of_device_id rockchip_pcie_of_match[] = { 1045 { .compatible = "rockchip,rk3399-pcie", }, 1046 {} 1047 }; 1048 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match); 1049 1050 static struct platform_driver rockchip_pcie_driver = { 1051 .driver = { 1052 .name = "rockchip-pcie", 1053 .of_match_table = rockchip_pcie_of_match, 1054 .pm = &rockchip_pcie_pm_ops, 1055 }, 1056 .probe = rockchip_pcie_probe, 1057 .remove = rockchip_pcie_remove, 1058 }; 1059 module_platform_driver(rockchip_pcie_driver); 1060 1061 MODULE_AUTHOR("Rockchip Inc"); 1062 MODULE_DESCRIPTION("Rockchip AXI PCIe driver"); 1063 MODULE_LICENSE("GPL v2"); 1064