1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/msi.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_pci.h> 26 #include <linux/of_platform.h> 27 #include <linux/pci.h> 28 #include <linux/phy/phy.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/slab.h> 32 33 #include "../pci.h" 34 35 #define PCIECAR 0x000010 36 #define PCIECCTLR 0x000018 37 #define CONFIG_SEND_ENABLE BIT(31) 38 #define TYPE0 (0 << 8) 39 #define TYPE1 BIT(8) 40 #define PCIECDR 0x000020 41 #define PCIEMSR 0x000028 42 #define PCIEINTXR 0x000400 43 #define PCIEPHYSR 0x0007f0 44 #define PHYRDY BIT(0) 45 #define PCIEMSITXR 0x000840 46 47 /* Transfer control */ 48 #define PCIETCTLR 0x02000 49 #define CFINIT 1 50 #define PCIETSTR 0x02004 51 #define DATA_LINK_ACTIVE 1 52 #define PCIEERRFR 0x02020 53 #define UNSUPPORTED_REQUEST BIT(4) 54 #define PCIEMSIFR 0x02044 55 #define PCIEMSIALR 0x02048 56 #define MSIFE 1 57 #define PCIEMSIAUR 0x0204c 58 #define PCIEMSIIER 0x02050 59 60 /* root port address */ 61 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) 62 63 /* local address reg & mask */ 64 #define PCIELAR(x) (0x02200 + ((x) * 0x20)) 65 #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) 66 #define LAM_PREFETCH BIT(3) 67 #define LAM_64BIT BIT(2) 68 #define LAR_ENABLE BIT(1) 69 70 /* PCIe address reg & mask */ 71 #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) 72 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) 73 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) 74 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) 75 #define PAR_ENABLE BIT(31) 76 #define IO_SPACE BIT(8) 77 78 /* Configuration */ 79 #define PCICONF(x) (0x010000 + ((x) * 0x4)) 80 #define PMCAP(x) (0x010040 + ((x) * 0x4)) 81 #define EXPCAP(x) (0x010070 + ((x) * 0x4)) 82 #define VCCAP(x) (0x010100 + ((x) * 0x4)) 83 84 /* link layer */ 85 #define IDSETR1 0x011004 86 #define TLCTLR 0x011048 87 #define MACSR 0x011054 88 #define SPCHGFIN BIT(4) 89 #define SPCHGFAIL BIT(6) 90 #define SPCHGSUC BIT(7) 91 #define LINK_SPEED (0xf << 16) 92 #define LINK_SPEED_2_5GTS (1 << 16) 93 #define LINK_SPEED_5_0GTS (2 << 16) 94 #define MACCTLR 0x011058 95 #define SPEED_CHANGE BIT(24) 96 #define SCRAMBLE_DISABLE BIT(27) 97 #define MACS2R 0x011078 98 #define MACCGSPSETR 0x011084 99 #define SPCNGRSN BIT(31) 100 101 /* R-Car H1 PHY */ 102 #define H1_PCIEPHYADRR 0x04000c 103 #define WRITE_CMD BIT(16) 104 #define PHY_ACK BIT(24) 105 #define RATE_POS 12 106 #define LANE_POS 8 107 #define ADR_POS 0 108 #define H1_PCIEPHYDOUTR 0x040014 109 110 /* R-Car Gen2 PHY */ 111 #define GEN2_PCIEPHYADDR 0x780 112 #define GEN2_PCIEPHYDATA 0x784 113 #define GEN2_PCIEPHYCTRL 0x78c 114 115 #define INT_PCI_MSI_NR 32 116 117 #define RCONF(x) (PCICONF(0) + (x)) 118 #define RPMCAP(x) (PMCAP(0) + (x)) 119 #define REXPCAP(x) (EXPCAP(0) + (x)) 120 #define RVCCAP(x) (VCCAP(0) + (x)) 121 122 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) 123 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) 124 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) 125 126 #define RCAR_PCI_MAX_RESOURCES 4 127 #define MAX_NR_INBOUND_MAPS 6 128 129 struct rcar_msi { 130 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 131 struct irq_domain *domain; 132 struct msi_controller chip; 133 unsigned long pages; 134 struct mutex lock; 135 int irq1; 136 int irq2; 137 }; 138 139 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) 140 { 141 return container_of(chip, struct rcar_msi, chip); 142 } 143 144 /* Structure representing the PCIe interface */ 145 struct rcar_pcie { 146 struct device *dev; 147 struct phy *phy; 148 void __iomem *base; 149 struct list_head resources; 150 int root_bus_nr; 151 struct clk *bus_clk; 152 struct rcar_msi msi; 153 }; 154 155 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val, 156 unsigned long reg) 157 { 158 writel(val, pcie->base + reg); 159 } 160 161 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie, 162 unsigned long reg) 163 { 164 return readl(pcie->base + reg); 165 } 166 167 enum { 168 RCAR_PCI_ACCESS_READ, 169 RCAR_PCI_ACCESS_WRITE, 170 }; 171 172 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) 173 { 174 int shift = 8 * (where & 3); 175 u32 val = rcar_pci_read_reg(pcie, where & ~3); 176 177 val &= ~(mask << shift); 178 val |= data << shift; 179 rcar_pci_write_reg(pcie, val, where & ~3); 180 } 181 182 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 183 { 184 int shift = 8 * (where & 3); 185 u32 val = rcar_pci_read_reg(pcie, where & ~3); 186 187 return val >> shift; 188 } 189 190 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 191 static int rcar_pcie_config_access(struct rcar_pcie *pcie, 192 unsigned char access_type, struct pci_bus *bus, 193 unsigned int devfn, int where, u32 *data) 194 { 195 int dev, func, reg, index; 196 197 dev = PCI_SLOT(devfn); 198 func = PCI_FUNC(devfn); 199 reg = where & ~3; 200 index = reg / 4; 201 202 /* 203 * While each channel has its own memory-mapped extended config 204 * space, it's generally only accessible when in endpoint mode. 205 * When in root complex mode, the controller is unable to target 206 * itself with either type 0 or type 1 accesses, and indeed, any 207 * controller initiated target transfer to its own config space 208 * result in a completer abort. 209 * 210 * Each channel effectively only supports a single device, but as 211 * the same channel <-> device access works for any PCI_SLOT() 212 * value, we cheat a bit here and bind the controller's config 213 * space to devfn 0 in order to enable self-enumeration. In this 214 * case the regular ECAR/ECDR path is sidelined and the mangled 215 * config access itself is initiated as an internal bus transaction. 216 */ 217 if (pci_is_root_bus(bus)) { 218 if (dev != 0) 219 return PCIBIOS_DEVICE_NOT_FOUND; 220 221 if (access_type == RCAR_PCI_ACCESS_READ) { 222 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 223 } else { 224 /* Keep an eye out for changes to the root bus number */ 225 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) 226 pcie->root_bus_nr = *data & 0xff; 227 228 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 229 } 230 231 return PCIBIOS_SUCCESSFUL; 232 } 233 234 if (pcie->root_bus_nr < 0) 235 return PCIBIOS_DEVICE_NOT_FOUND; 236 237 /* Clear errors */ 238 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 239 240 /* Set the PIO address */ 241 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 242 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 243 244 /* Enable the configuration access */ 245 if (bus->parent->number == pcie->root_bus_nr) 246 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); 247 else 248 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); 249 250 /* Check for errors */ 251 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 252 return PCIBIOS_DEVICE_NOT_FOUND; 253 254 /* Check for master and target aborts */ 255 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 256 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 257 return PCIBIOS_DEVICE_NOT_FOUND; 258 259 if (access_type == RCAR_PCI_ACCESS_READ) 260 *data = rcar_pci_read_reg(pcie, PCIECDR); 261 else 262 rcar_pci_write_reg(pcie, *data, PCIECDR); 263 264 /* Disable the configuration access */ 265 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 266 267 return PCIBIOS_SUCCESSFUL; 268 } 269 270 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 271 int where, int size, u32 *val) 272 { 273 struct rcar_pcie *pcie = bus->sysdata; 274 int ret; 275 276 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, 277 bus, devfn, where, val); 278 if (ret != PCIBIOS_SUCCESSFUL) { 279 *val = 0xffffffff; 280 return ret; 281 } 282 283 if (size == 1) 284 *val = (*val >> (8 * (where & 3))) & 0xff; 285 else if (size == 2) 286 *val = (*val >> (8 * (where & 2))) & 0xffff; 287 288 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", 289 bus->number, devfn, where, size, (unsigned long)*val); 290 291 return ret; 292 } 293 294 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 295 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 296 int where, int size, u32 val) 297 { 298 struct rcar_pcie *pcie = bus->sysdata; 299 int shift, ret; 300 u32 data; 301 302 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, 303 bus, devfn, where, &data); 304 if (ret != PCIBIOS_SUCCESSFUL) 305 return ret; 306 307 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", 308 bus->number, devfn, where, size, (unsigned long)val); 309 310 if (size == 1) { 311 shift = 8 * (where & 3); 312 data &= ~(0xff << shift); 313 data |= ((val & 0xff) << shift); 314 } else if (size == 2) { 315 shift = 8 * (where & 2); 316 data &= ~(0xffff << shift); 317 data |= ((val & 0xffff) << shift); 318 } else 319 data = val; 320 321 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, 322 bus, devfn, where, &data); 323 324 return ret; 325 } 326 327 static struct pci_ops rcar_pcie_ops = { 328 .read = rcar_pcie_read_conf, 329 .write = rcar_pcie_write_conf, 330 }; 331 332 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie, 333 struct resource *res) 334 { 335 /* Setup PCIe address space mappings for each resource */ 336 resource_size_t size; 337 resource_size_t res_start; 338 u32 mask; 339 340 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); 341 342 /* 343 * The PAMR mask is calculated in units of 128Bytes, which 344 * keeps things pretty simple. 345 */ 346 size = resource_size(res); 347 mask = (roundup_pow_of_two(size) / SZ_128) - 1; 348 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); 349 350 if (res->flags & IORESOURCE_IO) 351 res_start = pci_pio_to_address(res->start); 352 else 353 res_start = res->start; 354 355 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); 356 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, 357 PCIEPALR(win)); 358 359 /* First resource is for IO */ 360 mask = PAR_ENABLE; 361 if (res->flags & IORESOURCE_IO) 362 mask |= IO_SPACE; 363 364 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); 365 } 366 367 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci) 368 { 369 struct resource_entry *win; 370 int i = 0; 371 372 /* Setup PCI resources */ 373 resource_list_for_each_entry(win, &pci->resources) { 374 struct resource *res = win->res; 375 376 if (!res->flags) 377 continue; 378 379 switch (resource_type(res)) { 380 case IORESOURCE_IO: 381 case IORESOURCE_MEM: 382 rcar_pcie_setup_window(i, pci, res); 383 i++; 384 break; 385 case IORESOURCE_BUS: 386 pci->root_bus_nr = res->start; 387 break; 388 default: 389 continue; 390 } 391 392 pci_add_resource(resource, res); 393 } 394 395 return 1; 396 } 397 398 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 399 { 400 struct device *dev = pcie->dev; 401 unsigned int timeout = 1000; 402 u32 macsr; 403 404 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 405 return; 406 407 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 408 dev_err(dev, "Speed change already in progress\n"); 409 return; 410 } 411 412 macsr = rcar_pci_read_reg(pcie, MACSR); 413 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 414 goto done; 415 416 /* Set target link speed to 5.0 GT/s */ 417 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 418 PCI_EXP_LNKSTA_CLS_5_0GB); 419 420 /* Set speed change reason as intentional factor */ 421 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 422 423 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 424 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 425 rcar_pci_write_reg(pcie, macsr, MACSR); 426 427 /* Start link speed change */ 428 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 429 430 while (timeout--) { 431 macsr = rcar_pci_read_reg(pcie, MACSR); 432 if (macsr & SPCHGFIN) { 433 /* Clear the interrupt bits */ 434 rcar_pci_write_reg(pcie, macsr, MACSR); 435 436 if (macsr & SPCHGFAIL) 437 dev_err(dev, "Speed change failed\n"); 438 439 goto done; 440 } 441 442 msleep(1); 443 } 444 445 dev_err(dev, "Speed change timed out\n"); 446 447 done: 448 dev_info(dev, "Current link speed is %s GT/s\n", 449 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 450 } 451 452 static int rcar_pcie_enable(struct rcar_pcie *pcie) 453 { 454 struct device *dev = pcie->dev; 455 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 456 struct pci_bus *bus, *child; 457 int ret; 458 459 /* Try setting 5 GT/s link speed */ 460 rcar_pcie_force_speedup(pcie); 461 462 rcar_pcie_setup(&bridge->windows, pcie); 463 464 pci_add_flags(PCI_REASSIGN_ALL_BUS); 465 466 bridge->dev.parent = dev; 467 bridge->sysdata = pcie; 468 bridge->busnr = pcie->root_bus_nr; 469 bridge->ops = &rcar_pcie_ops; 470 bridge->map_irq = of_irq_parse_and_map_pci; 471 bridge->swizzle_irq = pci_common_swizzle; 472 if (IS_ENABLED(CONFIG_PCI_MSI)) 473 bridge->msi = &pcie->msi.chip; 474 475 ret = pci_scan_root_bus_bridge(bridge); 476 if (ret < 0) 477 return ret; 478 479 bus = bridge->bus; 480 481 pci_bus_size_bridges(bus); 482 pci_bus_assign_resources(bus); 483 484 list_for_each_entry(child, &bus->children, node) 485 pcie_bus_configure_settings(child); 486 487 pci_bus_add_devices(bus); 488 489 return 0; 490 } 491 492 static int phy_wait_for_ack(struct rcar_pcie *pcie) 493 { 494 struct device *dev = pcie->dev; 495 unsigned int timeout = 100; 496 497 while (timeout--) { 498 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 499 return 0; 500 501 udelay(100); 502 } 503 504 dev_err(dev, "Access to PCIe phy timed out\n"); 505 506 return -ETIMEDOUT; 507 } 508 509 static void phy_write_reg(struct rcar_pcie *pcie, 510 unsigned int rate, unsigned int addr, 511 unsigned int lane, unsigned int data) 512 { 513 unsigned long phyaddr; 514 515 phyaddr = WRITE_CMD | 516 ((rate & 1) << RATE_POS) | 517 ((lane & 0xf) << LANE_POS) | 518 ((addr & 0xff) << ADR_POS); 519 520 /* Set write data */ 521 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 522 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 523 524 /* Ignore errors as they will be dealt with if the data link is down */ 525 phy_wait_for_ack(pcie); 526 527 /* Clear command */ 528 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 529 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 530 531 /* Ignore errors as they will be dealt with if the data link is down */ 532 phy_wait_for_ack(pcie); 533 } 534 535 static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) 536 { 537 unsigned int timeout = 10; 538 539 while (timeout--) { 540 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY) 541 return 0; 542 543 msleep(5); 544 } 545 546 return -ETIMEDOUT; 547 } 548 549 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) 550 { 551 unsigned int timeout = 10000; 552 553 while (timeout--) { 554 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE)) 555 return 0; 556 557 udelay(5); 558 cpu_relax(); 559 } 560 561 return -ETIMEDOUT; 562 } 563 564 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 565 { 566 int err; 567 568 /* Begin initialization */ 569 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 570 571 /* Set mode */ 572 rcar_pci_write_reg(pcie, 1, PCIEMSR); 573 574 err = rcar_pcie_wait_for_phyrdy(pcie); 575 if (err) 576 return err; 577 578 /* 579 * Initial header for port config space is type 1, set the device 580 * class to match. Hardware takes care of propagating the IDSETR 581 * settings, so there is no need to bother with a quirk. 582 */ 583 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); 584 585 /* 586 * Setup Secondary Bus Number & Subordinate Bus Number, even though 587 * they aren't used, to avoid bridge being detected as broken. 588 */ 589 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 590 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 591 592 /* Initialize default capabilities. */ 593 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 594 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 595 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 596 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 597 PCI_HEADER_TYPE_BRIDGE); 598 599 /* Enable data link layer active state reporting */ 600 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 601 PCI_EXP_LNKCAP_DLLLARC); 602 603 /* Write out the physical slot number = 0 */ 604 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 605 606 /* Set the completion timer timeout to the maximum 50ms. */ 607 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 608 609 /* Terminate list of capabilities (Next Capability Offset=0) */ 610 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 611 612 /* Enable MSI */ 613 if (IS_ENABLED(CONFIG_PCI_MSI)) 614 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 615 616 /* Finish initialization - establish a PCI Express link */ 617 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 618 619 /* This will timeout if we don't have a link. */ 620 err = rcar_pcie_wait_for_dl(pcie); 621 if (err) 622 return err; 623 624 /* Enable INTx interrupts */ 625 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 626 627 wmb(); 628 629 return 0; 630 } 631 632 static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie) 633 { 634 /* Initialize the phy */ 635 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 636 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 637 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 638 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 639 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 640 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 641 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 642 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 643 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 644 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 645 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 646 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 647 648 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 649 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 650 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 651 652 return 0; 653 } 654 655 static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie) 656 { 657 /* 658 * These settings come from the R-Car Series, 2nd Generation User's 659 * Manual, section 50.3.1 (2) Initialization of the physical layer. 660 */ 661 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 662 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 663 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 664 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 665 666 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 667 /* The following value is for DC connection, no termination resistor */ 668 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 669 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 670 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 671 672 return 0; 673 } 674 675 static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie) 676 { 677 int err; 678 679 err = phy_init(pcie->phy); 680 if (err) 681 return err; 682 683 return phy_power_on(pcie->phy); 684 } 685 686 static int rcar_msi_alloc(struct rcar_msi *chip) 687 { 688 int msi; 689 690 mutex_lock(&chip->lock); 691 692 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); 693 if (msi < INT_PCI_MSI_NR) 694 set_bit(msi, chip->used); 695 else 696 msi = -ENOSPC; 697 698 mutex_unlock(&chip->lock); 699 700 return msi; 701 } 702 703 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) 704 { 705 int msi; 706 707 mutex_lock(&chip->lock); 708 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, 709 order_base_2(no_irqs)); 710 mutex_unlock(&chip->lock); 711 712 return msi; 713 } 714 715 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) 716 { 717 mutex_lock(&chip->lock); 718 clear_bit(irq, chip->used); 719 mutex_unlock(&chip->lock); 720 } 721 722 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 723 { 724 struct rcar_pcie *pcie = data; 725 struct rcar_msi *msi = &pcie->msi; 726 struct device *dev = pcie->dev; 727 unsigned long reg; 728 729 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 730 731 /* MSI & INTx share an interrupt - we only handle MSI here */ 732 if (!reg) 733 return IRQ_NONE; 734 735 while (reg) { 736 unsigned int index = find_first_bit(®, 32); 737 unsigned int irq; 738 739 /* clear the interrupt */ 740 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); 741 742 irq = irq_find_mapping(msi->domain, index); 743 if (irq) { 744 if (test_bit(index, msi->used)) 745 generic_handle_irq(irq); 746 else 747 dev_info(dev, "unhandled MSI\n"); 748 } else { 749 /* Unknown MSI, just clear it */ 750 dev_dbg(dev, "unexpected MSI\n"); 751 } 752 753 /* see if there's any more pending in this vector */ 754 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 755 } 756 757 return IRQ_HANDLED; 758 } 759 760 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, 761 struct msi_desc *desc) 762 { 763 struct rcar_msi *msi = to_rcar_msi(chip); 764 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); 765 struct msi_msg msg; 766 unsigned int irq; 767 int hwirq; 768 769 hwirq = rcar_msi_alloc(msi); 770 if (hwirq < 0) 771 return hwirq; 772 773 irq = irq_find_mapping(msi->domain, hwirq); 774 if (!irq) { 775 rcar_msi_free(msi, hwirq); 776 return -EINVAL; 777 } 778 779 irq_set_msi_desc(irq, desc); 780 781 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 782 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 783 msg.data = hwirq; 784 785 pci_write_msi_msg(irq, &msg); 786 787 return 0; 788 } 789 790 static int rcar_msi_setup_irqs(struct msi_controller *chip, 791 struct pci_dev *pdev, int nvec, int type) 792 { 793 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); 794 struct rcar_msi *msi = to_rcar_msi(chip); 795 struct msi_desc *desc; 796 struct msi_msg msg; 797 unsigned int irq; 798 int hwirq; 799 int i; 800 801 /* MSI-X interrupts are not supported */ 802 if (type == PCI_CAP_ID_MSIX) 803 return -EINVAL; 804 805 WARN_ON(!list_is_singular(&pdev->dev.msi_list)); 806 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); 807 808 hwirq = rcar_msi_alloc_region(msi, nvec); 809 if (hwirq < 0) 810 return -ENOSPC; 811 812 irq = irq_find_mapping(msi->domain, hwirq); 813 if (!irq) 814 return -ENOSPC; 815 816 for (i = 0; i < nvec; i++) { 817 /* 818 * irq_create_mapping() called from rcar_pcie_probe() pre- 819 * allocates descs, so there is no need to allocate descs here. 820 * We can therefore assume that if irq_find_mapping() above 821 * returns non-zero, then the descs are also successfully 822 * allocated. 823 */ 824 if (irq_set_msi_desc_off(irq, i, desc)) { 825 /* TODO: clear */ 826 return -EINVAL; 827 } 828 } 829 830 desc->nvec_used = nvec; 831 desc->msi_attrib.multiple = order_base_2(nvec); 832 833 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 834 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 835 msg.data = hwirq; 836 837 pci_write_msi_msg(irq, &msg); 838 839 return 0; 840 } 841 842 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) 843 { 844 struct rcar_msi *msi = to_rcar_msi(chip); 845 struct irq_data *d = irq_get_irq_data(irq); 846 847 rcar_msi_free(msi, d->hwirq); 848 } 849 850 static struct irq_chip rcar_msi_irq_chip = { 851 .name = "R-Car PCIe MSI", 852 .irq_enable = pci_msi_unmask_irq, 853 .irq_disable = pci_msi_mask_irq, 854 .irq_mask = pci_msi_mask_irq, 855 .irq_unmask = pci_msi_unmask_irq, 856 }; 857 858 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, 859 irq_hw_number_t hwirq) 860 { 861 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); 862 irq_set_chip_data(irq, domain->host_data); 863 864 return 0; 865 } 866 867 static const struct irq_domain_ops msi_domain_ops = { 868 .map = rcar_msi_map, 869 }; 870 871 static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie) 872 { 873 struct rcar_msi *msi = &pcie->msi; 874 int i, irq; 875 876 for (i = 0; i < INT_PCI_MSI_NR; i++) { 877 irq = irq_find_mapping(msi->domain, i); 878 if (irq > 0) 879 irq_dispose_mapping(irq); 880 } 881 882 irq_domain_remove(msi->domain); 883 } 884 885 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) 886 { 887 struct device *dev = pcie->dev; 888 struct rcar_msi *msi = &pcie->msi; 889 unsigned long base; 890 int err, i; 891 892 mutex_init(&msi->lock); 893 894 msi->chip.dev = dev; 895 msi->chip.setup_irq = rcar_msi_setup_irq; 896 msi->chip.setup_irqs = rcar_msi_setup_irqs; 897 msi->chip.teardown_irq = rcar_msi_teardown_irq; 898 899 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, 900 &msi_domain_ops, &msi->chip); 901 if (!msi->domain) { 902 dev_err(dev, "failed to create IRQ domain\n"); 903 return -ENOMEM; 904 } 905 906 for (i = 0; i < INT_PCI_MSI_NR; i++) 907 irq_create_mapping(msi->domain, i); 908 909 /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 910 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 911 IRQF_SHARED | IRQF_NO_THREAD, 912 rcar_msi_irq_chip.name, pcie); 913 if (err < 0) { 914 dev_err(dev, "failed to request IRQ: %d\n", err); 915 goto err; 916 } 917 918 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 919 IRQF_SHARED | IRQF_NO_THREAD, 920 rcar_msi_irq_chip.name, pcie); 921 if (err < 0) { 922 dev_err(dev, "failed to request IRQ: %d\n", err); 923 goto err; 924 } 925 926 /* setup MSI data target */ 927 msi->pages = __get_free_pages(GFP_KERNEL, 0); 928 base = virt_to_phys((void *)msi->pages); 929 930 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR); 931 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR); 932 933 /* enable all MSI interrupts */ 934 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); 935 936 return 0; 937 938 err: 939 rcar_pcie_unmap_msi(pcie); 940 return err; 941 } 942 943 static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie) 944 { 945 struct rcar_msi *msi = &pcie->msi; 946 947 /* Disable all MSI interrupts */ 948 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 949 950 /* Disable address decoding of the MSI interrupt, MSIFE */ 951 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 952 953 free_pages(msi->pages, 0); 954 955 rcar_pcie_unmap_msi(pcie); 956 } 957 958 static int rcar_pcie_get_resources(struct rcar_pcie *pcie) 959 { 960 struct device *dev = pcie->dev; 961 struct resource res; 962 int err, i; 963 964 pcie->phy = devm_phy_optional_get(dev, "pcie"); 965 if (IS_ERR(pcie->phy)) 966 return PTR_ERR(pcie->phy); 967 968 err = of_address_to_resource(dev->of_node, 0, &res); 969 if (err) 970 return err; 971 972 pcie->base = devm_ioremap_resource(dev, &res); 973 if (IS_ERR(pcie->base)) 974 return PTR_ERR(pcie->base); 975 976 pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); 977 if (IS_ERR(pcie->bus_clk)) { 978 dev_err(dev, "cannot get pcie bus clock\n"); 979 return PTR_ERR(pcie->bus_clk); 980 } 981 982 i = irq_of_parse_and_map(dev->of_node, 0); 983 if (!i) { 984 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 985 err = -ENOENT; 986 goto err_irq1; 987 } 988 pcie->msi.irq1 = i; 989 990 i = irq_of_parse_and_map(dev->of_node, 1); 991 if (!i) { 992 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 993 err = -ENOENT; 994 goto err_irq2; 995 } 996 pcie->msi.irq2 = i; 997 998 return 0; 999 1000 err_irq2: 1001 irq_dispose_mapping(pcie->msi.irq1); 1002 err_irq1: 1003 return err; 1004 } 1005 1006 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 1007 struct of_pci_range *range, 1008 int *index) 1009 { 1010 u64 restype = range->flags; 1011 u64 cpu_addr = range->cpu_addr; 1012 u64 cpu_end = range->cpu_addr + range->size; 1013 u64 pci_addr = range->pci_addr; 1014 u32 flags = LAM_64BIT | LAR_ENABLE; 1015 u64 mask; 1016 u64 size; 1017 int idx = *index; 1018 1019 if (restype & IORESOURCE_PREFETCH) 1020 flags |= LAM_PREFETCH; 1021 1022 /* 1023 * If the size of the range is larger than the alignment of the start 1024 * address, we have to use multiple entries to perform the mapping. 1025 */ 1026 if (cpu_addr > 0) { 1027 unsigned long nr_zeros = __ffs64(cpu_addr); 1028 u64 alignment = 1ULL << nr_zeros; 1029 1030 size = min(range->size, alignment); 1031 } else { 1032 size = range->size; 1033 } 1034 /* Hardware supports max 4GiB inbound region */ 1035 size = min(size, 1ULL << 32); 1036 1037 mask = roundup_pow_of_two(size) - 1; 1038 mask &= ~0xf; 1039 1040 while (cpu_addr < cpu_end) { 1041 /* 1042 * Set up 64-bit inbound regions as the range parser doesn't 1043 * distinguish between 32 and 64-bit types. 1044 */ 1045 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), 1046 PCIEPRAR(idx)); 1047 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); 1048 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, 1049 PCIELAMR(idx)); 1050 1051 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), 1052 PCIEPRAR(idx + 1)); 1053 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), 1054 PCIELAR(idx + 1)); 1055 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1)); 1056 1057 pci_addr += size; 1058 cpu_addr += size; 1059 idx += 2; 1060 1061 if (idx > MAX_NR_INBOUND_MAPS) { 1062 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 1063 return -EINVAL; 1064 } 1065 } 1066 *index = idx; 1067 1068 return 0; 1069 } 1070 1071 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie, 1072 struct device_node *np) 1073 { 1074 struct of_pci_range range; 1075 struct of_pci_range_parser parser; 1076 int index = 0; 1077 int err; 1078 1079 if (of_pci_dma_range_parser_init(&parser, np)) 1080 return -EINVAL; 1081 1082 /* Get the dma-ranges from DT */ 1083 for_each_of_pci_range(&parser, &range) { 1084 u64 end = range.cpu_addr + range.size - 1; 1085 1086 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", 1087 range.flags, range.cpu_addr, end, range.pci_addr); 1088 1089 err = rcar_pcie_inbound_ranges(pcie, &range, &index); 1090 if (err) 1091 return err; 1092 } 1093 1094 return 0; 1095 } 1096 1097 static const struct of_device_id rcar_pcie_of_match[] = { 1098 { .compatible = "renesas,pcie-r8a7779", 1099 .data = rcar_pcie_phy_init_h1 }, 1100 { .compatible = "renesas,pcie-r8a7790", 1101 .data = rcar_pcie_phy_init_gen2 }, 1102 { .compatible = "renesas,pcie-r8a7791", 1103 .data = rcar_pcie_phy_init_gen2 }, 1104 { .compatible = "renesas,pcie-rcar-gen2", 1105 .data = rcar_pcie_phy_init_gen2 }, 1106 { .compatible = "renesas,pcie-r8a7795", 1107 .data = rcar_pcie_phy_init_gen3 }, 1108 { .compatible = "renesas,pcie-rcar-gen3", 1109 .data = rcar_pcie_phy_init_gen3 }, 1110 {}, 1111 }; 1112 1113 static int rcar_pcie_probe(struct platform_device *pdev) 1114 { 1115 struct device *dev = &pdev->dev; 1116 struct rcar_pcie *pcie; 1117 unsigned int data; 1118 int err; 1119 int (*phy_init_fn)(struct rcar_pcie *); 1120 struct pci_host_bridge *bridge; 1121 1122 bridge = pci_alloc_host_bridge(sizeof(*pcie)); 1123 if (!bridge) 1124 return -ENOMEM; 1125 1126 pcie = pci_host_bridge_priv(bridge); 1127 1128 pcie->dev = dev; 1129 1130 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL); 1131 if (err) 1132 goto err_free_bridge; 1133 1134 pm_runtime_enable(pcie->dev); 1135 err = pm_runtime_get_sync(pcie->dev); 1136 if (err < 0) { 1137 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 1138 goto err_pm_disable; 1139 } 1140 1141 err = rcar_pcie_get_resources(pcie); 1142 if (err < 0) { 1143 dev_err(dev, "failed to request resources: %d\n", err); 1144 goto err_pm_put; 1145 } 1146 1147 err = clk_prepare_enable(pcie->bus_clk); 1148 if (err) { 1149 dev_err(dev, "failed to enable bus clock: %d\n", err); 1150 goto err_unmap_msi_irqs; 1151 } 1152 1153 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node); 1154 if (err) 1155 goto err_clk_disable; 1156 1157 phy_init_fn = of_device_get_match_data(dev); 1158 err = phy_init_fn(pcie); 1159 if (err) { 1160 dev_err(dev, "failed to init PCIe PHY\n"); 1161 goto err_clk_disable; 1162 } 1163 1164 /* Failure to get a link might just be that no cards are inserted */ 1165 if (rcar_pcie_hw_init(pcie)) { 1166 dev_info(dev, "PCIe link down\n"); 1167 err = -ENODEV; 1168 goto err_clk_disable; 1169 } 1170 1171 data = rcar_pci_read_reg(pcie, MACSR); 1172 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1173 1174 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1175 err = rcar_pcie_enable_msi(pcie); 1176 if (err < 0) { 1177 dev_err(dev, 1178 "failed to enable MSI support: %d\n", 1179 err); 1180 goto err_clk_disable; 1181 } 1182 } 1183 1184 err = rcar_pcie_enable(pcie); 1185 if (err) 1186 goto err_msi_teardown; 1187 1188 return 0; 1189 1190 err_msi_teardown: 1191 if (IS_ENABLED(CONFIG_PCI_MSI)) 1192 rcar_pcie_teardown_msi(pcie); 1193 1194 err_clk_disable: 1195 clk_disable_unprepare(pcie->bus_clk); 1196 1197 err_unmap_msi_irqs: 1198 irq_dispose_mapping(pcie->msi.irq2); 1199 irq_dispose_mapping(pcie->msi.irq1); 1200 1201 err_pm_put: 1202 pm_runtime_put(dev); 1203 1204 err_pm_disable: 1205 pm_runtime_disable(dev); 1206 pci_free_resource_list(&pcie->resources); 1207 1208 err_free_bridge: 1209 pci_free_host_bridge(bridge); 1210 1211 return err; 1212 } 1213 1214 static struct platform_driver rcar_pcie_driver = { 1215 .driver = { 1216 .name = "rcar-pcie", 1217 .of_match_table = rcar_pcie_of_match, 1218 .suppress_bind_attrs = true, 1219 }, 1220 .probe = rcar_pcie_probe, 1221 }; 1222 builtin_platform_driver(rcar_pcie_driver); 1223