1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/iopoll.h> 24 #include <linux/msi.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/pci.h> 29 #include <linux/phy/phy.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 33 #include "pcie-rcar.h" 34 35 struct rcar_msi { 36 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 37 struct irq_domain *domain; 38 struct mutex map_lock; 39 spinlock_t mask_lock; 40 int irq1; 41 int irq2; 42 }; 43 44 #ifdef CONFIG_ARM 45 /* 46 * Here we keep a static copy of the remapped PCIe controller address. 47 * This is only used on aarch32 systems, all of which have one single 48 * PCIe controller, to provide quick access to the PCIe controller in 49 * the L1 link state fixup function, called from the ARM fault handler. 50 */ 51 static void __iomem *pcie_base; 52 /* 53 * Static copy of PCIe device pointer, so we can check whether the 54 * device is runtime suspended or not. 55 */ 56 static struct device *pcie_dev; 57 #endif 58 59 /* Structure representing the PCIe interface */ 60 struct rcar_pcie_host { 61 struct rcar_pcie pcie; 62 struct phy *phy; 63 struct clk *bus_clk; 64 struct rcar_msi msi; 65 int (*phy_init_fn)(struct rcar_pcie_host *host); 66 }; 67 68 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 69 { 70 return container_of(msi, struct rcar_pcie_host, msi); 71 } 72 73 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 74 { 75 unsigned int shift = BITS_PER_BYTE * (where & 3); 76 u32 val = rcar_pci_read_reg(pcie, where & ~3); 77 78 return val >> shift; 79 } 80 81 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 82 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 83 unsigned char access_type, struct pci_bus *bus, 84 unsigned int devfn, int where, u32 *data) 85 { 86 struct rcar_pcie *pcie = &host->pcie; 87 unsigned int dev, func, reg, index; 88 89 dev = PCI_SLOT(devfn); 90 func = PCI_FUNC(devfn); 91 reg = where & ~3; 92 index = reg / 4; 93 94 /* 95 * While each channel has its own memory-mapped extended config 96 * space, it's generally only accessible when in endpoint mode. 97 * When in root complex mode, the controller is unable to target 98 * itself with either type 0 or type 1 accesses, and indeed, any 99 * controller initiated target transfer to its own config space 100 * result in a completer abort. 101 * 102 * Each channel effectively only supports a single device, but as 103 * the same channel <-> device access works for any PCI_SLOT() 104 * value, we cheat a bit here and bind the controller's config 105 * space to devfn 0 in order to enable self-enumeration. In this 106 * case the regular ECAR/ECDR path is sidelined and the mangled 107 * config access itself is initiated as an internal bus transaction. 108 */ 109 if (pci_is_root_bus(bus)) { 110 if (dev != 0) 111 return PCIBIOS_DEVICE_NOT_FOUND; 112 113 if (access_type == RCAR_PCI_ACCESS_READ) 114 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 115 else 116 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 117 118 return PCIBIOS_SUCCESSFUL; 119 } 120 121 /* Clear errors */ 122 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 123 124 /* Set the PIO address */ 125 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 126 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 127 128 /* Enable the configuration access */ 129 if (pci_is_root_bus(bus->parent)) 130 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); 131 else 132 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); 133 134 /* Check for errors */ 135 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 136 return PCIBIOS_DEVICE_NOT_FOUND; 137 138 /* Check for master and target aborts */ 139 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 140 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 141 return PCIBIOS_DEVICE_NOT_FOUND; 142 143 if (access_type == RCAR_PCI_ACCESS_READ) 144 *data = rcar_pci_read_reg(pcie, PCIECDR); 145 else 146 rcar_pci_write_reg(pcie, *data, PCIECDR); 147 148 /* Disable the configuration access */ 149 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 150 151 return PCIBIOS_SUCCESSFUL; 152 } 153 154 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 155 int where, int size, u32 *val) 156 { 157 struct rcar_pcie_host *host = bus->sysdata; 158 int ret; 159 160 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 161 bus, devfn, where, val); 162 if (ret != PCIBIOS_SUCCESSFUL) 163 return ret; 164 165 if (size == 1) 166 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 167 else if (size == 2) 168 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 169 170 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 171 bus->number, devfn, where, size, *val); 172 173 return ret; 174 } 175 176 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 177 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 178 int where, int size, u32 val) 179 { 180 struct rcar_pcie_host *host = bus->sysdata; 181 unsigned int shift; 182 u32 data; 183 int ret; 184 185 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 186 bus, devfn, where, &data); 187 if (ret != PCIBIOS_SUCCESSFUL) 188 return ret; 189 190 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 191 bus->number, devfn, where, size, val); 192 193 if (size == 1) { 194 shift = BITS_PER_BYTE * (where & 3); 195 data &= ~(0xff << shift); 196 data |= ((val & 0xff) << shift); 197 } else if (size == 2) { 198 shift = BITS_PER_BYTE * (where & 2); 199 data &= ~(0xffff << shift); 200 data |= ((val & 0xffff) << shift); 201 } else 202 data = val; 203 204 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 205 bus, devfn, where, &data); 206 207 return ret; 208 } 209 210 static struct pci_ops rcar_pcie_ops = { 211 .read = rcar_pcie_read_conf, 212 .write = rcar_pcie_write_conf, 213 }; 214 215 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 216 { 217 struct device *dev = pcie->dev; 218 unsigned int timeout = 1000; 219 u32 macsr; 220 221 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 222 return; 223 224 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 225 dev_err(dev, "Speed change already in progress\n"); 226 return; 227 } 228 229 macsr = rcar_pci_read_reg(pcie, MACSR); 230 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 231 goto done; 232 233 /* Set target link speed to 5.0 GT/s */ 234 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 235 PCI_EXP_LNKSTA_CLS_5_0GB); 236 237 /* Set speed change reason as intentional factor */ 238 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 239 240 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 241 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 242 rcar_pci_write_reg(pcie, macsr, MACSR); 243 244 /* Start link speed change */ 245 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 246 247 while (timeout--) { 248 macsr = rcar_pci_read_reg(pcie, MACSR); 249 if (macsr & SPCHGFIN) { 250 /* Clear the interrupt bits */ 251 rcar_pci_write_reg(pcie, macsr, MACSR); 252 253 if (macsr & SPCHGFAIL) 254 dev_err(dev, "Speed change failed\n"); 255 256 goto done; 257 } 258 259 msleep(1); 260 } 261 262 dev_err(dev, "Speed change timed out\n"); 263 264 done: 265 dev_info(dev, "Current link speed is %s GT/s\n", 266 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 267 } 268 269 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 270 { 271 struct rcar_pcie *pcie = &host->pcie; 272 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 273 struct resource_entry *win; 274 LIST_HEAD(res); 275 int i = 0; 276 277 /* Try setting 5 GT/s link speed */ 278 rcar_pcie_force_speedup(pcie); 279 280 /* Setup PCI resources */ 281 resource_list_for_each_entry(win, &bridge->windows) { 282 struct resource *res = win->res; 283 284 if (!res->flags) 285 continue; 286 287 switch (resource_type(res)) { 288 case IORESOURCE_IO: 289 case IORESOURCE_MEM: 290 rcar_pcie_set_outbound(pcie, i, win); 291 i++; 292 break; 293 } 294 } 295 } 296 297 static int rcar_pcie_enable(struct rcar_pcie_host *host) 298 { 299 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 300 301 rcar_pcie_hw_enable(host); 302 303 pci_add_flags(PCI_REASSIGN_ALL_BUS); 304 305 bridge->sysdata = host; 306 bridge->ops = &rcar_pcie_ops; 307 308 return pci_host_probe(bridge); 309 } 310 311 static int phy_wait_for_ack(struct rcar_pcie *pcie) 312 { 313 struct device *dev = pcie->dev; 314 unsigned int timeout = 100; 315 316 while (timeout--) { 317 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 318 return 0; 319 320 udelay(100); 321 } 322 323 dev_err(dev, "Access to PCIe phy timed out\n"); 324 325 return -ETIMEDOUT; 326 } 327 328 static void phy_write_reg(struct rcar_pcie *pcie, 329 unsigned int rate, u32 addr, 330 unsigned int lane, u32 data) 331 { 332 u32 phyaddr; 333 334 phyaddr = WRITE_CMD | 335 ((rate & 1) << RATE_POS) | 336 ((lane & 0xf) << LANE_POS) | 337 ((addr & 0xff) << ADR_POS); 338 339 /* Set write data */ 340 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 341 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 342 343 /* Ignore errors as they will be dealt with if the data link is down */ 344 phy_wait_for_ack(pcie); 345 346 /* Clear command */ 347 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 348 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 349 350 /* Ignore errors as they will be dealt with if the data link is down */ 351 phy_wait_for_ack(pcie); 352 } 353 354 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 355 { 356 int err; 357 358 /* Begin initialization */ 359 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 360 361 /* Set mode */ 362 rcar_pci_write_reg(pcie, 1, PCIEMSR); 363 364 err = rcar_pcie_wait_for_phyrdy(pcie); 365 if (err) 366 return err; 367 368 /* 369 * Initial header for port config space is type 1, set the device 370 * class to match. Hardware takes care of propagating the IDSETR 371 * settings, so there is no need to bother with a quirk. 372 */ 373 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); 374 375 /* 376 * Setup Secondary Bus Number & Subordinate Bus Number, even though 377 * they aren't used, to avoid bridge being detected as broken. 378 */ 379 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 380 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 381 382 /* Initialize default capabilities. */ 383 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 384 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 385 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 386 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 387 PCI_HEADER_TYPE_BRIDGE); 388 389 /* Enable data link layer active state reporting */ 390 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 391 PCI_EXP_LNKCAP_DLLLARC); 392 393 /* Write out the physical slot number = 0 */ 394 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 395 396 /* Set the completion timer timeout to the maximum 50ms. */ 397 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 398 399 /* Terminate list of capabilities (Next Capability Offset=0) */ 400 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 401 402 /* Enable MSI */ 403 if (IS_ENABLED(CONFIG_PCI_MSI)) 404 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 405 406 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 407 408 /* Finish initialization - establish a PCI Express link */ 409 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 410 411 /* This will timeout if we don't have a link. */ 412 err = rcar_pcie_wait_for_dl(pcie); 413 if (err) 414 return err; 415 416 /* Enable INTx interrupts */ 417 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 418 419 wmb(); 420 421 return 0; 422 } 423 424 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 425 { 426 struct rcar_pcie *pcie = &host->pcie; 427 428 /* Initialize the phy */ 429 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 430 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 431 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 432 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 433 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 434 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 435 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 436 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 437 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 438 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 439 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 440 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 441 442 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 443 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 444 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 445 446 return 0; 447 } 448 449 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 450 { 451 struct rcar_pcie *pcie = &host->pcie; 452 453 /* 454 * These settings come from the R-Car Series, 2nd Generation User's 455 * Manual, section 50.3.1 (2) Initialization of the physical layer. 456 */ 457 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 458 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 459 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 460 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 461 462 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 463 /* The following value is for DC connection, no termination resistor */ 464 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 465 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 466 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 467 468 return 0; 469 } 470 471 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 472 { 473 int err; 474 475 err = phy_init(host->phy); 476 if (err) 477 return err; 478 479 err = phy_power_on(host->phy); 480 if (err) 481 phy_exit(host->phy); 482 483 return err; 484 } 485 486 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 487 { 488 struct rcar_pcie_host *host = data; 489 struct rcar_pcie *pcie = &host->pcie; 490 struct rcar_msi *msi = &host->msi; 491 struct device *dev = pcie->dev; 492 unsigned long reg; 493 494 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 495 496 /* MSI & INTx share an interrupt - we only handle MSI here */ 497 if (!reg) 498 return IRQ_NONE; 499 500 while (reg) { 501 unsigned int index = find_first_bit(®, 32); 502 int ret; 503 504 ret = generic_handle_domain_irq(msi->domain->parent, index); 505 if (ret) { 506 /* Unknown MSI, just clear it */ 507 dev_dbg(dev, "unexpected MSI\n"); 508 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 509 } 510 511 /* see if there's any more pending in this vector */ 512 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 513 } 514 515 return IRQ_HANDLED; 516 } 517 518 static void rcar_msi_top_irq_ack(struct irq_data *d) 519 { 520 irq_chip_ack_parent(d); 521 } 522 523 static void rcar_msi_top_irq_mask(struct irq_data *d) 524 { 525 pci_msi_mask_irq(d); 526 irq_chip_mask_parent(d); 527 } 528 529 static void rcar_msi_top_irq_unmask(struct irq_data *d) 530 { 531 pci_msi_unmask_irq(d); 532 irq_chip_unmask_parent(d); 533 } 534 535 static struct irq_chip rcar_msi_top_chip = { 536 .name = "PCIe MSI", 537 .irq_ack = rcar_msi_top_irq_ack, 538 .irq_mask = rcar_msi_top_irq_mask, 539 .irq_unmask = rcar_msi_top_irq_unmask, 540 }; 541 542 static void rcar_msi_irq_ack(struct irq_data *d) 543 { 544 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 545 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 546 547 /* clear the interrupt */ 548 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 549 } 550 551 static void rcar_msi_irq_mask(struct irq_data *d) 552 { 553 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 554 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 555 unsigned long flags; 556 u32 value; 557 558 spin_lock_irqsave(&msi->mask_lock, flags); 559 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 560 value &= ~BIT(d->hwirq); 561 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 562 spin_unlock_irqrestore(&msi->mask_lock, flags); 563 } 564 565 static void rcar_msi_irq_unmask(struct irq_data *d) 566 { 567 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 568 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 569 unsigned long flags; 570 u32 value; 571 572 spin_lock_irqsave(&msi->mask_lock, flags); 573 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 574 value |= BIT(d->hwirq); 575 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 576 spin_unlock_irqrestore(&msi->mask_lock, flags); 577 } 578 579 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 580 { 581 return -EINVAL; 582 } 583 584 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 585 { 586 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 587 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 588 589 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 590 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 591 msg->data = data->hwirq; 592 } 593 594 static struct irq_chip rcar_msi_bottom_chip = { 595 .name = "Rcar MSI", 596 .irq_ack = rcar_msi_irq_ack, 597 .irq_mask = rcar_msi_irq_mask, 598 .irq_unmask = rcar_msi_irq_unmask, 599 .irq_set_affinity = rcar_msi_set_affinity, 600 .irq_compose_msi_msg = rcar_compose_msi_msg, 601 }; 602 603 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 604 unsigned int nr_irqs, void *args) 605 { 606 struct rcar_msi *msi = domain->host_data; 607 unsigned int i; 608 int hwirq; 609 610 mutex_lock(&msi->map_lock); 611 612 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 613 614 mutex_unlock(&msi->map_lock); 615 616 if (hwirq < 0) 617 return -ENOSPC; 618 619 for (i = 0; i < nr_irqs; i++) 620 irq_domain_set_info(domain, virq + i, hwirq + i, 621 &rcar_msi_bottom_chip, domain->host_data, 622 handle_edge_irq, NULL, NULL); 623 624 return 0; 625 } 626 627 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 628 unsigned int nr_irqs) 629 { 630 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 631 struct rcar_msi *msi = domain->host_data; 632 633 mutex_lock(&msi->map_lock); 634 635 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 636 637 mutex_unlock(&msi->map_lock); 638 } 639 640 static const struct irq_domain_ops rcar_msi_domain_ops = { 641 .alloc = rcar_msi_domain_alloc, 642 .free = rcar_msi_domain_free, 643 }; 644 645 static struct msi_domain_info rcar_msi_info = { 646 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 647 MSI_FLAG_MULTI_PCI_MSI), 648 .chip = &rcar_msi_top_chip, 649 }; 650 651 static int rcar_allocate_domains(struct rcar_msi *msi) 652 { 653 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 654 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); 655 struct irq_domain *parent; 656 657 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR, 658 &rcar_msi_domain_ops, msi); 659 if (!parent) { 660 dev_err(pcie->dev, "failed to create IRQ domain\n"); 661 return -ENOMEM; 662 } 663 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 664 665 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent); 666 if (!msi->domain) { 667 dev_err(pcie->dev, "failed to create MSI domain\n"); 668 irq_domain_remove(parent); 669 return -ENOMEM; 670 } 671 672 return 0; 673 } 674 675 static void rcar_free_domains(struct rcar_msi *msi) 676 { 677 struct irq_domain *parent = msi->domain->parent; 678 679 irq_domain_remove(msi->domain); 680 irq_domain_remove(parent); 681 } 682 683 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 684 { 685 struct rcar_pcie *pcie = &host->pcie; 686 struct device *dev = pcie->dev; 687 struct rcar_msi *msi = &host->msi; 688 struct resource res; 689 int err; 690 691 mutex_init(&msi->map_lock); 692 spin_lock_init(&msi->mask_lock); 693 694 err = of_address_to_resource(dev->of_node, 0, &res); 695 if (err) 696 return err; 697 698 err = rcar_allocate_domains(msi); 699 if (err) 700 return err; 701 702 /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 703 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 704 IRQF_SHARED | IRQF_NO_THREAD, 705 rcar_msi_bottom_chip.name, host); 706 if (err < 0) { 707 dev_err(dev, "failed to request IRQ: %d\n", err); 708 goto err; 709 } 710 711 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 712 IRQF_SHARED | IRQF_NO_THREAD, 713 rcar_msi_bottom_chip.name, host); 714 if (err < 0) { 715 dev_err(dev, "failed to request IRQ: %d\n", err); 716 goto err; 717 } 718 719 /* disable all MSIs */ 720 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 721 722 /* 723 * Setup MSI data target using RC base address address, which 724 * is guaranteed to be in the low 32bit range on any RCar HW. 725 */ 726 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 727 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 728 729 return 0; 730 731 err: 732 rcar_free_domains(msi); 733 return err; 734 } 735 736 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 737 { 738 struct rcar_pcie *pcie = &host->pcie; 739 740 /* Disable all MSI interrupts */ 741 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 742 743 /* Disable address decoding of the MSI interrupt, MSIFE */ 744 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 745 746 rcar_free_domains(&host->msi); 747 } 748 749 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 750 { 751 struct rcar_pcie *pcie = &host->pcie; 752 struct device *dev = pcie->dev; 753 struct resource res; 754 int err, i; 755 756 host->phy = devm_phy_optional_get(dev, "pcie"); 757 if (IS_ERR(host->phy)) 758 return PTR_ERR(host->phy); 759 760 err = of_address_to_resource(dev->of_node, 0, &res); 761 if (err) 762 return err; 763 764 pcie->base = devm_ioremap_resource(dev, &res); 765 if (IS_ERR(pcie->base)) 766 return PTR_ERR(pcie->base); 767 768 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 769 if (IS_ERR(host->bus_clk)) { 770 dev_err(dev, "cannot get pcie bus clock\n"); 771 return PTR_ERR(host->bus_clk); 772 } 773 774 i = irq_of_parse_and_map(dev->of_node, 0); 775 if (!i) { 776 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 777 err = -ENOENT; 778 goto err_irq1; 779 } 780 host->msi.irq1 = i; 781 782 i = irq_of_parse_and_map(dev->of_node, 1); 783 if (!i) { 784 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 785 err = -ENOENT; 786 goto err_irq2; 787 } 788 host->msi.irq2 = i; 789 790 #ifdef CONFIG_ARM 791 /* Cache static copy for L1 link state fixup hook on aarch32 */ 792 pcie_base = pcie->base; 793 pcie_dev = pcie->dev; 794 #endif 795 796 return 0; 797 798 err_irq2: 799 irq_dispose_mapping(host->msi.irq1); 800 err_irq1: 801 return err; 802 } 803 804 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 805 struct resource_entry *entry, 806 int *index) 807 { 808 u64 restype = entry->res->flags; 809 u64 cpu_addr = entry->res->start; 810 u64 cpu_end = entry->res->end; 811 u64 pci_addr = entry->res->start - entry->offset; 812 u32 flags = LAM_64BIT | LAR_ENABLE; 813 u64 mask; 814 u64 size = resource_size(entry->res); 815 int idx = *index; 816 817 if (restype & IORESOURCE_PREFETCH) 818 flags |= LAM_PREFETCH; 819 820 while (cpu_addr < cpu_end) { 821 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 822 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 823 return -EINVAL; 824 } 825 /* 826 * If the size of the range is larger than the alignment of 827 * the start address, we have to use multiple entries to 828 * perform the mapping. 829 */ 830 if (cpu_addr > 0) { 831 unsigned long nr_zeros = __ffs64(cpu_addr); 832 u64 alignment = 1ULL << nr_zeros; 833 834 size = min(size, alignment); 835 } 836 /* Hardware supports max 4GiB inbound region */ 837 size = min(size, 1ULL << 32); 838 839 mask = roundup_pow_of_two(size) - 1; 840 mask &= ~0xf; 841 842 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 843 lower_32_bits(mask) | flags, idx, true); 844 845 pci_addr += size; 846 cpu_addr += size; 847 idx += 2; 848 } 849 *index = idx; 850 851 return 0; 852 } 853 854 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 855 { 856 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 857 struct resource_entry *entry; 858 int index = 0, err = 0; 859 860 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 861 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 862 if (err) 863 break; 864 } 865 866 return err; 867 } 868 869 static const struct of_device_id rcar_pcie_of_match[] = { 870 { .compatible = "renesas,pcie-r8a7779", 871 .data = rcar_pcie_phy_init_h1 }, 872 { .compatible = "renesas,pcie-r8a7790", 873 .data = rcar_pcie_phy_init_gen2 }, 874 { .compatible = "renesas,pcie-r8a7791", 875 .data = rcar_pcie_phy_init_gen2 }, 876 { .compatible = "renesas,pcie-rcar-gen2", 877 .data = rcar_pcie_phy_init_gen2 }, 878 { .compatible = "renesas,pcie-r8a7795", 879 .data = rcar_pcie_phy_init_gen3 }, 880 { .compatible = "renesas,pcie-rcar-gen3", 881 .data = rcar_pcie_phy_init_gen3 }, 882 {}, 883 }; 884 885 static int rcar_pcie_probe(struct platform_device *pdev) 886 { 887 struct device *dev = &pdev->dev; 888 struct rcar_pcie_host *host; 889 struct rcar_pcie *pcie; 890 u32 data; 891 int err; 892 struct pci_host_bridge *bridge; 893 894 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 895 if (!bridge) 896 return -ENOMEM; 897 898 host = pci_host_bridge_priv(bridge); 899 pcie = &host->pcie; 900 pcie->dev = dev; 901 platform_set_drvdata(pdev, host); 902 903 pm_runtime_enable(pcie->dev); 904 err = pm_runtime_get_sync(pcie->dev); 905 if (err < 0) { 906 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 907 goto err_pm_put; 908 } 909 910 err = rcar_pcie_get_resources(host); 911 if (err < 0) { 912 dev_err(dev, "failed to request resources: %d\n", err); 913 goto err_pm_put; 914 } 915 916 err = clk_prepare_enable(host->bus_clk); 917 if (err) { 918 dev_err(dev, "failed to enable bus clock: %d\n", err); 919 goto err_unmap_msi_irqs; 920 } 921 922 err = rcar_pcie_parse_map_dma_ranges(host); 923 if (err) 924 goto err_clk_disable; 925 926 host->phy_init_fn = of_device_get_match_data(dev); 927 err = host->phy_init_fn(host); 928 if (err) { 929 dev_err(dev, "failed to init PCIe PHY\n"); 930 goto err_clk_disable; 931 } 932 933 /* Failure to get a link might just be that no cards are inserted */ 934 if (rcar_pcie_hw_init(pcie)) { 935 dev_info(dev, "PCIe link down\n"); 936 err = -ENODEV; 937 goto err_phy_shutdown; 938 } 939 940 data = rcar_pci_read_reg(pcie, MACSR); 941 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 942 943 if (IS_ENABLED(CONFIG_PCI_MSI)) { 944 err = rcar_pcie_enable_msi(host); 945 if (err < 0) { 946 dev_err(dev, 947 "failed to enable MSI support: %d\n", 948 err); 949 goto err_phy_shutdown; 950 } 951 } 952 953 err = rcar_pcie_enable(host); 954 if (err) 955 goto err_msi_teardown; 956 957 return 0; 958 959 err_msi_teardown: 960 if (IS_ENABLED(CONFIG_PCI_MSI)) 961 rcar_pcie_teardown_msi(host); 962 963 err_phy_shutdown: 964 if (host->phy) { 965 phy_power_off(host->phy); 966 phy_exit(host->phy); 967 } 968 969 err_clk_disable: 970 clk_disable_unprepare(host->bus_clk); 971 972 err_unmap_msi_irqs: 973 irq_dispose_mapping(host->msi.irq2); 974 irq_dispose_mapping(host->msi.irq1); 975 976 err_pm_put: 977 pm_runtime_put(dev); 978 pm_runtime_disable(dev); 979 980 return err; 981 } 982 983 static int __maybe_unused rcar_pcie_resume(struct device *dev) 984 { 985 struct rcar_pcie_host *host = dev_get_drvdata(dev); 986 struct rcar_pcie *pcie = &host->pcie; 987 unsigned int data; 988 int err; 989 990 err = rcar_pcie_parse_map_dma_ranges(host); 991 if (err) 992 return 0; 993 994 /* Failure to get a link might just be that no cards are inserted */ 995 err = host->phy_init_fn(host); 996 if (err) { 997 dev_info(dev, "PCIe link down\n"); 998 return 0; 999 } 1000 1001 data = rcar_pci_read_reg(pcie, MACSR); 1002 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1003 1004 /* Enable MSI */ 1005 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1006 struct resource res; 1007 u32 val; 1008 1009 of_address_to_resource(dev->of_node, 0, &res); 1010 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1011 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1012 1013 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1014 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1015 } 1016 1017 rcar_pcie_hw_enable(host); 1018 1019 return 0; 1020 } 1021 1022 static int rcar_pcie_resume_noirq(struct device *dev) 1023 { 1024 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1025 struct rcar_pcie *pcie = &host->pcie; 1026 1027 if (rcar_pci_read_reg(pcie, PMSR) && 1028 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1029 return 0; 1030 1031 /* Re-establish the PCIe link */ 1032 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1033 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1034 return rcar_pcie_wait_for_dl(pcie); 1035 } 1036 1037 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1038 SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1039 .resume_noirq = rcar_pcie_resume_noirq, 1040 }; 1041 1042 static struct platform_driver rcar_pcie_driver = { 1043 .driver = { 1044 .name = "rcar-pcie", 1045 .of_match_table = rcar_pcie_of_match, 1046 .pm = &rcar_pcie_pm_ops, 1047 .suppress_bind_attrs = true, 1048 }, 1049 .probe = rcar_pcie_probe, 1050 }; 1051 1052 #ifdef CONFIG_ARM 1053 static DEFINE_SPINLOCK(pmsr_lock); 1054 static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1055 unsigned int fsr, struct pt_regs *regs) 1056 { 1057 unsigned long flags; 1058 u32 pmsr, val; 1059 int ret = 0; 1060 1061 spin_lock_irqsave(&pmsr_lock, flags); 1062 1063 if (!pcie_base || pm_runtime_suspended(pcie_dev)) { 1064 ret = 1; 1065 goto unlock_exit; 1066 } 1067 1068 pmsr = readl(pcie_base + PMSR); 1069 1070 /* 1071 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 1072 * the PCIe controller is not in L1 link state. If true, apply 1073 * fix, which will put the controller into L1 link state, from 1074 * which it can return to L0s/L0 on its own. 1075 */ 1076 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 1077 writel(L1IATN, pcie_base + PMCTLR); 1078 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 1079 val & L1FAEG, 10, 1000); 1080 WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret); 1081 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 1082 } 1083 1084 unlock_exit: 1085 spin_unlock_irqrestore(&pmsr_lock, flags); 1086 return ret; 1087 } 1088 1089 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1090 { .compatible = "renesas,pcie-r8a7779" }, 1091 { .compatible = "renesas,pcie-r8a7790" }, 1092 { .compatible = "renesas,pcie-r8a7791" }, 1093 { .compatible = "renesas,pcie-rcar-gen2" }, 1094 {}, 1095 }; 1096 1097 static int __init rcar_pcie_init(void) 1098 { 1099 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1100 #ifdef CONFIG_ARM_LPAE 1101 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1102 "asynchronous external abort"); 1103 #else 1104 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1105 "imprecise external abort"); 1106 #endif 1107 } 1108 1109 return platform_driver_register(&rcar_pcie_driver); 1110 } 1111 device_initcall(rcar_pcie_init); 1112 #else 1113 builtin_platform_driver(rcar_pcie_driver); 1114 #endif 1115