1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/msi.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_pci.h> 26 #include <linux/of_platform.h> 27 #include <linux/pci.h> 28 #include <linux/phy/phy.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/slab.h> 32 33 #include "pcie-rcar.h" 34 35 struct rcar_msi { 36 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 37 struct irq_domain *domain; 38 struct msi_controller chip; 39 unsigned long pages; 40 struct mutex lock; 41 int irq1; 42 int irq2; 43 }; 44 45 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) 46 { 47 return container_of(chip, struct rcar_msi, chip); 48 } 49 50 /* Structure representing the PCIe interface */ 51 struct rcar_pcie_host { 52 struct rcar_pcie pcie; 53 struct phy *phy; 54 struct clk *bus_clk; 55 struct rcar_msi msi; 56 int (*phy_init_fn)(struct rcar_pcie_host *host); 57 }; 58 59 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 60 { 61 unsigned int shift = BITS_PER_BYTE * (where & 3); 62 u32 val = rcar_pci_read_reg(pcie, where & ~3); 63 64 return val >> shift; 65 } 66 67 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 68 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 69 unsigned char access_type, struct pci_bus *bus, 70 unsigned int devfn, int where, u32 *data) 71 { 72 struct rcar_pcie *pcie = &host->pcie; 73 unsigned int dev, func, reg, index; 74 75 dev = PCI_SLOT(devfn); 76 func = PCI_FUNC(devfn); 77 reg = where & ~3; 78 index = reg / 4; 79 80 /* 81 * While each channel has its own memory-mapped extended config 82 * space, it's generally only accessible when in endpoint mode. 83 * When in root complex mode, the controller is unable to target 84 * itself with either type 0 or type 1 accesses, and indeed, any 85 * controller initiated target transfer to its own config space 86 * result in a completer abort. 87 * 88 * Each channel effectively only supports a single device, but as 89 * the same channel <-> device access works for any PCI_SLOT() 90 * value, we cheat a bit here and bind the controller's config 91 * space to devfn 0 in order to enable self-enumeration. In this 92 * case the regular ECAR/ECDR path is sidelined and the mangled 93 * config access itself is initiated as an internal bus transaction. 94 */ 95 if (pci_is_root_bus(bus)) { 96 if (dev != 0) 97 return PCIBIOS_DEVICE_NOT_FOUND; 98 99 if (access_type == RCAR_PCI_ACCESS_READ) 100 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 101 else 102 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 103 104 return PCIBIOS_SUCCESSFUL; 105 } 106 107 /* Clear errors */ 108 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 109 110 /* Set the PIO address */ 111 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 112 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 113 114 /* Enable the configuration access */ 115 if (pci_is_root_bus(bus->parent)) 116 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); 117 else 118 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); 119 120 /* Check for errors */ 121 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 122 return PCIBIOS_DEVICE_NOT_FOUND; 123 124 /* Check for master and target aborts */ 125 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 126 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 127 return PCIBIOS_DEVICE_NOT_FOUND; 128 129 if (access_type == RCAR_PCI_ACCESS_READ) 130 *data = rcar_pci_read_reg(pcie, PCIECDR); 131 else 132 rcar_pci_write_reg(pcie, *data, PCIECDR); 133 134 /* Disable the configuration access */ 135 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 136 137 return PCIBIOS_SUCCESSFUL; 138 } 139 140 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 141 int where, int size, u32 *val) 142 { 143 struct rcar_pcie_host *host = bus->sysdata; 144 int ret; 145 146 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 147 bus, devfn, where, val); 148 if (ret != PCIBIOS_SUCCESSFUL) { 149 *val = 0xffffffff; 150 return ret; 151 } 152 153 if (size == 1) 154 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 155 else if (size == 2) 156 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 157 158 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 159 bus->number, devfn, where, size, *val); 160 161 return ret; 162 } 163 164 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 165 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 166 int where, int size, u32 val) 167 { 168 struct rcar_pcie_host *host = bus->sysdata; 169 unsigned int shift; 170 u32 data; 171 int ret; 172 173 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 174 bus, devfn, where, &data); 175 if (ret != PCIBIOS_SUCCESSFUL) 176 return ret; 177 178 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 179 bus->number, devfn, where, size, val); 180 181 if (size == 1) { 182 shift = BITS_PER_BYTE * (where & 3); 183 data &= ~(0xff << shift); 184 data |= ((val & 0xff) << shift); 185 } else if (size == 2) { 186 shift = BITS_PER_BYTE * (where & 2); 187 data &= ~(0xffff << shift); 188 data |= ((val & 0xffff) << shift); 189 } else 190 data = val; 191 192 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 193 bus, devfn, where, &data); 194 195 return ret; 196 } 197 198 static struct pci_ops rcar_pcie_ops = { 199 .read = rcar_pcie_read_conf, 200 .write = rcar_pcie_write_conf, 201 }; 202 203 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 204 { 205 struct device *dev = pcie->dev; 206 unsigned int timeout = 1000; 207 u32 macsr; 208 209 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 210 return; 211 212 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 213 dev_err(dev, "Speed change already in progress\n"); 214 return; 215 } 216 217 macsr = rcar_pci_read_reg(pcie, MACSR); 218 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 219 goto done; 220 221 /* Set target link speed to 5.0 GT/s */ 222 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 223 PCI_EXP_LNKSTA_CLS_5_0GB); 224 225 /* Set speed change reason as intentional factor */ 226 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 227 228 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 229 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 230 rcar_pci_write_reg(pcie, macsr, MACSR); 231 232 /* Start link speed change */ 233 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 234 235 while (timeout--) { 236 macsr = rcar_pci_read_reg(pcie, MACSR); 237 if (macsr & SPCHGFIN) { 238 /* Clear the interrupt bits */ 239 rcar_pci_write_reg(pcie, macsr, MACSR); 240 241 if (macsr & SPCHGFAIL) 242 dev_err(dev, "Speed change failed\n"); 243 244 goto done; 245 } 246 247 msleep(1); 248 } 249 250 dev_err(dev, "Speed change timed out\n"); 251 252 done: 253 dev_info(dev, "Current link speed is %s GT/s\n", 254 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 255 } 256 257 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 258 { 259 struct rcar_pcie *pcie = &host->pcie; 260 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 261 struct resource_entry *win; 262 LIST_HEAD(res); 263 int i = 0; 264 265 /* Try setting 5 GT/s link speed */ 266 rcar_pcie_force_speedup(pcie); 267 268 /* Setup PCI resources */ 269 resource_list_for_each_entry(win, &bridge->windows) { 270 struct resource *res = win->res; 271 272 if (!res->flags) 273 continue; 274 275 switch (resource_type(res)) { 276 case IORESOURCE_IO: 277 case IORESOURCE_MEM: 278 rcar_pcie_set_outbound(pcie, i, win); 279 i++; 280 break; 281 } 282 } 283 } 284 285 static int rcar_pcie_enable(struct rcar_pcie_host *host) 286 { 287 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 288 289 rcar_pcie_hw_enable(host); 290 291 pci_add_flags(PCI_REASSIGN_ALL_BUS); 292 293 bridge->sysdata = host; 294 bridge->ops = &rcar_pcie_ops; 295 if (IS_ENABLED(CONFIG_PCI_MSI)) 296 bridge->msi = &host->msi.chip; 297 298 return pci_host_probe(bridge); 299 } 300 301 static int phy_wait_for_ack(struct rcar_pcie *pcie) 302 { 303 struct device *dev = pcie->dev; 304 unsigned int timeout = 100; 305 306 while (timeout--) { 307 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 308 return 0; 309 310 udelay(100); 311 } 312 313 dev_err(dev, "Access to PCIe phy timed out\n"); 314 315 return -ETIMEDOUT; 316 } 317 318 static void phy_write_reg(struct rcar_pcie *pcie, 319 unsigned int rate, u32 addr, 320 unsigned int lane, u32 data) 321 { 322 u32 phyaddr; 323 324 phyaddr = WRITE_CMD | 325 ((rate & 1) << RATE_POS) | 326 ((lane & 0xf) << LANE_POS) | 327 ((addr & 0xff) << ADR_POS); 328 329 /* Set write data */ 330 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 331 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 332 333 /* Ignore errors as they will be dealt with if the data link is down */ 334 phy_wait_for_ack(pcie); 335 336 /* Clear command */ 337 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 338 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 339 340 /* Ignore errors as they will be dealt with if the data link is down */ 341 phy_wait_for_ack(pcie); 342 } 343 344 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 345 { 346 int err; 347 348 /* Begin initialization */ 349 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 350 351 /* Set mode */ 352 rcar_pci_write_reg(pcie, 1, PCIEMSR); 353 354 err = rcar_pcie_wait_for_phyrdy(pcie); 355 if (err) 356 return err; 357 358 /* 359 * Initial header for port config space is type 1, set the device 360 * class to match. Hardware takes care of propagating the IDSETR 361 * settings, so there is no need to bother with a quirk. 362 */ 363 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); 364 365 /* 366 * Setup Secondary Bus Number & Subordinate Bus Number, even though 367 * they aren't used, to avoid bridge being detected as broken. 368 */ 369 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 370 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 371 372 /* Initialize default capabilities. */ 373 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 374 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 375 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 376 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 377 PCI_HEADER_TYPE_BRIDGE); 378 379 /* Enable data link layer active state reporting */ 380 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 381 PCI_EXP_LNKCAP_DLLLARC); 382 383 /* Write out the physical slot number = 0 */ 384 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 385 386 /* Set the completion timer timeout to the maximum 50ms. */ 387 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 388 389 /* Terminate list of capabilities (Next Capability Offset=0) */ 390 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 391 392 /* Enable MSI */ 393 if (IS_ENABLED(CONFIG_PCI_MSI)) 394 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 395 396 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 397 398 /* Finish initialization - establish a PCI Express link */ 399 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 400 401 /* This will timeout if we don't have a link. */ 402 err = rcar_pcie_wait_for_dl(pcie); 403 if (err) 404 return err; 405 406 /* Enable INTx interrupts */ 407 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 408 409 wmb(); 410 411 return 0; 412 } 413 414 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 415 { 416 struct rcar_pcie *pcie = &host->pcie; 417 418 /* Initialize the phy */ 419 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 420 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 421 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 422 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 423 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 424 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 425 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 426 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 427 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 428 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 429 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 430 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 431 432 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 433 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 434 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 435 436 return 0; 437 } 438 439 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 440 { 441 struct rcar_pcie *pcie = &host->pcie; 442 443 /* 444 * These settings come from the R-Car Series, 2nd Generation User's 445 * Manual, section 50.3.1 (2) Initialization of the physical layer. 446 */ 447 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 448 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 449 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 450 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 451 452 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 453 /* The following value is for DC connection, no termination resistor */ 454 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 455 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 456 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 457 458 return 0; 459 } 460 461 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 462 { 463 int err; 464 465 err = phy_init(host->phy); 466 if (err) 467 return err; 468 469 err = phy_power_on(host->phy); 470 if (err) 471 phy_exit(host->phy); 472 473 return err; 474 } 475 476 static int rcar_msi_alloc(struct rcar_msi *chip) 477 { 478 int msi; 479 480 mutex_lock(&chip->lock); 481 482 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); 483 if (msi < INT_PCI_MSI_NR) 484 set_bit(msi, chip->used); 485 else 486 msi = -ENOSPC; 487 488 mutex_unlock(&chip->lock); 489 490 return msi; 491 } 492 493 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) 494 { 495 int msi; 496 497 mutex_lock(&chip->lock); 498 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, 499 order_base_2(no_irqs)); 500 mutex_unlock(&chip->lock); 501 502 return msi; 503 } 504 505 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) 506 { 507 mutex_lock(&chip->lock); 508 clear_bit(irq, chip->used); 509 mutex_unlock(&chip->lock); 510 } 511 512 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 513 { 514 struct rcar_pcie_host *host = data; 515 struct rcar_pcie *pcie = &host->pcie; 516 struct rcar_msi *msi = &host->msi; 517 struct device *dev = pcie->dev; 518 unsigned long reg; 519 520 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 521 522 /* MSI & INTx share an interrupt - we only handle MSI here */ 523 if (!reg) 524 return IRQ_NONE; 525 526 while (reg) { 527 unsigned int index = find_first_bit(®, 32); 528 unsigned int msi_irq; 529 530 /* clear the interrupt */ 531 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); 532 533 msi_irq = irq_find_mapping(msi->domain, index); 534 if (msi_irq) { 535 if (test_bit(index, msi->used)) 536 generic_handle_irq(msi_irq); 537 else 538 dev_info(dev, "unhandled MSI\n"); 539 } else { 540 /* Unknown MSI, just clear it */ 541 dev_dbg(dev, "unexpected MSI\n"); 542 } 543 544 /* see if there's any more pending in this vector */ 545 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 546 } 547 548 return IRQ_HANDLED; 549 } 550 551 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, 552 struct msi_desc *desc) 553 { 554 struct rcar_msi *msi = to_rcar_msi(chip); 555 struct rcar_pcie_host *host = container_of(chip, struct rcar_pcie_host, 556 msi.chip); 557 struct rcar_pcie *pcie = &host->pcie; 558 struct msi_msg msg; 559 unsigned int irq; 560 int hwirq; 561 562 hwirq = rcar_msi_alloc(msi); 563 if (hwirq < 0) 564 return hwirq; 565 566 irq = irq_find_mapping(msi->domain, hwirq); 567 if (!irq) { 568 rcar_msi_free(msi, hwirq); 569 return -EINVAL; 570 } 571 572 irq_set_msi_desc(irq, desc); 573 574 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 575 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 576 msg.data = hwirq; 577 578 pci_write_msi_msg(irq, &msg); 579 580 return 0; 581 } 582 583 static int rcar_msi_setup_irqs(struct msi_controller *chip, 584 struct pci_dev *pdev, int nvec, int type) 585 { 586 struct rcar_msi *msi = to_rcar_msi(chip); 587 struct rcar_pcie_host *host = container_of(chip, struct rcar_pcie_host, 588 msi.chip); 589 struct rcar_pcie *pcie = &host->pcie; 590 struct msi_desc *desc; 591 struct msi_msg msg; 592 unsigned int irq; 593 int hwirq; 594 int i; 595 596 /* MSI-X interrupts are not supported */ 597 if (type == PCI_CAP_ID_MSIX) 598 return -EINVAL; 599 600 WARN_ON(!list_is_singular(&pdev->dev.msi_list)); 601 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); 602 603 hwirq = rcar_msi_alloc_region(msi, nvec); 604 if (hwirq < 0) 605 return -ENOSPC; 606 607 irq = irq_find_mapping(msi->domain, hwirq); 608 if (!irq) 609 return -ENOSPC; 610 611 for (i = 0; i < nvec; i++) { 612 /* 613 * irq_create_mapping() called from rcar_pcie_probe() pre- 614 * allocates descs, so there is no need to allocate descs here. 615 * We can therefore assume that if irq_find_mapping() above 616 * returns non-zero, then the descs are also successfully 617 * allocated. 618 */ 619 if (irq_set_msi_desc_off(irq, i, desc)) { 620 /* TODO: clear */ 621 return -EINVAL; 622 } 623 } 624 625 desc->nvec_used = nvec; 626 desc->msi_attrib.multiple = order_base_2(nvec); 627 628 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 629 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 630 msg.data = hwirq; 631 632 pci_write_msi_msg(irq, &msg); 633 634 return 0; 635 } 636 637 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) 638 { 639 struct rcar_msi *msi = to_rcar_msi(chip); 640 struct irq_data *d = irq_get_irq_data(irq); 641 642 rcar_msi_free(msi, d->hwirq); 643 } 644 645 static struct irq_chip rcar_msi_irq_chip = { 646 .name = "R-Car PCIe MSI", 647 .irq_enable = pci_msi_unmask_irq, 648 .irq_disable = pci_msi_mask_irq, 649 .irq_mask = pci_msi_mask_irq, 650 .irq_unmask = pci_msi_unmask_irq, 651 }; 652 653 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, 654 irq_hw_number_t hwirq) 655 { 656 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); 657 irq_set_chip_data(irq, domain->host_data); 658 659 return 0; 660 } 661 662 static const struct irq_domain_ops msi_domain_ops = { 663 .map = rcar_msi_map, 664 }; 665 666 static void rcar_pcie_unmap_msi(struct rcar_pcie_host *host) 667 { 668 struct rcar_msi *msi = &host->msi; 669 int i, irq; 670 671 for (i = 0; i < INT_PCI_MSI_NR; i++) { 672 irq = irq_find_mapping(msi->domain, i); 673 if (irq > 0) 674 irq_dispose_mapping(irq); 675 } 676 677 irq_domain_remove(msi->domain); 678 } 679 680 static void rcar_pcie_hw_enable_msi(struct rcar_pcie_host *host) 681 { 682 struct rcar_pcie *pcie = &host->pcie; 683 struct rcar_msi *msi = &host->msi; 684 unsigned long base; 685 686 /* setup MSI data target */ 687 base = virt_to_phys((void *)msi->pages); 688 689 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR); 690 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR); 691 692 /* enable all MSI interrupts */ 693 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); 694 } 695 696 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 697 { 698 struct rcar_pcie *pcie = &host->pcie; 699 struct device *dev = pcie->dev; 700 struct rcar_msi *msi = &host->msi; 701 int err, i; 702 703 mutex_init(&msi->lock); 704 705 msi->chip.dev = dev; 706 msi->chip.setup_irq = rcar_msi_setup_irq; 707 msi->chip.setup_irqs = rcar_msi_setup_irqs; 708 msi->chip.teardown_irq = rcar_msi_teardown_irq; 709 710 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, 711 &msi_domain_ops, &msi->chip); 712 if (!msi->domain) { 713 dev_err(dev, "failed to create IRQ domain\n"); 714 return -ENOMEM; 715 } 716 717 for (i = 0; i < INT_PCI_MSI_NR; i++) 718 irq_create_mapping(msi->domain, i); 719 720 /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 721 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 722 IRQF_SHARED | IRQF_NO_THREAD, 723 rcar_msi_irq_chip.name, host); 724 if (err < 0) { 725 dev_err(dev, "failed to request IRQ: %d\n", err); 726 goto err; 727 } 728 729 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 730 IRQF_SHARED | IRQF_NO_THREAD, 731 rcar_msi_irq_chip.name, host); 732 if (err < 0) { 733 dev_err(dev, "failed to request IRQ: %d\n", err); 734 goto err; 735 } 736 737 /* setup MSI data target */ 738 msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA32, 0); 739 rcar_pcie_hw_enable_msi(host); 740 741 return 0; 742 743 err: 744 rcar_pcie_unmap_msi(host); 745 return err; 746 } 747 748 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 749 { 750 struct rcar_pcie *pcie = &host->pcie; 751 struct rcar_msi *msi = &host->msi; 752 753 /* Disable all MSI interrupts */ 754 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 755 756 /* Disable address decoding of the MSI interrupt, MSIFE */ 757 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 758 759 free_pages(msi->pages, 0); 760 761 rcar_pcie_unmap_msi(host); 762 } 763 764 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 765 { 766 struct rcar_pcie *pcie = &host->pcie; 767 struct device *dev = pcie->dev; 768 struct resource res; 769 int err, i; 770 771 host->phy = devm_phy_optional_get(dev, "pcie"); 772 if (IS_ERR(host->phy)) 773 return PTR_ERR(host->phy); 774 775 err = of_address_to_resource(dev->of_node, 0, &res); 776 if (err) 777 return err; 778 779 pcie->base = devm_ioremap_resource(dev, &res); 780 if (IS_ERR(pcie->base)) 781 return PTR_ERR(pcie->base); 782 783 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 784 if (IS_ERR(host->bus_clk)) { 785 dev_err(dev, "cannot get pcie bus clock\n"); 786 return PTR_ERR(host->bus_clk); 787 } 788 789 i = irq_of_parse_and_map(dev->of_node, 0); 790 if (!i) { 791 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 792 err = -ENOENT; 793 goto err_irq1; 794 } 795 host->msi.irq1 = i; 796 797 i = irq_of_parse_and_map(dev->of_node, 1); 798 if (!i) { 799 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 800 err = -ENOENT; 801 goto err_irq2; 802 } 803 host->msi.irq2 = i; 804 805 return 0; 806 807 err_irq2: 808 irq_dispose_mapping(host->msi.irq1); 809 err_irq1: 810 return err; 811 } 812 813 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 814 struct resource_entry *entry, 815 int *index) 816 { 817 u64 restype = entry->res->flags; 818 u64 cpu_addr = entry->res->start; 819 u64 cpu_end = entry->res->end; 820 u64 pci_addr = entry->res->start - entry->offset; 821 u32 flags = LAM_64BIT | LAR_ENABLE; 822 u64 mask; 823 u64 size = resource_size(entry->res); 824 int idx = *index; 825 826 if (restype & IORESOURCE_PREFETCH) 827 flags |= LAM_PREFETCH; 828 829 while (cpu_addr < cpu_end) { 830 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 831 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 832 return -EINVAL; 833 } 834 /* 835 * If the size of the range is larger than the alignment of 836 * the start address, we have to use multiple entries to 837 * perform the mapping. 838 */ 839 if (cpu_addr > 0) { 840 unsigned long nr_zeros = __ffs64(cpu_addr); 841 u64 alignment = 1ULL << nr_zeros; 842 843 size = min(size, alignment); 844 } 845 /* Hardware supports max 4GiB inbound region */ 846 size = min(size, 1ULL << 32); 847 848 mask = roundup_pow_of_two(size) - 1; 849 mask &= ~0xf; 850 851 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 852 lower_32_bits(mask) | flags, idx, true); 853 854 pci_addr += size; 855 cpu_addr += size; 856 idx += 2; 857 } 858 *index = idx; 859 860 return 0; 861 } 862 863 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 864 { 865 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 866 struct resource_entry *entry; 867 int index = 0, err = 0; 868 869 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 870 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 871 if (err) 872 break; 873 } 874 875 return err; 876 } 877 878 static const struct of_device_id rcar_pcie_of_match[] = { 879 { .compatible = "renesas,pcie-r8a7779", 880 .data = rcar_pcie_phy_init_h1 }, 881 { .compatible = "renesas,pcie-r8a7790", 882 .data = rcar_pcie_phy_init_gen2 }, 883 { .compatible = "renesas,pcie-r8a7791", 884 .data = rcar_pcie_phy_init_gen2 }, 885 { .compatible = "renesas,pcie-rcar-gen2", 886 .data = rcar_pcie_phy_init_gen2 }, 887 { .compatible = "renesas,pcie-r8a7795", 888 .data = rcar_pcie_phy_init_gen3 }, 889 { .compatible = "renesas,pcie-rcar-gen3", 890 .data = rcar_pcie_phy_init_gen3 }, 891 {}, 892 }; 893 894 static int rcar_pcie_probe(struct platform_device *pdev) 895 { 896 struct device *dev = &pdev->dev; 897 struct rcar_pcie_host *host; 898 struct rcar_pcie *pcie; 899 u32 data; 900 int err; 901 struct pci_host_bridge *bridge; 902 903 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 904 if (!bridge) 905 return -ENOMEM; 906 907 host = pci_host_bridge_priv(bridge); 908 pcie = &host->pcie; 909 pcie->dev = dev; 910 platform_set_drvdata(pdev, host); 911 912 pm_runtime_enable(pcie->dev); 913 err = pm_runtime_get_sync(pcie->dev); 914 if (err < 0) { 915 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 916 goto err_pm_put; 917 } 918 919 err = rcar_pcie_get_resources(host); 920 if (err < 0) { 921 dev_err(dev, "failed to request resources: %d\n", err); 922 goto err_pm_put; 923 } 924 925 err = clk_prepare_enable(host->bus_clk); 926 if (err) { 927 dev_err(dev, "failed to enable bus clock: %d\n", err); 928 goto err_unmap_msi_irqs; 929 } 930 931 err = rcar_pcie_parse_map_dma_ranges(host); 932 if (err) 933 goto err_clk_disable; 934 935 host->phy_init_fn = of_device_get_match_data(dev); 936 err = host->phy_init_fn(host); 937 if (err) { 938 dev_err(dev, "failed to init PCIe PHY\n"); 939 goto err_clk_disable; 940 } 941 942 /* Failure to get a link might just be that no cards are inserted */ 943 if (rcar_pcie_hw_init(pcie)) { 944 dev_info(dev, "PCIe link down\n"); 945 err = -ENODEV; 946 goto err_phy_shutdown; 947 } 948 949 data = rcar_pci_read_reg(pcie, MACSR); 950 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 951 952 if (IS_ENABLED(CONFIG_PCI_MSI)) { 953 err = rcar_pcie_enable_msi(host); 954 if (err < 0) { 955 dev_err(dev, 956 "failed to enable MSI support: %d\n", 957 err); 958 goto err_phy_shutdown; 959 } 960 } 961 962 err = rcar_pcie_enable(host); 963 if (err) 964 goto err_msi_teardown; 965 966 return 0; 967 968 err_msi_teardown: 969 if (IS_ENABLED(CONFIG_PCI_MSI)) 970 rcar_pcie_teardown_msi(host); 971 972 err_phy_shutdown: 973 if (host->phy) { 974 phy_power_off(host->phy); 975 phy_exit(host->phy); 976 } 977 978 err_clk_disable: 979 clk_disable_unprepare(host->bus_clk); 980 981 err_unmap_msi_irqs: 982 irq_dispose_mapping(host->msi.irq2); 983 irq_dispose_mapping(host->msi.irq1); 984 985 err_pm_put: 986 pm_runtime_put(dev); 987 pm_runtime_disable(dev); 988 989 return err; 990 } 991 992 static int __maybe_unused rcar_pcie_resume(struct device *dev) 993 { 994 struct rcar_pcie_host *host = dev_get_drvdata(dev); 995 struct rcar_pcie *pcie = &host->pcie; 996 unsigned int data; 997 int err; 998 999 err = rcar_pcie_parse_map_dma_ranges(host); 1000 if (err) 1001 return 0; 1002 1003 /* Failure to get a link might just be that no cards are inserted */ 1004 err = host->phy_init_fn(host); 1005 if (err) { 1006 dev_info(dev, "PCIe link down\n"); 1007 return 0; 1008 } 1009 1010 data = rcar_pci_read_reg(pcie, MACSR); 1011 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1012 1013 /* Enable MSI */ 1014 if (IS_ENABLED(CONFIG_PCI_MSI)) 1015 rcar_pcie_hw_enable_msi(host); 1016 1017 rcar_pcie_hw_enable(host); 1018 1019 return 0; 1020 } 1021 1022 static int rcar_pcie_resume_noirq(struct device *dev) 1023 { 1024 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1025 struct rcar_pcie *pcie = &host->pcie; 1026 1027 if (rcar_pci_read_reg(pcie, PMSR) && 1028 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1029 return 0; 1030 1031 /* Re-establish the PCIe link */ 1032 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1033 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1034 return rcar_pcie_wait_for_dl(pcie); 1035 } 1036 1037 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1038 SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1039 .resume_noirq = rcar_pcie_resume_noirq, 1040 }; 1041 1042 static struct platform_driver rcar_pcie_driver = { 1043 .driver = { 1044 .name = "rcar-pcie", 1045 .of_match_table = rcar_pcie_of_match, 1046 .pm = &rcar_pcie_pm_ops, 1047 .suppress_bind_attrs = true, 1048 }, 1049 .probe = rcar_pcie_probe, 1050 }; 1051 builtin_platform_driver(rcar_pcie_driver); 1052