1*a18f4b6eSLad Prabhakar // SPDX-License-Identifier: GPL-2.0 2*a18f4b6eSLad Prabhakar /* 3*a18f4b6eSLad Prabhakar * PCIe driver for Renesas R-Car SoCs 4*a18f4b6eSLad Prabhakar * Copyright (C) 2014 Renesas Electronics Europe Ltd 5*a18f4b6eSLad Prabhakar * 6*a18f4b6eSLad Prabhakar * Based on: 7*a18f4b6eSLad Prabhakar * arch/sh/drivers/pci/pcie-sh7786.c 8*a18f4b6eSLad Prabhakar * arch/sh/drivers/pci/ops-sh7786.c 9*a18f4b6eSLad Prabhakar * Copyright (C) 2009 - 2011 Paul Mundt 10*a18f4b6eSLad Prabhakar * 11*a18f4b6eSLad Prabhakar * Author: Phil Edworthy <phil.edworthy@renesas.com> 12*a18f4b6eSLad Prabhakar */ 13*a18f4b6eSLad Prabhakar 14*a18f4b6eSLad Prabhakar #include <linux/bitops.h> 15*a18f4b6eSLad Prabhakar #include <linux/clk.h> 16*a18f4b6eSLad Prabhakar #include <linux/delay.h> 17*a18f4b6eSLad Prabhakar #include <linux/interrupt.h> 18*a18f4b6eSLad Prabhakar #include <linux/irq.h> 19*a18f4b6eSLad Prabhakar #include <linux/irqdomain.h> 20*a18f4b6eSLad Prabhakar #include <linux/kernel.h> 21*a18f4b6eSLad Prabhakar #include <linux/init.h> 22*a18f4b6eSLad Prabhakar #include <linux/msi.h> 23*a18f4b6eSLad Prabhakar #include <linux/of_address.h> 24*a18f4b6eSLad Prabhakar #include <linux/of_irq.h> 25*a18f4b6eSLad Prabhakar #include <linux/of_pci.h> 26*a18f4b6eSLad Prabhakar #include <linux/of_platform.h> 27*a18f4b6eSLad Prabhakar #include <linux/pci.h> 28*a18f4b6eSLad Prabhakar #include <linux/phy/phy.h> 29*a18f4b6eSLad Prabhakar #include <linux/platform_device.h> 30*a18f4b6eSLad Prabhakar #include <linux/pm_runtime.h> 31*a18f4b6eSLad Prabhakar #include <linux/slab.h> 32*a18f4b6eSLad Prabhakar 33*a18f4b6eSLad Prabhakar #define PCIECAR 0x000010 34*a18f4b6eSLad Prabhakar #define PCIECCTLR 0x000018 35*a18f4b6eSLad Prabhakar #define CONFIG_SEND_ENABLE BIT(31) 36*a18f4b6eSLad Prabhakar #define TYPE0 (0 << 8) 37*a18f4b6eSLad Prabhakar #define TYPE1 BIT(8) 38*a18f4b6eSLad Prabhakar #define PCIECDR 0x000020 39*a18f4b6eSLad Prabhakar #define PCIEMSR 0x000028 40*a18f4b6eSLad Prabhakar #define PCIEINTXR 0x000400 41*a18f4b6eSLad Prabhakar #define PCIEPHYSR 0x0007f0 42*a18f4b6eSLad Prabhakar #define PHYRDY BIT(0) 43*a18f4b6eSLad Prabhakar #define PCIEMSITXR 0x000840 44*a18f4b6eSLad Prabhakar 45*a18f4b6eSLad Prabhakar /* Transfer control */ 46*a18f4b6eSLad Prabhakar #define PCIETCTLR 0x02000 47*a18f4b6eSLad Prabhakar #define DL_DOWN BIT(3) 48*a18f4b6eSLad Prabhakar #define CFINIT BIT(0) 49*a18f4b6eSLad Prabhakar #define PCIETSTR 0x02004 50*a18f4b6eSLad Prabhakar #define DATA_LINK_ACTIVE BIT(0) 51*a18f4b6eSLad Prabhakar #define PCIEERRFR 0x02020 52*a18f4b6eSLad Prabhakar #define UNSUPPORTED_REQUEST BIT(4) 53*a18f4b6eSLad Prabhakar #define PCIEMSIFR 0x02044 54*a18f4b6eSLad Prabhakar #define PCIEMSIALR 0x02048 55*a18f4b6eSLad Prabhakar #define MSIFE BIT(0) 56*a18f4b6eSLad Prabhakar #define PCIEMSIAUR 0x0204c 57*a18f4b6eSLad Prabhakar #define PCIEMSIIER 0x02050 58*a18f4b6eSLad Prabhakar 59*a18f4b6eSLad Prabhakar /* root port address */ 60*a18f4b6eSLad Prabhakar #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) 61*a18f4b6eSLad Prabhakar 62*a18f4b6eSLad Prabhakar /* local address reg & mask */ 63*a18f4b6eSLad Prabhakar #define PCIELAR(x) (0x02200 + ((x) * 0x20)) 64*a18f4b6eSLad Prabhakar #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) 65*a18f4b6eSLad Prabhakar #define LAM_PREFETCH BIT(3) 66*a18f4b6eSLad Prabhakar #define LAM_64BIT BIT(2) 67*a18f4b6eSLad Prabhakar #define LAR_ENABLE BIT(1) 68*a18f4b6eSLad Prabhakar 69*a18f4b6eSLad Prabhakar /* PCIe address reg & mask */ 70*a18f4b6eSLad Prabhakar #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) 71*a18f4b6eSLad Prabhakar #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) 72*a18f4b6eSLad Prabhakar #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) 73*a18f4b6eSLad Prabhakar #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) 74*a18f4b6eSLad Prabhakar #define PAR_ENABLE BIT(31) 75*a18f4b6eSLad Prabhakar #define IO_SPACE BIT(8) 76*a18f4b6eSLad Prabhakar 77*a18f4b6eSLad Prabhakar /* Configuration */ 78*a18f4b6eSLad Prabhakar #define PCICONF(x) (0x010000 + ((x) * 0x4)) 79*a18f4b6eSLad Prabhakar #define PMCAP(x) (0x010040 + ((x) * 0x4)) 80*a18f4b6eSLad Prabhakar #define EXPCAP(x) (0x010070 + ((x) * 0x4)) 81*a18f4b6eSLad Prabhakar #define VCCAP(x) (0x010100 + ((x) * 0x4)) 82*a18f4b6eSLad Prabhakar 83*a18f4b6eSLad Prabhakar /* link layer */ 84*a18f4b6eSLad Prabhakar #define IDSETR1 0x011004 85*a18f4b6eSLad Prabhakar #define TLCTLR 0x011048 86*a18f4b6eSLad Prabhakar #define MACSR 0x011054 87*a18f4b6eSLad Prabhakar #define SPCHGFIN BIT(4) 88*a18f4b6eSLad Prabhakar #define SPCHGFAIL BIT(6) 89*a18f4b6eSLad Prabhakar #define SPCHGSUC BIT(7) 90*a18f4b6eSLad Prabhakar #define LINK_SPEED (0xf << 16) 91*a18f4b6eSLad Prabhakar #define LINK_SPEED_2_5GTS (1 << 16) 92*a18f4b6eSLad Prabhakar #define LINK_SPEED_5_0GTS (2 << 16) 93*a18f4b6eSLad Prabhakar #define MACCTLR 0x011058 94*a18f4b6eSLad Prabhakar #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */ 95*a18f4b6eSLad Prabhakar #define SPEED_CHANGE BIT(24) 96*a18f4b6eSLad Prabhakar #define SCRAMBLE_DISABLE BIT(27) 97*a18f4b6eSLad Prabhakar #define LTSMDIS BIT(31) 98*a18f4b6eSLad Prabhakar #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK) 99*a18f4b6eSLad Prabhakar #define PMSR 0x01105c 100*a18f4b6eSLad Prabhakar #define MACS2R 0x011078 101*a18f4b6eSLad Prabhakar #define MACCGSPSETR 0x011084 102*a18f4b6eSLad Prabhakar #define SPCNGRSN BIT(31) 103*a18f4b6eSLad Prabhakar 104*a18f4b6eSLad Prabhakar /* R-Car H1 PHY */ 105*a18f4b6eSLad Prabhakar #define H1_PCIEPHYADRR 0x04000c 106*a18f4b6eSLad Prabhakar #define WRITE_CMD BIT(16) 107*a18f4b6eSLad Prabhakar #define PHY_ACK BIT(24) 108*a18f4b6eSLad Prabhakar #define RATE_POS 12 109*a18f4b6eSLad Prabhakar #define LANE_POS 8 110*a18f4b6eSLad Prabhakar #define ADR_POS 0 111*a18f4b6eSLad Prabhakar #define H1_PCIEPHYDOUTR 0x040014 112*a18f4b6eSLad Prabhakar 113*a18f4b6eSLad Prabhakar /* R-Car Gen2 PHY */ 114*a18f4b6eSLad Prabhakar #define GEN2_PCIEPHYADDR 0x780 115*a18f4b6eSLad Prabhakar #define GEN2_PCIEPHYDATA 0x784 116*a18f4b6eSLad Prabhakar #define GEN2_PCIEPHYCTRL 0x78c 117*a18f4b6eSLad Prabhakar 118*a18f4b6eSLad Prabhakar #define INT_PCI_MSI_NR 32 119*a18f4b6eSLad Prabhakar 120*a18f4b6eSLad Prabhakar #define RCONF(x) (PCICONF(0) + (x)) 121*a18f4b6eSLad Prabhakar #define RPMCAP(x) (PMCAP(0) + (x)) 122*a18f4b6eSLad Prabhakar #define REXPCAP(x) (EXPCAP(0) + (x)) 123*a18f4b6eSLad Prabhakar #define RVCCAP(x) (VCCAP(0) + (x)) 124*a18f4b6eSLad Prabhakar 125*a18f4b6eSLad Prabhakar #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) 126*a18f4b6eSLad Prabhakar #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) 127*a18f4b6eSLad Prabhakar #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) 128*a18f4b6eSLad Prabhakar 129*a18f4b6eSLad Prabhakar #define RCAR_PCI_MAX_RESOURCES 4 130*a18f4b6eSLad Prabhakar #define MAX_NR_INBOUND_MAPS 6 131*a18f4b6eSLad Prabhakar 132*a18f4b6eSLad Prabhakar struct rcar_msi { 133*a18f4b6eSLad Prabhakar DECLARE_BITMAP(used, INT_PCI_MSI_NR); 134*a18f4b6eSLad Prabhakar struct irq_domain *domain; 135*a18f4b6eSLad Prabhakar struct msi_controller chip; 136*a18f4b6eSLad Prabhakar unsigned long pages; 137*a18f4b6eSLad Prabhakar struct mutex lock; 138*a18f4b6eSLad Prabhakar int irq1; 139*a18f4b6eSLad Prabhakar int irq2; 140*a18f4b6eSLad Prabhakar }; 141*a18f4b6eSLad Prabhakar 142*a18f4b6eSLad Prabhakar static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) 143*a18f4b6eSLad Prabhakar { 144*a18f4b6eSLad Prabhakar return container_of(chip, struct rcar_msi, chip); 145*a18f4b6eSLad Prabhakar } 146*a18f4b6eSLad Prabhakar 147*a18f4b6eSLad Prabhakar /* Structure representing the PCIe interface */ 148*a18f4b6eSLad Prabhakar struct rcar_pcie { 149*a18f4b6eSLad Prabhakar struct device *dev; 150*a18f4b6eSLad Prabhakar struct phy *phy; 151*a18f4b6eSLad Prabhakar void __iomem *base; 152*a18f4b6eSLad Prabhakar struct list_head resources; 153*a18f4b6eSLad Prabhakar int root_bus_nr; 154*a18f4b6eSLad Prabhakar struct clk *bus_clk; 155*a18f4b6eSLad Prabhakar struct rcar_msi msi; 156*a18f4b6eSLad Prabhakar int (*phy_init_fn)(struct rcar_pcie *pcie); 157*a18f4b6eSLad Prabhakar }; 158*a18f4b6eSLad Prabhakar 159*a18f4b6eSLad Prabhakar static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, 160*a18f4b6eSLad Prabhakar unsigned int reg) 161*a18f4b6eSLad Prabhakar { 162*a18f4b6eSLad Prabhakar writel(val, pcie->base + reg); 163*a18f4b6eSLad Prabhakar } 164*a18f4b6eSLad Prabhakar 165*a18f4b6eSLad Prabhakar static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) 166*a18f4b6eSLad Prabhakar { 167*a18f4b6eSLad Prabhakar return readl(pcie->base + reg); 168*a18f4b6eSLad Prabhakar } 169*a18f4b6eSLad Prabhakar 170*a18f4b6eSLad Prabhakar enum { 171*a18f4b6eSLad Prabhakar RCAR_PCI_ACCESS_READ, 172*a18f4b6eSLad Prabhakar RCAR_PCI_ACCESS_WRITE, 173*a18f4b6eSLad Prabhakar }; 174*a18f4b6eSLad Prabhakar 175*a18f4b6eSLad Prabhakar static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) 176*a18f4b6eSLad Prabhakar { 177*a18f4b6eSLad Prabhakar unsigned int shift = BITS_PER_BYTE * (where & 3); 178*a18f4b6eSLad Prabhakar u32 val = rcar_pci_read_reg(pcie, where & ~3); 179*a18f4b6eSLad Prabhakar 180*a18f4b6eSLad Prabhakar val &= ~(mask << shift); 181*a18f4b6eSLad Prabhakar val |= data << shift; 182*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, val, where & ~3); 183*a18f4b6eSLad Prabhakar } 184*a18f4b6eSLad Prabhakar 185*a18f4b6eSLad Prabhakar static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 186*a18f4b6eSLad Prabhakar { 187*a18f4b6eSLad Prabhakar unsigned int shift = BITS_PER_BYTE * (where & 3); 188*a18f4b6eSLad Prabhakar u32 val = rcar_pci_read_reg(pcie, where & ~3); 189*a18f4b6eSLad Prabhakar 190*a18f4b6eSLad Prabhakar return val >> shift; 191*a18f4b6eSLad Prabhakar } 192*a18f4b6eSLad Prabhakar 193*a18f4b6eSLad Prabhakar /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 194*a18f4b6eSLad Prabhakar static int rcar_pcie_config_access(struct rcar_pcie *pcie, 195*a18f4b6eSLad Prabhakar unsigned char access_type, struct pci_bus *bus, 196*a18f4b6eSLad Prabhakar unsigned int devfn, int where, u32 *data) 197*a18f4b6eSLad Prabhakar { 198*a18f4b6eSLad Prabhakar unsigned int dev, func, reg, index; 199*a18f4b6eSLad Prabhakar 200*a18f4b6eSLad Prabhakar dev = PCI_SLOT(devfn); 201*a18f4b6eSLad Prabhakar func = PCI_FUNC(devfn); 202*a18f4b6eSLad Prabhakar reg = where & ~3; 203*a18f4b6eSLad Prabhakar index = reg / 4; 204*a18f4b6eSLad Prabhakar 205*a18f4b6eSLad Prabhakar /* 206*a18f4b6eSLad Prabhakar * While each channel has its own memory-mapped extended config 207*a18f4b6eSLad Prabhakar * space, it's generally only accessible when in endpoint mode. 208*a18f4b6eSLad Prabhakar * When in root complex mode, the controller is unable to target 209*a18f4b6eSLad Prabhakar * itself with either type 0 or type 1 accesses, and indeed, any 210*a18f4b6eSLad Prabhakar * controller initiated target transfer to its own config space 211*a18f4b6eSLad Prabhakar * result in a completer abort. 212*a18f4b6eSLad Prabhakar * 213*a18f4b6eSLad Prabhakar * Each channel effectively only supports a single device, but as 214*a18f4b6eSLad Prabhakar * the same channel <-> device access works for any PCI_SLOT() 215*a18f4b6eSLad Prabhakar * value, we cheat a bit here and bind the controller's config 216*a18f4b6eSLad Prabhakar * space to devfn 0 in order to enable self-enumeration. In this 217*a18f4b6eSLad Prabhakar * case the regular ECAR/ECDR path is sidelined and the mangled 218*a18f4b6eSLad Prabhakar * config access itself is initiated as an internal bus transaction. 219*a18f4b6eSLad Prabhakar */ 220*a18f4b6eSLad Prabhakar if (pci_is_root_bus(bus)) { 221*a18f4b6eSLad Prabhakar if (dev != 0) 222*a18f4b6eSLad Prabhakar return PCIBIOS_DEVICE_NOT_FOUND; 223*a18f4b6eSLad Prabhakar 224*a18f4b6eSLad Prabhakar if (access_type == RCAR_PCI_ACCESS_READ) { 225*a18f4b6eSLad Prabhakar *data = rcar_pci_read_reg(pcie, PCICONF(index)); 226*a18f4b6eSLad Prabhakar } else { 227*a18f4b6eSLad Prabhakar /* Keep an eye out for changes to the root bus number */ 228*a18f4b6eSLad Prabhakar if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) 229*a18f4b6eSLad Prabhakar pcie->root_bus_nr = *data & 0xff; 230*a18f4b6eSLad Prabhakar 231*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, *data, PCICONF(index)); 232*a18f4b6eSLad Prabhakar } 233*a18f4b6eSLad Prabhakar 234*a18f4b6eSLad Prabhakar return PCIBIOS_SUCCESSFUL; 235*a18f4b6eSLad Prabhakar } 236*a18f4b6eSLad Prabhakar 237*a18f4b6eSLad Prabhakar if (pcie->root_bus_nr < 0) 238*a18f4b6eSLad Prabhakar return PCIBIOS_DEVICE_NOT_FOUND; 239*a18f4b6eSLad Prabhakar 240*a18f4b6eSLad Prabhakar /* Clear errors */ 241*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 242*a18f4b6eSLad Prabhakar 243*a18f4b6eSLad Prabhakar /* Set the PIO address */ 244*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 245*a18f4b6eSLad Prabhakar PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 246*a18f4b6eSLad Prabhakar 247*a18f4b6eSLad Prabhakar /* Enable the configuration access */ 248*a18f4b6eSLad Prabhakar if (bus->parent->number == pcie->root_bus_nr) 249*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); 250*a18f4b6eSLad Prabhakar else 251*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); 252*a18f4b6eSLad Prabhakar 253*a18f4b6eSLad Prabhakar /* Check for errors */ 254*a18f4b6eSLad Prabhakar if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 255*a18f4b6eSLad Prabhakar return PCIBIOS_DEVICE_NOT_FOUND; 256*a18f4b6eSLad Prabhakar 257*a18f4b6eSLad Prabhakar /* Check for master and target aborts */ 258*a18f4b6eSLad Prabhakar if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 259*a18f4b6eSLad Prabhakar (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 260*a18f4b6eSLad Prabhakar return PCIBIOS_DEVICE_NOT_FOUND; 261*a18f4b6eSLad Prabhakar 262*a18f4b6eSLad Prabhakar if (access_type == RCAR_PCI_ACCESS_READ) 263*a18f4b6eSLad Prabhakar *data = rcar_pci_read_reg(pcie, PCIECDR); 264*a18f4b6eSLad Prabhakar else 265*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, *data, PCIECDR); 266*a18f4b6eSLad Prabhakar 267*a18f4b6eSLad Prabhakar /* Disable the configuration access */ 268*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, PCIECCTLR); 269*a18f4b6eSLad Prabhakar 270*a18f4b6eSLad Prabhakar return PCIBIOS_SUCCESSFUL; 271*a18f4b6eSLad Prabhakar } 272*a18f4b6eSLad Prabhakar 273*a18f4b6eSLad Prabhakar static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 274*a18f4b6eSLad Prabhakar int where, int size, u32 *val) 275*a18f4b6eSLad Prabhakar { 276*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = bus->sysdata; 277*a18f4b6eSLad Prabhakar int ret; 278*a18f4b6eSLad Prabhakar 279*a18f4b6eSLad Prabhakar ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, 280*a18f4b6eSLad Prabhakar bus, devfn, where, val); 281*a18f4b6eSLad Prabhakar if (ret != PCIBIOS_SUCCESSFUL) { 282*a18f4b6eSLad Prabhakar *val = 0xffffffff; 283*a18f4b6eSLad Prabhakar return ret; 284*a18f4b6eSLad Prabhakar } 285*a18f4b6eSLad Prabhakar 286*a18f4b6eSLad Prabhakar if (size == 1) 287*a18f4b6eSLad Prabhakar *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 288*a18f4b6eSLad Prabhakar else if (size == 2) 289*a18f4b6eSLad Prabhakar *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 290*a18f4b6eSLad Prabhakar 291*a18f4b6eSLad Prabhakar dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 292*a18f4b6eSLad Prabhakar bus->number, devfn, where, size, *val); 293*a18f4b6eSLad Prabhakar 294*a18f4b6eSLad Prabhakar return ret; 295*a18f4b6eSLad Prabhakar } 296*a18f4b6eSLad Prabhakar 297*a18f4b6eSLad Prabhakar /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 298*a18f4b6eSLad Prabhakar static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 299*a18f4b6eSLad Prabhakar int where, int size, u32 val) 300*a18f4b6eSLad Prabhakar { 301*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = bus->sysdata; 302*a18f4b6eSLad Prabhakar unsigned int shift; 303*a18f4b6eSLad Prabhakar u32 data; 304*a18f4b6eSLad Prabhakar int ret; 305*a18f4b6eSLad Prabhakar 306*a18f4b6eSLad Prabhakar ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, 307*a18f4b6eSLad Prabhakar bus, devfn, where, &data); 308*a18f4b6eSLad Prabhakar if (ret != PCIBIOS_SUCCESSFUL) 309*a18f4b6eSLad Prabhakar return ret; 310*a18f4b6eSLad Prabhakar 311*a18f4b6eSLad Prabhakar dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 312*a18f4b6eSLad Prabhakar bus->number, devfn, where, size, val); 313*a18f4b6eSLad Prabhakar 314*a18f4b6eSLad Prabhakar if (size == 1) { 315*a18f4b6eSLad Prabhakar shift = BITS_PER_BYTE * (where & 3); 316*a18f4b6eSLad Prabhakar data &= ~(0xff << shift); 317*a18f4b6eSLad Prabhakar data |= ((val & 0xff) << shift); 318*a18f4b6eSLad Prabhakar } else if (size == 2) { 319*a18f4b6eSLad Prabhakar shift = BITS_PER_BYTE * (where & 2); 320*a18f4b6eSLad Prabhakar data &= ~(0xffff << shift); 321*a18f4b6eSLad Prabhakar data |= ((val & 0xffff) << shift); 322*a18f4b6eSLad Prabhakar } else 323*a18f4b6eSLad Prabhakar data = val; 324*a18f4b6eSLad Prabhakar 325*a18f4b6eSLad Prabhakar ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, 326*a18f4b6eSLad Prabhakar bus, devfn, where, &data); 327*a18f4b6eSLad Prabhakar 328*a18f4b6eSLad Prabhakar return ret; 329*a18f4b6eSLad Prabhakar } 330*a18f4b6eSLad Prabhakar 331*a18f4b6eSLad Prabhakar static struct pci_ops rcar_pcie_ops = { 332*a18f4b6eSLad Prabhakar .read = rcar_pcie_read_conf, 333*a18f4b6eSLad Prabhakar .write = rcar_pcie_write_conf, 334*a18f4b6eSLad Prabhakar }; 335*a18f4b6eSLad Prabhakar 336*a18f4b6eSLad Prabhakar static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie, 337*a18f4b6eSLad Prabhakar struct resource_entry *window) 338*a18f4b6eSLad Prabhakar { 339*a18f4b6eSLad Prabhakar /* Setup PCIe address space mappings for each resource */ 340*a18f4b6eSLad Prabhakar resource_size_t size; 341*a18f4b6eSLad Prabhakar resource_size_t res_start; 342*a18f4b6eSLad Prabhakar struct resource *res = window->res; 343*a18f4b6eSLad Prabhakar u32 mask; 344*a18f4b6eSLad Prabhakar 345*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); 346*a18f4b6eSLad Prabhakar 347*a18f4b6eSLad Prabhakar /* 348*a18f4b6eSLad Prabhakar * The PAMR mask is calculated in units of 128Bytes, which 349*a18f4b6eSLad Prabhakar * keeps things pretty simple. 350*a18f4b6eSLad Prabhakar */ 351*a18f4b6eSLad Prabhakar size = resource_size(res); 352*a18f4b6eSLad Prabhakar mask = (roundup_pow_of_two(size) / SZ_128) - 1; 353*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); 354*a18f4b6eSLad Prabhakar 355*a18f4b6eSLad Prabhakar if (res->flags & IORESOURCE_IO) 356*a18f4b6eSLad Prabhakar res_start = pci_pio_to_address(res->start) - window->offset; 357*a18f4b6eSLad Prabhakar else 358*a18f4b6eSLad Prabhakar res_start = res->start - window->offset; 359*a18f4b6eSLad Prabhakar 360*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); 361*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, 362*a18f4b6eSLad Prabhakar PCIEPALR(win)); 363*a18f4b6eSLad Prabhakar 364*a18f4b6eSLad Prabhakar /* First resource is for IO */ 365*a18f4b6eSLad Prabhakar mask = PAR_ENABLE; 366*a18f4b6eSLad Prabhakar if (res->flags & IORESOURCE_IO) 367*a18f4b6eSLad Prabhakar mask |= IO_SPACE; 368*a18f4b6eSLad Prabhakar 369*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); 370*a18f4b6eSLad Prabhakar } 371*a18f4b6eSLad Prabhakar 372*a18f4b6eSLad Prabhakar static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci) 373*a18f4b6eSLad Prabhakar { 374*a18f4b6eSLad Prabhakar struct resource_entry *win; 375*a18f4b6eSLad Prabhakar int i = 0; 376*a18f4b6eSLad Prabhakar 377*a18f4b6eSLad Prabhakar /* Setup PCI resources */ 378*a18f4b6eSLad Prabhakar resource_list_for_each_entry(win, &pci->resources) { 379*a18f4b6eSLad Prabhakar struct resource *res = win->res; 380*a18f4b6eSLad Prabhakar 381*a18f4b6eSLad Prabhakar if (!res->flags) 382*a18f4b6eSLad Prabhakar continue; 383*a18f4b6eSLad Prabhakar 384*a18f4b6eSLad Prabhakar switch (resource_type(res)) { 385*a18f4b6eSLad Prabhakar case IORESOURCE_IO: 386*a18f4b6eSLad Prabhakar case IORESOURCE_MEM: 387*a18f4b6eSLad Prabhakar rcar_pcie_setup_window(i, pci, win); 388*a18f4b6eSLad Prabhakar i++; 389*a18f4b6eSLad Prabhakar break; 390*a18f4b6eSLad Prabhakar case IORESOURCE_BUS: 391*a18f4b6eSLad Prabhakar pci->root_bus_nr = res->start; 392*a18f4b6eSLad Prabhakar break; 393*a18f4b6eSLad Prabhakar default: 394*a18f4b6eSLad Prabhakar continue; 395*a18f4b6eSLad Prabhakar } 396*a18f4b6eSLad Prabhakar 397*a18f4b6eSLad Prabhakar pci_add_resource(resource, res); 398*a18f4b6eSLad Prabhakar } 399*a18f4b6eSLad Prabhakar 400*a18f4b6eSLad Prabhakar return 1; 401*a18f4b6eSLad Prabhakar } 402*a18f4b6eSLad Prabhakar 403*a18f4b6eSLad Prabhakar static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 404*a18f4b6eSLad Prabhakar { 405*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 406*a18f4b6eSLad Prabhakar unsigned int timeout = 1000; 407*a18f4b6eSLad Prabhakar u32 macsr; 408*a18f4b6eSLad Prabhakar 409*a18f4b6eSLad Prabhakar if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 410*a18f4b6eSLad Prabhakar return; 411*a18f4b6eSLad Prabhakar 412*a18f4b6eSLad Prabhakar if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 413*a18f4b6eSLad Prabhakar dev_err(dev, "Speed change already in progress\n"); 414*a18f4b6eSLad Prabhakar return; 415*a18f4b6eSLad Prabhakar } 416*a18f4b6eSLad Prabhakar 417*a18f4b6eSLad Prabhakar macsr = rcar_pci_read_reg(pcie, MACSR); 418*a18f4b6eSLad Prabhakar if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 419*a18f4b6eSLad Prabhakar goto done; 420*a18f4b6eSLad Prabhakar 421*a18f4b6eSLad Prabhakar /* Set target link speed to 5.0 GT/s */ 422*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 423*a18f4b6eSLad Prabhakar PCI_EXP_LNKSTA_CLS_5_0GB); 424*a18f4b6eSLad Prabhakar 425*a18f4b6eSLad Prabhakar /* Set speed change reason as intentional factor */ 426*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 427*a18f4b6eSLad Prabhakar 428*a18f4b6eSLad Prabhakar /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 429*a18f4b6eSLad Prabhakar if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 430*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, macsr, MACSR); 431*a18f4b6eSLad Prabhakar 432*a18f4b6eSLad Prabhakar /* Start link speed change */ 433*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 434*a18f4b6eSLad Prabhakar 435*a18f4b6eSLad Prabhakar while (timeout--) { 436*a18f4b6eSLad Prabhakar macsr = rcar_pci_read_reg(pcie, MACSR); 437*a18f4b6eSLad Prabhakar if (macsr & SPCHGFIN) { 438*a18f4b6eSLad Prabhakar /* Clear the interrupt bits */ 439*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, macsr, MACSR); 440*a18f4b6eSLad Prabhakar 441*a18f4b6eSLad Prabhakar if (macsr & SPCHGFAIL) 442*a18f4b6eSLad Prabhakar dev_err(dev, "Speed change failed\n"); 443*a18f4b6eSLad Prabhakar 444*a18f4b6eSLad Prabhakar goto done; 445*a18f4b6eSLad Prabhakar } 446*a18f4b6eSLad Prabhakar 447*a18f4b6eSLad Prabhakar msleep(1); 448*a18f4b6eSLad Prabhakar } 449*a18f4b6eSLad Prabhakar 450*a18f4b6eSLad Prabhakar dev_err(dev, "Speed change timed out\n"); 451*a18f4b6eSLad Prabhakar 452*a18f4b6eSLad Prabhakar done: 453*a18f4b6eSLad Prabhakar dev_info(dev, "Current link speed is %s GT/s\n", 454*a18f4b6eSLad Prabhakar (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 455*a18f4b6eSLad Prabhakar } 456*a18f4b6eSLad Prabhakar 457*a18f4b6eSLad Prabhakar static void rcar_pcie_hw_enable(struct rcar_pcie *pci) 458*a18f4b6eSLad Prabhakar { 459*a18f4b6eSLad Prabhakar struct resource_entry *win; 460*a18f4b6eSLad Prabhakar LIST_HEAD(res); 461*a18f4b6eSLad Prabhakar int i = 0; 462*a18f4b6eSLad Prabhakar 463*a18f4b6eSLad Prabhakar /* Try setting 5 GT/s link speed */ 464*a18f4b6eSLad Prabhakar rcar_pcie_force_speedup(pci); 465*a18f4b6eSLad Prabhakar 466*a18f4b6eSLad Prabhakar /* Setup PCI resources */ 467*a18f4b6eSLad Prabhakar resource_list_for_each_entry(win, &pci->resources) { 468*a18f4b6eSLad Prabhakar struct resource *res = win->res; 469*a18f4b6eSLad Prabhakar 470*a18f4b6eSLad Prabhakar if (!res->flags) 471*a18f4b6eSLad Prabhakar continue; 472*a18f4b6eSLad Prabhakar 473*a18f4b6eSLad Prabhakar switch (resource_type(res)) { 474*a18f4b6eSLad Prabhakar case IORESOURCE_IO: 475*a18f4b6eSLad Prabhakar case IORESOURCE_MEM: 476*a18f4b6eSLad Prabhakar rcar_pcie_setup_window(i, pci, win); 477*a18f4b6eSLad Prabhakar i++; 478*a18f4b6eSLad Prabhakar break; 479*a18f4b6eSLad Prabhakar } 480*a18f4b6eSLad Prabhakar } 481*a18f4b6eSLad Prabhakar } 482*a18f4b6eSLad Prabhakar 483*a18f4b6eSLad Prabhakar static int rcar_pcie_enable(struct rcar_pcie *pcie) 484*a18f4b6eSLad Prabhakar { 485*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 486*a18f4b6eSLad Prabhakar struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 487*a18f4b6eSLad Prabhakar struct pci_bus *bus, *child; 488*a18f4b6eSLad Prabhakar int ret; 489*a18f4b6eSLad Prabhakar 490*a18f4b6eSLad Prabhakar /* Try setting 5 GT/s link speed */ 491*a18f4b6eSLad Prabhakar rcar_pcie_force_speedup(pcie); 492*a18f4b6eSLad Prabhakar 493*a18f4b6eSLad Prabhakar rcar_pcie_setup(&bridge->windows, pcie); 494*a18f4b6eSLad Prabhakar 495*a18f4b6eSLad Prabhakar pci_add_flags(PCI_REASSIGN_ALL_BUS); 496*a18f4b6eSLad Prabhakar 497*a18f4b6eSLad Prabhakar bridge->dev.parent = dev; 498*a18f4b6eSLad Prabhakar bridge->sysdata = pcie; 499*a18f4b6eSLad Prabhakar bridge->busnr = pcie->root_bus_nr; 500*a18f4b6eSLad Prabhakar bridge->ops = &rcar_pcie_ops; 501*a18f4b6eSLad Prabhakar bridge->map_irq = of_irq_parse_and_map_pci; 502*a18f4b6eSLad Prabhakar bridge->swizzle_irq = pci_common_swizzle; 503*a18f4b6eSLad Prabhakar if (IS_ENABLED(CONFIG_PCI_MSI)) 504*a18f4b6eSLad Prabhakar bridge->msi = &pcie->msi.chip; 505*a18f4b6eSLad Prabhakar 506*a18f4b6eSLad Prabhakar ret = pci_scan_root_bus_bridge(bridge); 507*a18f4b6eSLad Prabhakar if (ret < 0) 508*a18f4b6eSLad Prabhakar return ret; 509*a18f4b6eSLad Prabhakar 510*a18f4b6eSLad Prabhakar bus = bridge->bus; 511*a18f4b6eSLad Prabhakar 512*a18f4b6eSLad Prabhakar pci_bus_size_bridges(bus); 513*a18f4b6eSLad Prabhakar pci_bus_assign_resources(bus); 514*a18f4b6eSLad Prabhakar 515*a18f4b6eSLad Prabhakar list_for_each_entry(child, &bus->children, node) 516*a18f4b6eSLad Prabhakar pcie_bus_configure_settings(child); 517*a18f4b6eSLad Prabhakar 518*a18f4b6eSLad Prabhakar pci_bus_add_devices(bus); 519*a18f4b6eSLad Prabhakar 520*a18f4b6eSLad Prabhakar return 0; 521*a18f4b6eSLad Prabhakar } 522*a18f4b6eSLad Prabhakar 523*a18f4b6eSLad Prabhakar static int phy_wait_for_ack(struct rcar_pcie *pcie) 524*a18f4b6eSLad Prabhakar { 525*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 526*a18f4b6eSLad Prabhakar unsigned int timeout = 100; 527*a18f4b6eSLad Prabhakar 528*a18f4b6eSLad Prabhakar while (timeout--) { 529*a18f4b6eSLad Prabhakar if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 530*a18f4b6eSLad Prabhakar return 0; 531*a18f4b6eSLad Prabhakar 532*a18f4b6eSLad Prabhakar udelay(100); 533*a18f4b6eSLad Prabhakar } 534*a18f4b6eSLad Prabhakar 535*a18f4b6eSLad Prabhakar dev_err(dev, "Access to PCIe phy timed out\n"); 536*a18f4b6eSLad Prabhakar 537*a18f4b6eSLad Prabhakar return -ETIMEDOUT; 538*a18f4b6eSLad Prabhakar } 539*a18f4b6eSLad Prabhakar 540*a18f4b6eSLad Prabhakar static void phy_write_reg(struct rcar_pcie *pcie, 541*a18f4b6eSLad Prabhakar unsigned int rate, u32 addr, 542*a18f4b6eSLad Prabhakar unsigned int lane, u32 data) 543*a18f4b6eSLad Prabhakar { 544*a18f4b6eSLad Prabhakar u32 phyaddr; 545*a18f4b6eSLad Prabhakar 546*a18f4b6eSLad Prabhakar phyaddr = WRITE_CMD | 547*a18f4b6eSLad Prabhakar ((rate & 1) << RATE_POS) | 548*a18f4b6eSLad Prabhakar ((lane & 0xf) << LANE_POS) | 549*a18f4b6eSLad Prabhakar ((addr & 0xff) << ADR_POS); 550*a18f4b6eSLad Prabhakar 551*a18f4b6eSLad Prabhakar /* Set write data */ 552*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 553*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 554*a18f4b6eSLad Prabhakar 555*a18f4b6eSLad Prabhakar /* Ignore errors as they will be dealt with if the data link is down */ 556*a18f4b6eSLad Prabhakar phy_wait_for_ack(pcie); 557*a18f4b6eSLad Prabhakar 558*a18f4b6eSLad Prabhakar /* Clear command */ 559*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 560*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 561*a18f4b6eSLad Prabhakar 562*a18f4b6eSLad Prabhakar /* Ignore errors as they will be dealt with if the data link is down */ 563*a18f4b6eSLad Prabhakar phy_wait_for_ack(pcie); 564*a18f4b6eSLad Prabhakar } 565*a18f4b6eSLad Prabhakar 566*a18f4b6eSLad Prabhakar static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) 567*a18f4b6eSLad Prabhakar { 568*a18f4b6eSLad Prabhakar unsigned int timeout = 10; 569*a18f4b6eSLad Prabhakar 570*a18f4b6eSLad Prabhakar while (timeout--) { 571*a18f4b6eSLad Prabhakar if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY) 572*a18f4b6eSLad Prabhakar return 0; 573*a18f4b6eSLad Prabhakar 574*a18f4b6eSLad Prabhakar msleep(5); 575*a18f4b6eSLad Prabhakar } 576*a18f4b6eSLad Prabhakar 577*a18f4b6eSLad Prabhakar return -ETIMEDOUT; 578*a18f4b6eSLad Prabhakar } 579*a18f4b6eSLad Prabhakar 580*a18f4b6eSLad Prabhakar static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) 581*a18f4b6eSLad Prabhakar { 582*a18f4b6eSLad Prabhakar unsigned int timeout = 10000; 583*a18f4b6eSLad Prabhakar 584*a18f4b6eSLad Prabhakar while (timeout--) { 585*a18f4b6eSLad Prabhakar if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE)) 586*a18f4b6eSLad Prabhakar return 0; 587*a18f4b6eSLad Prabhakar 588*a18f4b6eSLad Prabhakar udelay(5); 589*a18f4b6eSLad Prabhakar cpu_relax(); 590*a18f4b6eSLad Prabhakar } 591*a18f4b6eSLad Prabhakar 592*a18f4b6eSLad Prabhakar return -ETIMEDOUT; 593*a18f4b6eSLad Prabhakar } 594*a18f4b6eSLad Prabhakar 595*a18f4b6eSLad Prabhakar static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 596*a18f4b6eSLad Prabhakar { 597*a18f4b6eSLad Prabhakar int err; 598*a18f4b6eSLad Prabhakar 599*a18f4b6eSLad Prabhakar /* Begin initialization */ 600*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, PCIETCTLR); 601*a18f4b6eSLad Prabhakar 602*a18f4b6eSLad Prabhakar /* Set mode */ 603*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 1, PCIEMSR); 604*a18f4b6eSLad Prabhakar 605*a18f4b6eSLad Prabhakar err = rcar_pcie_wait_for_phyrdy(pcie); 606*a18f4b6eSLad Prabhakar if (err) 607*a18f4b6eSLad Prabhakar return err; 608*a18f4b6eSLad Prabhakar 609*a18f4b6eSLad Prabhakar /* 610*a18f4b6eSLad Prabhakar * Initial header for port config space is type 1, set the device 611*a18f4b6eSLad Prabhakar * class to match. Hardware takes care of propagating the IDSETR 612*a18f4b6eSLad Prabhakar * settings, so there is no need to bother with a quirk. 613*a18f4b6eSLad Prabhakar */ 614*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); 615*a18f4b6eSLad Prabhakar 616*a18f4b6eSLad Prabhakar /* 617*a18f4b6eSLad Prabhakar * Setup Secondary Bus Number & Subordinate Bus Number, even though 618*a18f4b6eSLad Prabhakar * they aren't used, to avoid bridge being detected as broken. 619*a18f4b6eSLad Prabhakar */ 620*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 621*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 622*a18f4b6eSLad Prabhakar 623*a18f4b6eSLad Prabhakar /* Initialize default capabilities. */ 624*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 625*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 626*a18f4b6eSLad Prabhakar PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 627*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 628*a18f4b6eSLad Prabhakar PCI_HEADER_TYPE_BRIDGE); 629*a18f4b6eSLad Prabhakar 630*a18f4b6eSLad Prabhakar /* Enable data link layer active state reporting */ 631*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 632*a18f4b6eSLad Prabhakar PCI_EXP_LNKCAP_DLLLARC); 633*a18f4b6eSLad Prabhakar 634*a18f4b6eSLad Prabhakar /* Write out the physical slot number = 0 */ 635*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 636*a18f4b6eSLad Prabhakar 637*a18f4b6eSLad Prabhakar /* Set the completion timer timeout to the maximum 50ms. */ 638*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 639*a18f4b6eSLad Prabhakar 640*a18f4b6eSLad Prabhakar /* Terminate list of capabilities (Next Capability Offset=0) */ 641*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 642*a18f4b6eSLad Prabhakar 643*a18f4b6eSLad Prabhakar /* Enable MSI */ 644*a18f4b6eSLad Prabhakar if (IS_ENABLED(CONFIG_PCI_MSI)) 645*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 646*a18f4b6eSLad Prabhakar 647*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 648*a18f4b6eSLad Prabhakar 649*a18f4b6eSLad Prabhakar /* Finish initialization - establish a PCI Express link */ 650*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 651*a18f4b6eSLad Prabhakar 652*a18f4b6eSLad Prabhakar /* This will timeout if we don't have a link. */ 653*a18f4b6eSLad Prabhakar err = rcar_pcie_wait_for_dl(pcie); 654*a18f4b6eSLad Prabhakar if (err) 655*a18f4b6eSLad Prabhakar return err; 656*a18f4b6eSLad Prabhakar 657*a18f4b6eSLad Prabhakar /* Enable INTx interrupts */ 658*a18f4b6eSLad Prabhakar rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 659*a18f4b6eSLad Prabhakar 660*a18f4b6eSLad Prabhakar wmb(); 661*a18f4b6eSLad Prabhakar 662*a18f4b6eSLad Prabhakar return 0; 663*a18f4b6eSLad Prabhakar } 664*a18f4b6eSLad Prabhakar 665*a18f4b6eSLad Prabhakar static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie) 666*a18f4b6eSLad Prabhakar { 667*a18f4b6eSLad Prabhakar /* Initialize the phy */ 668*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 669*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 670*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 671*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 672*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 673*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 674*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 675*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 676*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 677*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 678*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 679*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 680*a18f4b6eSLad Prabhakar 681*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 682*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 683*a18f4b6eSLad Prabhakar phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 684*a18f4b6eSLad Prabhakar 685*a18f4b6eSLad Prabhakar return 0; 686*a18f4b6eSLad Prabhakar } 687*a18f4b6eSLad Prabhakar 688*a18f4b6eSLad Prabhakar static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie) 689*a18f4b6eSLad Prabhakar { 690*a18f4b6eSLad Prabhakar /* 691*a18f4b6eSLad Prabhakar * These settings come from the R-Car Series, 2nd Generation User's 692*a18f4b6eSLad Prabhakar * Manual, section 50.3.1 (2) Initialization of the physical layer. 693*a18f4b6eSLad Prabhakar */ 694*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 695*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 696*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 697*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 698*a18f4b6eSLad Prabhakar 699*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 700*a18f4b6eSLad Prabhakar /* The following value is for DC connection, no termination resistor */ 701*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 702*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 703*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 704*a18f4b6eSLad Prabhakar 705*a18f4b6eSLad Prabhakar return 0; 706*a18f4b6eSLad Prabhakar } 707*a18f4b6eSLad Prabhakar 708*a18f4b6eSLad Prabhakar static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie) 709*a18f4b6eSLad Prabhakar { 710*a18f4b6eSLad Prabhakar int err; 711*a18f4b6eSLad Prabhakar 712*a18f4b6eSLad Prabhakar err = phy_init(pcie->phy); 713*a18f4b6eSLad Prabhakar if (err) 714*a18f4b6eSLad Prabhakar return err; 715*a18f4b6eSLad Prabhakar 716*a18f4b6eSLad Prabhakar err = phy_power_on(pcie->phy); 717*a18f4b6eSLad Prabhakar if (err) 718*a18f4b6eSLad Prabhakar phy_exit(pcie->phy); 719*a18f4b6eSLad Prabhakar 720*a18f4b6eSLad Prabhakar return err; 721*a18f4b6eSLad Prabhakar } 722*a18f4b6eSLad Prabhakar 723*a18f4b6eSLad Prabhakar static int rcar_msi_alloc(struct rcar_msi *chip) 724*a18f4b6eSLad Prabhakar { 725*a18f4b6eSLad Prabhakar int msi; 726*a18f4b6eSLad Prabhakar 727*a18f4b6eSLad Prabhakar mutex_lock(&chip->lock); 728*a18f4b6eSLad Prabhakar 729*a18f4b6eSLad Prabhakar msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); 730*a18f4b6eSLad Prabhakar if (msi < INT_PCI_MSI_NR) 731*a18f4b6eSLad Prabhakar set_bit(msi, chip->used); 732*a18f4b6eSLad Prabhakar else 733*a18f4b6eSLad Prabhakar msi = -ENOSPC; 734*a18f4b6eSLad Prabhakar 735*a18f4b6eSLad Prabhakar mutex_unlock(&chip->lock); 736*a18f4b6eSLad Prabhakar 737*a18f4b6eSLad Prabhakar return msi; 738*a18f4b6eSLad Prabhakar } 739*a18f4b6eSLad Prabhakar 740*a18f4b6eSLad Prabhakar static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) 741*a18f4b6eSLad Prabhakar { 742*a18f4b6eSLad Prabhakar int msi; 743*a18f4b6eSLad Prabhakar 744*a18f4b6eSLad Prabhakar mutex_lock(&chip->lock); 745*a18f4b6eSLad Prabhakar msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, 746*a18f4b6eSLad Prabhakar order_base_2(no_irqs)); 747*a18f4b6eSLad Prabhakar mutex_unlock(&chip->lock); 748*a18f4b6eSLad Prabhakar 749*a18f4b6eSLad Prabhakar return msi; 750*a18f4b6eSLad Prabhakar } 751*a18f4b6eSLad Prabhakar 752*a18f4b6eSLad Prabhakar static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) 753*a18f4b6eSLad Prabhakar { 754*a18f4b6eSLad Prabhakar mutex_lock(&chip->lock); 755*a18f4b6eSLad Prabhakar clear_bit(irq, chip->used); 756*a18f4b6eSLad Prabhakar mutex_unlock(&chip->lock); 757*a18f4b6eSLad Prabhakar } 758*a18f4b6eSLad Prabhakar 759*a18f4b6eSLad Prabhakar static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 760*a18f4b6eSLad Prabhakar { 761*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = data; 762*a18f4b6eSLad Prabhakar struct rcar_msi *msi = &pcie->msi; 763*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 764*a18f4b6eSLad Prabhakar unsigned long reg; 765*a18f4b6eSLad Prabhakar 766*a18f4b6eSLad Prabhakar reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 767*a18f4b6eSLad Prabhakar 768*a18f4b6eSLad Prabhakar /* MSI & INTx share an interrupt - we only handle MSI here */ 769*a18f4b6eSLad Prabhakar if (!reg) 770*a18f4b6eSLad Prabhakar return IRQ_NONE; 771*a18f4b6eSLad Prabhakar 772*a18f4b6eSLad Prabhakar while (reg) { 773*a18f4b6eSLad Prabhakar unsigned int index = find_first_bit(®, 32); 774*a18f4b6eSLad Prabhakar unsigned int msi_irq; 775*a18f4b6eSLad Prabhakar 776*a18f4b6eSLad Prabhakar /* clear the interrupt */ 777*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); 778*a18f4b6eSLad Prabhakar 779*a18f4b6eSLad Prabhakar msi_irq = irq_find_mapping(msi->domain, index); 780*a18f4b6eSLad Prabhakar if (msi_irq) { 781*a18f4b6eSLad Prabhakar if (test_bit(index, msi->used)) 782*a18f4b6eSLad Prabhakar generic_handle_irq(msi_irq); 783*a18f4b6eSLad Prabhakar else 784*a18f4b6eSLad Prabhakar dev_info(dev, "unhandled MSI\n"); 785*a18f4b6eSLad Prabhakar } else { 786*a18f4b6eSLad Prabhakar /* Unknown MSI, just clear it */ 787*a18f4b6eSLad Prabhakar dev_dbg(dev, "unexpected MSI\n"); 788*a18f4b6eSLad Prabhakar } 789*a18f4b6eSLad Prabhakar 790*a18f4b6eSLad Prabhakar /* see if there's any more pending in this vector */ 791*a18f4b6eSLad Prabhakar reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 792*a18f4b6eSLad Prabhakar } 793*a18f4b6eSLad Prabhakar 794*a18f4b6eSLad Prabhakar return IRQ_HANDLED; 795*a18f4b6eSLad Prabhakar } 796*a18f4b6eSLad Prabhakar 797*a18f4b6eSLad Prabhakar static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, 798*a18f4b6eSLad Prabhakar struct msi_desc *desc) 799*a18f4b6eSLad Prabhakar { 800*a18f4b6eSLad Prabhakar struct rcar_msi *msi = to_rcar_msi(chip); 801*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); 802*a18f4b6eSLad Prabhakar struct msi_msg msg; 803*a18f4b6eSLad Prabhakar unsigned int irq; 804*a18f4b6eSLad Prabhakar int hwirq; 805*a18f4b6eSLad Prabhakar 806*a18f4b6eSLad Prabhakar hwirq = rcar_msi_alloc(msi); 807*a18f4b6eSLad Prabhakar if (hwirq < 0) 808*a18f4b6eSLad Prabhakar return hwirq; 809*a18f4b6eSLad Prabhakar 810*a18f4b6eSLad Prabhakar irq = irq_find_mapping(msi->domain, hwirq); 811*a18f4b6eSLad Prabhakar if (!irq) { 812*a18f4b6eSLad Prabhakar rcar_msi_free(msi, hwirq); 813*a18f4b6eSLad Prabhakar return -EINVAL; 814*a18f4b6eSLad Prabhakar } 815*a18f4b6eSLad Prabhakar 816*a18f4b6eSLad Prabhakar irq_set_msi_desc(irq, desc); 817*a18f4b6eSLad Prabhakar 818*a18f4b6eSLad Prabhakar msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 819*a18f4b6eSLad Prabhakar msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 820*a18f4b6eSLad Prabhakar msg.data = hwirq; 821*a18f4b6eSLad Prabhakar 822*a18f4b6eSLad Prabhakar pci_write_msi_msg(irq, &msg); 823*a18f4b6eSLad Prabhakar 824*a18f4b6eSLad Prabhakar return 0; 825*a18f4b6eSLad Prabhakar } 826*a18f4b6eSLad Prabhakar 827*a18f4b6eSLad Prabhakar static int rcar_msi_setup_irqs(struct msi_controller *chip, 828*a18f4b6eSLad Prabhakar struct pci_dev *pdev, int nvec, int type) 829*a18f4b6eSLad Prabhakar { 830*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); 831*a18f4b6eSLad Prabhakar struct rcar_msi *msi = to_rcar_msi(chip); 832*a18f4b6eSLad Prabhakar struct msi_desc *desc; 833*a18f4b6eSLad Prabhakar struct msi_msg msg; 834*a18f4b6eSLad Prabhakar unsigned int irq; 835*a18f4b6eSLad Prabhakar int hwirq; 836*a18f4b6eSLad Prabhakar int i; 837*a18f4b6eSLad Prabhakar 838*a18f4b6eSLad Prabhakar /* MSI-X interrupts are not supported */ 839*a18f4b6eSLad Prabhakar if (type == PCI_CAP_ID_MSIX) 840*a18f4b6eSLad Prabhakar return -EINVAL; 841*a18f4b6eSLad Prabhakar 842*a18f4b6eSLad Prabhakar WARN_ON(!list_is_singular(&pdev->dev.msi_list)); 843*a18f4b6eSLad Prabhakar desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); 844*a18f4b6eSLad Prabhakar 845*a18f4b6eSLad Prabhakar hwirq = rcar_msi_alloc_region(msi, nvec); 846*a18f4b6eSLad Prabhakar if (hwirq < 0) 847*a18f4b6eSLad Prabhakar return -ENOSPC; 848*a18f4b6eSLad Prabhakar 849*a18f4b6eSLad Prabhakar irq = irq_find_mapping(msi->domain, hwirq); 850*a18f4b6eSLad Prabhakar if (!irq) 851*a18f4b6eSLad Prabhakar return -ENOSPC; 852*a18f4b6eSLad Prabhakar 853*a18f4b6eSLad Prabhakar for (i = 0; i < nvec; i++) { 854*a18f4b6eSLad Prabhakar /* 855*a18f4b6eSLad Prabhakar * irq_create_mapping() called from rcar_pcie_probe() pre- 856*a18f4b6eSLad Prabhakar * allocates descs, so there is no need to allocate descs here. 857*a18f4b6eSLad Prabhakar * We can therefore assume that if irq_find_mapping() above 858*a18f4b6eSLad Prabhakar * returns non-zero, then the descs are also successfully 859*a18f4b6eSLad Prabhakar * allocated. 860*a18f4b6eSLad Prabhakar */ 861*a18f4b6eSLad Prabhakar if (irq_set_msi_desc_off(irq, i, desc)) { 862*a18f4b6eSLad Prabhakar /* TODO: clear */ 863*a18f4b6eSLad Prabhakar return -EINVAL; 864*a18f4b6eSLad Prabhakar } 865*a18f4b6eSLad Prabhakar } 866*a18f4b6eSLad Prabhakar 867*a18f4b6eSLad Prabhakar desc->nvec_used = nvec; 868*a18f4b6eSLad Prabhakar desc->msi_attrib.multiple = order_base_2(nvec); 869*a18f4b6eSLad Prabhakar 870*a18f4b6eSLad Prabhakar msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 871*a18f4b6eSLad Prabhakar msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 872*a18f4b6eSLad Prabhakar msg.data = hwirq; 873*a18f4b6eSLad Prabhakar 874*a18f4b6eSLad Prabhakar pci_write_msi_msg(irq, &msg); 875*a18f4b6eSLad Prabhakar 876*a18f4b6eSLad Prabhakar return 0; 877*a18f4b6eSLad Prabhakar } 878*a18f4b6eSLad Prabhakar 879*a18f4b6eSLad Prabhakar static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) 880*a18f4b6eSLad Prabhakar { 881*a18f4b6eSLad Prabhakar struct rcar_msi *msi = to_rcar_msi(chip); 882*a18f4b6eSLad Prabhakar struct irq_data *d = irq_get_irq_data(irq); 883*a18f4b6eSLad Prabhakar 884*a18f4b6eSLad Prabhakar rcar_msi_free(msi, d->hwirq); 885*a18f4b6eSLad Prabhakar } 886*a18f4b6eSLad Prabhakar 887*a18f4b6eSLad Prabhakar static struct irq_chip rcar_msi_irq_chip = { 888*a18f4b6eSLad Prabhakar .name = "R-Car PCIe MSI", 889*a18f4b6eSLad Prabhakar .irq_enable = pci_msi_unmask_irq, 890*a18f4b6eSLad Prabhakar .irq_disable = pci_msi_mask_irq, 891*a18f4b6eSLad Prabhakar .irq_mask = pci_msi_mask_irq, 892*a18f4b6eSLad Prabhakar .irq_unmask = pci_msi_unmask_irq, 893*a18f4b6eSLad Prabhakar }; 894*a18f4b6eSLad Prabhakar 895*a18f4b6eSLad Prabhakar static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, 896*a18f4b6eSLad Prabhakar irq_hw_number_t hwirq) 897*a18f4b6eSLad Prabhakar { 898*a18f4b6eSLad Prabhakar irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); 899*a18f4b6eSLad Prabhakar irq_set_chip_data(irq, domain->host_data); 900*a18f4b6eSLad Prabhakar 901*a18f4b6eSLad Prabhakar return 0; 902*a18f4b6eSLad Prabhakar } 903*a18f4b6eSLad Prabhakar 904*a18f4b6eSLad Prabhakar static const struct irq_domain_ops msi_domain_ops = { 905*a18f4b6eSLad Prabhakar .map = rcar_msi_map, 906*a18f4b6eSLad Prabhakar }; 907*a18f4b6eSLad Prabhakar 908*a18f4b6eSLad Prabhakar static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie) 909*a18f4b6eSLad Prabhakar { 910*a18f4b6eSLad Prabhakar struct rcar_msi *msi = &pcie->msi; 911*a18f4b6eSLad Prabhakar int i, irq; 912*a18f4b6eSLad Prabhakar 913*a18f4b6eSLad Prabhakar for (i = 0; i < INT_PCI_MSI_NR; i++) { 914*a18f4b6eSLad Prabhakar irq = irq_find_mapping(msi->domain, i); 915*a18f4b6eSLad Prabhakar if (irq > 0) 916*a18f4b6eSLad Prabhakar irq_dispose_mapping(irq); 917*a18f4b6eSLad Prabhakar } 918*a18f4b6eSLad Prabhakar 919*a18f4b6eSLad Prabhakar irq_domain_remove(msi->domain); 920*a18f4b6eSLad Prabhakar } 921*a18f4b6eSLad Prabhakar 922*a18f4b6eSLad Prabhakar static void rcar_pcie_hw_enable_msi(struct rcar_pcie *pcie) 923*a18f4b6eSLad Prabhakar { 924*a18f4b6eSLad Prabhakar struct rcar_msi *msi = &pcie->msi; 925*a18f4b6eSLad Prabhakar unsigned long base; 926*a18f4b6eSLad Prabhakar 927*a18f4b6eSLad Prabhakar /* setup MSI data target */ 928*a18f4b6eSLad Prabhakar base = virt_to_phys((void *)msi->pages); 929*a18f4b6eSLad Prabhakar 930*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR); 931*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR); 932*a18f4b6eSLad Prabhakar 933*a18f4b6eSLad Prabhakar /* enable all MSI interrupts */ 934*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); 935*a18f4b6eSLad Prabhakar } 936*a18f4b6eSLad Prabhakar 937*a18f4b6eSLad Prabhakar static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) 938*a18f4b6eSLad Prabhakar { 939*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 940*a18f4b6eSLad Prabhakar struct rcar_msi *msi = &pcie->msi; 941*a18f4b6eSLad Prabhakar int err, i; 942*a18f4b6eSLad Prabhakar 943*a18f4b6eSLad Prabhakar mutex_init(&msi->lock); 944*a18f4b6eSLad Prabhakar 945*a18f4b6eSLad Prabhakar msi->chip.dev = dev; 946*a18f4b6eSLad Prabhakar msi->chip.setup_irq = rcar_msi_setup_irq; 947*a18f4b6eSLad Prabhakar msi->chip.setup_irqs = rcar_msi_setup_irqs; 948*a18f4b6eSLad Prabhakar msi->chip.teardown_irq = rcar_msi_teardown_irq; 949*a18f4b6eSLad Prabhakar 950*a18f4b6eSLad Prabhakar msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, 951*a18f4b6eSLad Prabhakar &msi_domain_ops, &msi->chip); 952*a18f4b6eSLad Prabhakar if (!msi->domain) { 953*a18f4b6eSLad Prabhakar dev_err(dev, "failed to create IRQ domain\n"); 954*a18f4b6eSLad Prabhakar return -ENOMEM; 955*a18f4b6eSLad Prabhakar } 956*a18f4b6eSLad Prabhakar 957*a18f4b6eSLad Prabhakar for (i = 0; i < INT_PCI_MSI_NR; i++) 958*a18f4b6eSLad Prabhakar irq_create_mapping(msi->domain, i); 959*a18f4b6eSLad Prabhakar 960*a18f4b6eSLad Prabhakar /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 961*a18f4b6eSLad Prabhakar err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 962*a18f4b6eSLad Prabhakar IRQF_SHARED | IRQF_NO_THREAD, 963*a18f4b6eSLad Prabhakar rcar_msi_irq_chip.name, pcie); 964*a18f4b6eSLad Prabhakar if (err < 0) { 965*a18f4b6eSLad Prabhakar dev_err(dev, "failed to request IRQ: %d\n", err); 966*a18f4b6eSLad Prabhakar goto err; 967*a18f4b6eSLad Prabhakar } 968*a18f4b6eSLad Prabhakar 969*a18f4b6eSLad Prabhakar err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 970*a18f4b6eSLad Prabhakar IRQF_SHARED | IRQF_NO_THREAD, 971*a18f4b6eSLad Prabhakar rcar_msi_irq_chip.name, pcie); 972*a18f4b6eSLad Prabhakar if (err < 0) { 973*a18f4b6eSLad Prabhakar dev_err(dev, "failed to request IRQ: %d\n", err); 974*a18f4b6eSLad Prabhakar goto err; 975*a18f4b6eSLad Prabhakar } 976*a18f4b6eSLad Prabhakar 977*a18f4b6eSLad Prabhakar /* setup MSI data target */ 978*a18f4b6eSLad Prabhakar msi->pages = __get_free_pages(GFP_KERNEL, 0); 979*a18f4b6eSLad Prabhakar rcar_pcie_hw_enable_msi(pcie); 980*a18f4b6eSLad Prabhakar 981*a18f4b6eSLad Prabhakar return 0; 982*a18f4b6eSLad Prabhakar 983*a18f4b6eSLad Prabhakar err: 984*a18f4b6eSLad Prabhakar rcar_pcie_unmap_msi(pcie); 985*a18f4b6eSLad Prabhakar return err; 986*a18f4b6eSLad Prabhakar } 987*a18f4b6eSLad Prabhakar 988*a18f4b6eSLad Prabhakar static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie) 989*a18f4b6eSLad Prabhakar { 990*a18f4b6eSLad Prabhakar struct rcar_msi *msi = &pcie->msi; 991*a18f4b6eSLad Prabhakar 992*a18f4b6eSLad Prabhakar /* Disable all MSI interrupts */ 993*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 994*a18f4b6eSLad Prabhakar 995*a18f4b6eSLad Prabhakar /* Disable address decoding of the MSI interrupt, MSIFE */ 996*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 997*a18f4b6eSLad Prabhakar 998*a18f4b6eSLad Prabhakar free_pages(msi->pages, 0); 999*a18f4b6eSLad Prabhakar 1000*a18f4b6eSLad Prabhakar rcar_pcie_unmap_msi(pcie); 1001*a18f4b6eSLad Prabhakar } 1002*a18f4b6eSLad Prabhakar 1003*a18f4b6eSLad Prabhakar static int rcar_pcie_get_resources(struct rcar_pcie *pcie) 1004*a18f4b6eSLad Prabhakar { 1005*a18f4b6eSLad Prabhakar struct device *dev = pcie->dev; 1006*a18f4b6eSLad Prabhakar struct resource res; 1007*a18f4b6eSLad Prabhakar int err, i; 1008*a18f4b6eSLad Prabhakar 1009*a18f4b6eSLad Prabhakar pcie->phy = devm_phy_optional_get(dev, "pcie"); 1010*a18f4b6eSLad Prabhakar if (IS_ERR(pcie->phy)) 1011*a18f4b6eSLad Prabhakar return PTR_ERR(pcie->phy); 1012*a18f4b6eSLad Prabhakar 1013*a18f4b6eSLad Prabhakar err = of_address_to_resource(dev->of_node, 0, &res); 1014*a18f4b6eSLad Prabhakar if (err) 1015*a18f4b6eSLad Prabhakar return err; 1016*a18f4b6eSLad Prabhakar 1017*a18f4b6eSLad Prabhakar pcie->base = devm_ioremap_resource(dev, &res); 1018*a18f4b6eSLad Prabhakar if (IS_ERR(pcie->base)) 1019*a18f4b6eSLad Prabhakar return PTR_ERR(pcie->base); 1020*a18f4b6eSLad Prabhakar 1021*a18f4b6eSLad Prabhakar pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); 1022*a18f4b6eSLad Prabhakar if (IS_ERR(pcie->bus_clk)) { 1023*a18f4b6eSLad Prabhakar dev_err(dev, "cannot get pcie bus clock\n"); 1024*a18f4b6eSLad Prabhakar return PTR_ERR(pcie->bus_clk); 1025*a18f4b6eSLad Prabhakar } 1026*a18f4b6eSLad Prabhakar 1027*a18f4b6eSLad Prabhakar i = irq_of_parse_and_map(dev->of_node, 0); 1028*a18f4b6eSLad Prabhakar if (!i) { 1029*a18f4b6eSLad Prabhakar dev_err(dev, "cannot get platform resources for msi interrupt\n"); 1030*a18f4b6eSLad Prabhakar err = -ENOENT; 1031*a18f4b6eSLad Prabhakar goto err_irq1; 1032*a18f4b6eSLad Prabhakar } 1033*a18f4b6eSLad Prabhakar pcie->msi.irq1 = i; 1034*a18f4b6eSLad Prabhakar 1035*a18f4b6eSLad Prabhakar i = irq_of_parse_and_map(dev->of_node, 1); 1036*a18f4b6eSLad Prabhakar if (!i) { 1037*a18f4b6eSLad Prabhakar dev_err(dev, "cannot get platform resources for msi interrupt\n"); 1038*a18f4b6eSLad Prabhakar err = -ENOENT; 1039*a18f4b6eSLad Prabhakar goto err_irq2; 1040*a18f4b6eSLad Prabhakar } 1041*a18f4b6eSLad Prabhakar pcie->msi.irq2 = i; 1042*a18f4b6eSLad Prabhakar 1043*a18f4b6eSLad Prabhakar return 0; 1044*a18f4b6eSLad Prabhakar 1045*a18f4b6eSLad Prabhakar err_irq2: 1046*a18f4b6eSLad Prabhakar irq_dispose_mapping(pcie->msi.irq1); 1047*a18f4b6eSLad Prabhakar err_irq1: 1048*a18f4b6eSLad Prabhakar return err; 1049*a18f4b6eSLad Prabhakar } 1050*a18f4b6eSLad Prabhakar 1051*a18f4b6eSLad Prabhakar static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 1052*a18f4b6eSLad Prabhakar struct resource_entry *entry, 1053*a18f4b6eSLad Prabhakar int *index) 1054*a18f4b6eSLad Prabhakar { 1055*a18f4b6eSLad Prabhakar u64 restype = entry->res->flags; 1056*a18f4b6eSLad Prabhakar u64 cpu_addr = entry->res->start; 1057*a18f4b6eSLad Prabhakar u64 cpu_end = entry->res->end; 1058*a18f4b6eSLad Prabhakar u64 pci_addr = entry->res->start - entry->offset; 1059*a18f4b6eSLad Prabhakar u32 flags = LAM_64BIT | LAR_ENABLE; 1060*a18f4b6eSLad Prabhakar u64 mask; 1061*a18f4b6eSLad Prabhakar u64 size = resource_size(entry->res); 1062*a18f4b6eSLad Prabhakar int idx = *index; 1063*a18f4b6eSLad Prabhakar 1064*a18f4b6eSLad Prabhakar if (restype & IORESOURCE_PREFETCH) 1065*a18f4b6eSLad Prabhakar flags |= LAM_PREFETCH; 1066*a18f4b6eSLad Prabhakar 1067*a18f4b6eSLad Prabhakar while (cpu_addr < cpu_end) { 1068*a18f4b6eSLad Prabhakar if (idx >= MAX_NR_INBOUND_MAPS - 1) { 1069*a18f4b6eSLad Prabhakar dev_err(pcie->dev, "Failed to map inbound regions!\n"); 1070*a18f4b6eSLad Prabhakar return -EINVAL; 1071*a18f4b6eSLad Prabhakar } 1072*a18f4b6eSLad Prabhakar /* 1073*a18f4b6eSLad Prabhakar * If the size of the range is larger than the alignment of 1074*a18f4b6eSLad Prabhakar * the start address, we have to use multiple entries to 1075*a18f4b6eSLad Prabhakar * perform the mapping. 1076*a18f4b6eSLad Prabhakar */ 1077*a18f4b6eSLad Prabhakar if (cpu_addr > 0) { 1078*a18f4b6eSLad Prabhakar unsigned long nr_zeros = __ffs64(cpu_addr); 1079*a18f4b6eSLad Prabhakar u64 alignment = 1ULL << nr_zeros; 1080*a18f4b6eSLad Prabhakar 1081*a18f4b6eSLad Prabhakar size = min(size, alignment); 1082*a18f4b6eSLad Prabhakar } 1083*a18f4b6eSLad Prabhakar /* Hardware supports max 4GiB inbound region */ 1084*a18f4b6eSLad Prabhakar size = min(size, 1ULL << 32); 1085*a18f4b6eSLad Prabhakar 1086*a18f4b6eSLad Prabhakar mask = roundup_pow_of_two(size) - 1; 1087*a18f4b6eSLad Prabhakar mask &= ~0xf; 1088*a18f4b6eSLad Prabhakar 1089*a18f4b6eSLad Prabhakar /* 1090*a18f4b6eSLad Prabhakar * Set up 64-bit inbound regions as the range parser doesn't 1091*a18f4b6eSLad Prabhakar * distinguish between 32 and 64-bit types. 1092*a18f4b6eSLad Prabhakar */ 1093*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), 1094*a18f4b6eSLad Prabhakar PCIEPRAR(idx)); 1095*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); 1096*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, 1097*a18f4b6eSLad Prabhakar PCIELAMR(idx)); 1098*a18f4b6eSLad Prabhakar 1099*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), 1100*a18f4b6eSLad Prabhakar PCIEPRAR(idx + 1)); 1101*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), 1102*a18f4b6eSLad Prabhakar PCIELAR(idx + 1)); 1103*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1)); 1104*a18f4b6eSLad Prabhakar 1105*a18f4b6eSLad Prabhakar pci_addr += size; 1106*a18f4b6eSLad Prabhakar cpu_addr += size; 1107*a18f4b6eSLad Prabhakar idx += 2; 1108*a18f4b6eSLad Prabhakar } 1109*a18f4b6eSLad Prabhakar *index = idx; 1110*a18f4b6eSLad Prabhakar 1111*a18f4b6eSLad Prabhakar return 0; 1112*a18f4b6eSLad Prabhakar } 1113*a18f4b6eSLad Prabhakar 1114*a18f4b6eSLad Prabhakar static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie) 1115*a18f4b6eSLad Prabhakar { 1116*a18f4b6eSLad Prabhakar struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1117*a18f4b6eSLad Prabhakar struct resource_entry *entry; 1118*a18f4b6eSLad Prabhakar int index = 0, err = 0; 1119*a18f4b6eSLad Prabhakar 1120*a18f4b6eSLad Prabhakar resource_list_for_each_entry(entry, &bridge->dma_ranges) { 1121*a18f4b6eSLad Prabhakar err = rcar_pcie_inbound_ranges(pcie, entry, &index); 1122*a18f4b6eSLad Prabhakar if (err) 1123*a18f4b6eSLad Prabhakar break; 1124*a18f4b6eSLad Prabhakar } 1125*a18f4b6eSLad Prabhakar 1126*a18f4b6eSLad Prabhakar return err; 1127*a18f4b6eSLad Prabhakar } 1128*a18f4b6eSLad Prabhakar 1129*a18f4b6eSLad Prabhakar static const struct of_device_id rcar_pcie_of_match[] = { 1130*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-r8a7779", 1131*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_h1 }, 1132*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-r8a7790", 1133*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_gen2 }, 1134*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-r8a7791", 1135*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_gen2 }, 1136*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-rcar-gen2", 1137*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_gen2 }, 1138*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-r8a7795", 1139*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_gen3 }, 1140*a18f4b6eSLad Prabhakar { .compatible = "renesas,pcie-rcar-gen3", 1141*a18f4b6eSLad Prabhakar .data = rcar_pcie_phy_init_gen3 }, 1142*a18f4b6eSLad Prabhakar {}, 1143*a18f4b6eSLad Prabhakar }; 1144*a18f4b6eSLad Prabhakar 1145*a18f4b6eSLad Prabhakar static int rcar_pcie_probe(struct platform_device *pdev) 1146*a18f4b6eSLad Prabhakar { 1147*a18f4b6eSLad Prabhakar struct device *dev = &pdev->dev; 1148*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie; 1149*a18f4b6eSLad Prabhakar u32 data; 1150*a18f4b6eSLad Prabhakar int err; 1151*a18f4b6eSLad Prabhakar struct pci_host_bridge *bridge; 1152*a18f4b6eSLad Prabhakar 1153*a18f4b6eSLad Prabhakar bridge = pci_alloc_host_bridge(sizeof(*pcie)); 1154*a18f4b6eSLad Prabhakar if (!bridge) 1155*a18f4b6eSLad Prabhakar return -ENOMEM; 1156*a18f4b6eSLad Prabhakar 1157*a18f4b6eSLad Prabhakar pcie = pci_host_bridge_priv(bridge); 1158*a18f4b6eSLad Prabhakar 1159*a18f4b6eSLad Prabhakar pcie->dev = dev; 1160*a18f4b6eSLad Prabhakar platform_set_drvdata(pdev, pcie); 1161*a18f4b6eSLad Prabhakar 1162*a18f4b6eSLad Prabhakar err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, 1163*a18f4b6eSLad Prabhakar &bridge->dma_ranges, NULL); 1164*a18f4b6eSLad Prabhakar if (err) 1165*a18f4b6eSLad Prabhakar goto err_free_bridge; 1166*a18f4b6eSLad Prabhakar 1167*a18f4b6eSLad Prabhakar pm_runtime_enable(pcie->dev); 1168*a18f4b6eSLad Prabhakar err = pm_runtime_get_sync(pcie->dev); 1169*a18f4b6eSLad Prabhakar if (err < 0) { 1170*a18f4b6eSLad Prabhakar dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 1171*a18f4b6eSLad Prabhakar goto err_pm_disable; 1172*a18f4b6eSLad Prabhakar } 1173*a18f4b6eSLad Prabhakar 1174*a18f4b6eSLad Prabhakar err = rcar_pcie_get_resources(pcie); 1175*a18f4b6eSLad Prabhakar if (err < 0) { 1176*a18f4b6eSLad Prabhakar dev_err(dev, "failed to request resources: %d\n", err); 1177*a18f4b6eSLad Prabhakar goto err_pm_put; 1178*a18f4b6eSLad Prabhakar } 1179*a18f4b6eSLad Prabhakar 1180*a18f4b6eSLad Prabhakar err = clk_prepare_enable(pcie->bus_clk); 1181*a18f4b6eSLad Prabhakar if (err) { 1182*a18f4b6eSLad Prabhakar dev_err(dev, "failed to enable bus clock: %d\n", err); 1183*a18f4b6eSLad Prabhakar goto err_unmap_msi_irqs; 1184*a18f4b6eSLad Prabhakar } 1185*a18f4b6eSLad Prabhakar 1186*a18f4b6eSLad Prabhakar err = rcar_pcie_parse_map_dma_ranges(pcie); 1187*a18f4b6eSLad Prabhakar if (err) 1188*a18f4b6eSLad Prabhakar goto err_clk_disable; 1189*a18f4b6eSLad Prabhakar 1190*a18f4b6eSLad Prabhakar pcie->phy_init_fn = of_device_get_match_data(dev); 1191*a18f4b6eSLad Prabhakar err = pcie->phy_init_fn(pcie); 1192*a18f4b6eSLad Prabhakar if (err) { 1193*a18f4b6eSLad Prabhakar dev_err(dev, "failed to init PCIe PHY\n"); 1194*a18f4b6eSLad Prabhakar goto err_clk_disable; 1195*a18f4b6eSLad Prabhakar } 1196*a18f4b6eSLad Prabhakar 1197*a18f4b6eSLad Prabhakar /* Failure to get a link might just be that no cards are inserted */ 1198*a18f4b6eSLad Prabhakar if (rcar_pcie_hw_init(pcie)) { 1199*a18f4b6eSLad Prabhakar dev_info(dev, "PCIe link down\n"); 1200*a18f4b6eSLad Prabhakar err = -ENODEV; 1201*a18f4b6eSLad Prabhakar goto err_phy_shutdown; 1202*a18f4b6eSLad Prabhakar } 1203*a18f4b6eSLad Prabhakar 1204*a18f4b6eSLad Prabhakar data = rcar_pci_read_reg(pcie, MACSR); 1205*a18f4b6eSLad Prabhakar dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1206*a18f4b6eSLad Prabhakar 1207*a18f4b6eSLad Prabhakar if (IS_ENABLED(CONFIG_PCI_MSI)) { 1208*a18f4b6eSLad Prabhakar err = rcar_pcie_enable_msi(pcie); 1209*a18f4b6eSLad Prabhakar if (err < 0) { 1210*a18f4b6eSLad Prabhakar dev_err(dev, 1211*a18f4b6eSLad Prabhakar "failed to enable MSI support: %d\n", 1212*a18f4b6eSLad Prabhakar err); 1213*a18f4b6eSLad Prabhakar goto err_phy_shutdown; 1214*a18f4b6eSLad Prabhakar } 1215*a18f4b6eSLad Prabhakar } 1216*a18f4b6eSLad Prabhakar 1217*a18f4b6eSLad Prabhakar err = rcar_pcie_enable(pcie); 1218*a18f4b6eSLad Prabhakar if (err) 1219*a18f4b6eSLad Prabhakar goto err_msi_teardown; 1220*a18f4b6eSLad Prabhakar 1221*a18f4b6eSLad Prabhakar return 0; 1222*a18f4b6eSLad Prabhakar 1223*a18f4b6eSLad Prabhakar err_msi_teardown: 1224*a18f4b6eSLad Prabhakar if (IS_ENABLED(CONFIG_PCI_MSI)) 1225*a18f4b6eSLad Prabhakar rcar_pcie_teardown_msi(pcie); 1226*a18f4b6eSLad Prabhakar 1227*a18f4b6eSLad Prabhakar err_phy_shutdown: 1228*a18f4b6eSLad Prabhakar if (pcie->phy) { 1229*a18f4b6eSLad Prabhakar phy_power_off(pcie->phy); 1230*a18f4b6eSLad Prabhakar phy_exit(pcie->phy); 1231*a18f4b6eSLad Prabhakar } 1232*a18f4b6eSLad Prabhakar 1233*a18f4b6eSLad Prabhakar err_clk_disable: 1234*a18f4b6eSLad Prabhakar clk_disable_unprepare(pcie->bus_clk); 1235*a18f4b6eSLad Prabhakar 1236*a18f4b6eSLad Prabhakar err_unmap_msi_irqs: 1237*a18f4b6eSLad Prabhakar irq_dispose_mapping(pcie->msi.irq2); 1238*a18f4b6eSLad Prabhakar irq_dispose_mapping(pcie->msi.irq1); 1239*a18f4b6eSLad Prabhakar 1240*a18f4b6eSLad Prabhakar err_pm_put: 1241*a18f4b6eSLad Prabhakar pm_runtime_put(dev); 1242*a18f4b6eSLad Prabhakar 1243*a18f4b6eSLad Prabhakar err_pm_disable: 1244*a18f4b6eSLad Prabhakar pm_runtime_disable(dev); 1245*a18f4b6eSLad Prabhakar pci_free_resource_list(&pcie->resources); 1246*a18f4b6eSLad Prabhakar 1247*a18f4b6eSLad Prabhakar err_free_bridge: 1248*a18f4b6eSLad Prabhakar pci_free_host_bridge(bridge); 1249*a18f4b6eSLad Prabhakar 1250*a18f4b6eSLad Prabhakar return err; 1251*a18f4b6eSLad Prabhakar } 1252*a18f4b6eSLad Prabhakar 1253*a18f4b6eSLad Prabhakar static int __maybe_unused rcar_pcie_resume(struct device *dev) 1254*a18f4b6eSLad Prabhakar { 1255*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = dev_get_drvdata(dev); 1256*a18f4b6eSLad Prabhakar unsigned int data; 1257*a18f4b6eSLad Prabhakar int err; 1258*a18f4b6eSLad Prabhakar 1259*a18f4b6eSLad Prabhakar err = rcar_pcie_parse_map_dma_ranges(pcie); 1260*a18f4b6eSLad Prabhakar if (err) 1261*a18f4b6eSLad Prabhakar return 0; 1262*a18f4b6eSLad Prabhakar 1263*a18f4b6eSLad Prabhakar /* Failure to get a link might just be that no cards are inserted */ 1264*a18f4b6eSLad Prabhakar err = pcie->phy_init_fn(pcie); 1265*a18f4b6eSLad Prabhakar if (err) { 1266*a18f4b6eSLad Prabhakar dev_info(dev, "PCIe link down\n"); 1267*a18f4b6eSLad Prabhakar return 0; 1268*a18f4b6eSLad Prabhakar } 1269*a18f4b6eSLad Prabhakar 1270*a18f4b6eSLad Prabhakar data = rcar_pci_read_reg(pcie, MACSR); 1271*a18f4b6eSLad Prabhakar dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1272*a18f4b6eSLad Prabhakar 1273*a18f4b6eSLad Prabhakar /* Enable MSI */ 1274*a18f4b6eSLad Prabhakar if (IS_ENABLED(CONFIG_PCI_MSI)) 1275*a18f4b6eSLad Prabhakar rcar_pcie_hw_enable_msi(pcie); 1276*a18f4b6eSLad Prabhakar 1277*a18f4b6eSLad Prabhakar rcar_pcie_hw_enable(pcie); 1278*a18f4b6eSLad Prabhakar 1279*a18f4b6eSLad Prabhakar return 0; 1280*a18f4b6eSLad Prabhakar } 1281*a18f4b6eSLad Prabhakar 1282*a18f4b6eSLad Prabhakar static int rcar_pcie_resume_noirq(struct device *dev) 1283*a18f4b6eSLad Prabhakar { 1284*a18f4b6eSLad Prabhakar struct rcar_pcie *pcie = dev_get_drvdata(dev); 1285*a18f4b6eSLad Prabhakar 1286*a18f4b6eSLad Prabhakar if (rcar_pci_read_reg(pcie, PMSR) && 1287*a18f4b6eSLad Prabhakar !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1288*a18f4b6eSLad Prabhakar return 0; 1289*a18f4b6eSLad Prabhakar 1290*a18f4b6eSLad Prabhakar /* Re-establish the PCIe link */ 1291*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1292*a18f4b6eSLad Prabhakar rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1293*a18f4b6eSLad Prabhakar return rcar_pcie_wait_for_dl(pcie); 1294*a18f4b6eSLad Prabhakar } 1295*a18f4b6eSLad Prabhakar 1296*a18f4b6eSLad Prabhakar static const struct dev_pm_ops rcar_pcie_pm_ops = { 1297*a18f4b6eSLad Prabhakar SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1298*a18f4b6eSLad Prabhakar .resume_noirq = rcar_pcie_resume_noirq, 1299*a18f4b6eSLad Prabhakar }; 1300*a18f4b6eSLad Prabhakar 1301*a18f4b6eSLad Prabhakar static struct platform_driver rcar_pcie_driver = { 1302*a18f4b6eSLad Prabhakar .driver = { 1303*a18f4b6eSLad Prabhakar .name = "rcar-pcie", 1304*a18f4b6eSLad Prabhakar .of_match_table = rcar_pcie_of_match, 1305*a18f4b6eSLad Prabhakar .pm = &rcar_pcie_pm_ops, 1306*a18f4b6eSLad Prabhakar .suppress_bind_attrs = true, 1307*a18f4b6eSLad Prabhakar }, 1308*a18f4b6eSLad Prabhakar .probe = rcar_pcie_probe, 1309*a18f4b6eSLad Prabhakar }; 1310*a18f4b6eSLad Prabhakar builtin_platform_driver(rcar_pcie_driver); 1311