1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Microchip AXI PCIe Bridge host controller driver
4  *
5  * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
6  *
7  * Author: Daire McNamara <daire.mcnamara@microchip.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/module.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci-ecam.h>
18 #include <linux/platform_device.h>
19 
20 #include "../pci.h"
21 
22 /* Number of MSI IRQs */
23 #define MC_NUM_MSI_IRQS				32
24 #define MC_NUM_MSI_IRQS_CODED			5
25 
26 /* PCIe Bridge Phy and Controller Phy offsets */
27 #define MC_PCIE1_BRIDGE_ADDR			0x00008000u
28 #define MC_PCIE1_CTRL_ADDR			0x0000a000u
29 
30 #define MC_PCIE_BRIDGE_ADDR			(MC_PCIE1_BRIDGE_ADDR)
31 #define MC_PCIE_CTRL_ADDR			(MC_PCIE1_CTRL_ADDR)
32 
33 /* PCIe Controller Phy Regs */
34 #define SEC_ERROR_CNT				0x20
35 #define DED_ERROR_CNT				0x24
36 #define SEC_ERROR_INT				0x28
37 #define  SEC_ERROR_INT_TX_RAM_SEC_ERR_INT	GENMASK(3, 0)
38 #define  SEC_ERROR_INT_RX_RAM_SEC_ERR_INT	GENMASK(7, 4)
39 #define  SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT	GENMASK(11, 8)
40 #define  SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT	GENMASK(15, 12)
41 #define  NUM_SEC_ERROR_INTS			(4)
42 #define SEC_ERROR_INT_MASK			0x2c
43 #define DED_ERROR_INT				0x30
44 #define  DED_ERROR_INT_TX_RAM_DED_ERR_INT	GENMASK(3, 0)
45 #define  DED_ERROR_INT_RX_RAM_DED_ERR_INT	GENMASK(7, 4)
46 #define  DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT	GENMASK(11, 8)
47 #define  DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT	GENMASK(15, 12)
48 #define  NUM_DED_ERROR_INTS			(4)
49 #define DED_ERROR_INT_MASK			0x34
50 #define ECC_CONTROL				0x38
51 #define  ECC_CONTROL_TX_RAM_INJ_ERROR_0		BIT(0)
52 #define  ECC_CONTROL_TX_RAM_INJ_ERROR_1		BIT(1)
53 #define  ECC_CONTROL_TX_RAM_INJ_ERROR_2		BIT(2)
54 #define  ECC_CONTROL_TX_RAM_INJ_ERROR_3		BIT(3)
55 #define  ECC_CONTROL_RX_RAM_INJ_ERROR_0		BIT(4)
56 #define  ECC_CONTROL_RX_RAM_INJ_ERROR_1		BIT(5)
57 #define  ECC_CONTROL_RX_RAM_INJ_ERROR_2		BIT(6)
58 #define  ECC_CONTROL_RX_RAM_INJ_ERROR_3		BIT(7)
59 #define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0	BIT(8)
60 #define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1	BIT(9)
61 #define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2	BIT(10)
62 #define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3	BIT(11)
63 #define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0	BIT(12)
64 #define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1	BIT(13)
65 #define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2	BIT(14)
66 #define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3	BIT(15)
67 #define  ECC_CONTROL_TX_RAM_ECC_BYPASS		BIT(24)
68 #define  ECC_CONTROL_RX_RAM_ECC_BYPASS		BIT(25)
69 #define  ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS	BIT(26)
70 #define  ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS	BIT(27)
71 #define LTSSM_STATE				0x5c
72 #define  LTSSM_L0_STATE				0x10
73 #define PCIE_EVENT_INT				0x14c
74 #define  PCIE_EVENT_INT_L2_EXIT_INT		BIT(0)
75 #define  PCIE_EVENT_INT_HOTRST_EXIT_INT		BIT(1)
76 #define  PCIE_EVENT_INT_DLUP_EXIT_INT		BIT(2)
77 #define  PCIE_EVENT_INT_MASK			GENMASK(2, 0)
78 #define  PCIE_EVENT_INT_L2_EXIT_INT_MASK	BIT(16)
79 #define  PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK	BIT(17)
80 #define  PCIE_EVENT_INT_DLUP_EXIT_INT_MASK	BIT(18)
81 #define  PCIE_EVENT_INT_ENB_MASK		GENMASK(18, 16)
82 #define  PCIE_EVENT_INT_ENB_SHIFT		16
83 #define  NUM_PCIE_EVENTS			(3)
84 
85 /* PCIe Bridge Phy Regs */
86 #define PCIE_PCI_IDS_DW1			0x9c
87 
88 /* PCIe Config space MSI capability structure */
89 #define MC_MSI_CAP_CTRL_OFFSET			0xe0u
90 #define  MC_MSI_MAX_Q_AVAIL			(MC_NUM_MSI_IRQS_CODED << 1)
91 #define  MC_MSI_Q_SIZE				(MC_NUM_MSI_IRQS_CODED << 4)
92 
93 #define IMASK_LOCAL				0x180
94 #define  DMA_END_ENGINE_0_MASK			0x00000000u
95 #define  DMA_END_ENGINE_0_SHIFT			0
96 #define  DMA_END_ENGINE_1_MASK			0x00000000u
97 #define  DMA_END_ENGINE_1_SHIFT			1
98 #define  DMA_ERROR_ENGINE_0_MASK		0x00000100u
99 #define  DMA_ERROR_ENGINE_0_SHIFT		8
100 #define  DMA_ERROR_ENGINE_1_MASK		0x00000200u
101 #define  DMA_ERROR_ENGINE_1_SHIFT		9
102 #define  A_ATR_EVT_POST_ERR_MASK		0x00010000u
103 #define  A_ATR_EVT_POST_ERR_SHIFT		16
104 #define  A_ATR_EVT_FETCH_ERR_MASK		0x00020000u
105 #define  A_ATR_EVT_FETCH_ERR_SHIFT		17
106 #define  A_ATR_EVT_DISCARD_ERR_MASK		0x00040000u
107 #define  A_ATR_EVT_DISCARD_ERR_SHIFT		18
108 #define  A_ATR_EVT_DOORBELL_MASK		0x00000000u
109 #define  A_ATR_EVT_DOORBELL_SHIFT		19
110 #define  P_ATR_EVT_POST_ERR_MASK		0x00100000u
111 #define  P_ATR_EVT_POST_ERR_SHIFT		20
112 #define  P_ATR_EVT_FETCH_ERR_MASK		0x00200000u
113 #define  P_ATR_EVT_FETCH_ERR_SHIFT		21
114 #define  P_ATR_EVT_DISCARD_ERR_MASK		0x00400000u
115 #define  P_ATR_EVT_DISCARD_ERR_SHIFT		22
116 #define  P_ATR_EVT_DOORBELL_MASK		0x00000000u
117 #define  P_ATR_EVT_DOORBELL_SHIFT		23
118 #define  PM_MSI_INT_INTA_MASK			0x01000000u
119 #define  PM_MSI_INT_INTA_SHIFT			24
120 #define  PM_MSI_INT_INTB_MASK			0x02000000u
121 #define  PM_MSI_INT_INTB_SHIFT			25
122 #define  PM_MSI_INT_INTC_MASK			0x04000000u
123 #define  PM_MSI_INT_INTC_SHIFT			26
124 #define  PM_MSI_INT_INTD_MASK			0x08000000u
125 #define  PM_MSI_INT_INTD_SHIFT			27
126 #define  PM_MSI_INT_INTX_MASK			0x0f000000u
127 #define  PM_MSI_INT_INTX_SHIFT			24
128 #define  PM_MSI_INT_MSI_MASK			0x10000000u
129 #define  PM_MSI_INT_MSI_SHIFT			28
130 #define  PM_MSI_INT_AER_EVT_MASK		0x20000000u
131 #define  PM_MSI_INT_AER_EVT_SHIFT		29
132 #define  PM_MSI_INT_EVENTS_MASK			0x40000000u
133 #define  PM_MSI_INT_EVENTS_SHIFT		30
134 #define  PM_MSI_INT_SYS_ERR_MASK		0x80000000u
135 #define  PM_MSI_INT_SYS_ERR_SHIFT		31
136 #define  NUM_LOCAL_EVENTS			15
137 #define ISTATUS_LOCAL				0x184
138 #define IMASK_HOST				0x188
139 #define ISTATUS_HOST				0x18c
140 #define MSI_ADDR				0x190
141 #define ISTATUS_MSI				0x194
142 
143 /* PCIe Master table init defines */
144 #define ATR0_PCIE_WIN0_SRCADDR_PARAM		0x600u
145 #define  ATR0_PCIE_ATR_SIZE			0x25
146 #define  ATR0_PCIE_ATR_SIZE_SHIFT		1
147 #define ATR0_PCIE_WIN0_SRC_ADDR			0x604u
148 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB		0x608u
149 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW		0x60cu
150 #define ATR0_PCIE_WIN0_TRSL_PARAM		0x610u
151 
152 /* PCIe AXI slave table init defines */
153 #define ATR0_AXI4_SLV0_SRCADDR_PARAM		0x800u
154 #define  ATR_SIZE_SHIFT				1
155 #define  ATR_IMPL_ENABLE			1
156 #define ATR0_AXI4_SLV0_SRC_ADDR			0x804u
157 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB		0x808u
158 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW		0x80cu
159 #define ATR0_AXI4_SLV0_TRSL_PARAM		0x810u
160 #define  PCIE_TX_RX_INTERFACE			0x00000000u
161 #define  PCIE_CONFIG_INTERFACE			0x00000001u
162 
163 #define ATR_ENTRY_SIZE				32
164 
165 #define EVENT_PCIE_L2_EXIT			0
166 #define EVENT_PCIE_HOTRST_EXIT			1
167 #define EVENT_PCIE_DLUP_EXIT			2
168 #define EVENT_SEC_TX_RAM_SEC_ERR		3
169 #define EVENT_SEC_RX_RAM_SEC_ERR		4
170 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR		5
171 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR		6
172 #define EVENT_DED_TX_RAM_DED_ERR		7
173 #define EVENT_DED_RX_RAM_DED_ERR		8
174 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR		9
175 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR		10
176 #define EVENT_LOCAL_DMA_END_ENGINE_0		11
177 #define EVENT_LOCAL_DMA_END_ENGINE_1		12
178 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0		13
179 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1		14
180 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR		15
181 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR		16
182 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR	17
183 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL		18
184 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR		19
185 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR		20
186 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR	21
187 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL		22
188 #define EVENT_LOCAL_PM_MSI_INT_INTX		23
189 #define EVENT_LOCAL_PM_MSI_INT_MSI		24
190 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT		25
191 #define EVENT_LOCAL_PM_MSI_INT_EVENTS		26
192 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR		27
193 #define NUM_EVENTS				28
194 
195 #define PCIE_EVENT_CAUSE(x, s)	\
196 	[EVENT_PCIE_ ## x] = { __stringify(x), s }
197 
198 #define SEC_ERROR_CAUSE(x, s) \
199 	[EVENT_SEC_ ## x] = { __stringify(x), s }
200 
201 #define DED_ERROR_CAUSE(x, s) \
202 	[EVENT_DED_ ## x] = { __stringify(x), s }
203 
204 #define LOCAL_EVENT_CAUSE(x, s) \
205 	[EVENT_LOCAL_ ## x] = { __stringify(x), s }
206 
207 #define PCIE_EVENT(x) \
208 	.base = MC_PCIE_CTRL_ADDR, \
209 	.offset = PCIE_EVENT_INT, \
210 	.mask_offset = PCIE_EVENT_INT, \
211 	.mask_high = 1, \
212 	.mask = PCIE_EVENT_INT_ ## x ## _INT, \
213 	.enb_mask = PCIE_EVENT_INT_ENB_MASK
214 
215 #define SEC_EVENT(x) \
216 	.base = MC_PCIE_CTRL_ADDR, \
217 	.offset = SEC_ERROR_INT, \
218 	.mask_offset = SEC_ERROR_INT_MASK, \
219 	.mask = SEC_ERROR_INT_ ## x ## _INT, \
220 	.mask_high = 1, \
221 	.enb_mask = 0
222 
223 #define DED_EVENT(x) \
224 	.base = MC_PCIE_CTRL_ADDR, \
225 	.offset = DED_ERROR_INT, \
226 	.mask_offset = DED_ERROR_INT_MASK, \
227 	.mask_high = 1, \
228 	.mask = DED_ERROR_INT_ ## x ## _INT, \
229 	.enb_mask = 0
230 
231 #define LOCAL_EVENT(x) \
232 	.base = MC_PCIE_BRIDGE_ADDR, \
233 	.offset = ISTATUS_LOCAL, \
234 	.mask_offset = IMASK_LOCAL, \
235 	.mask_high = 0, \
236 	.mask = x ## _MASK, \
237 	.enb_mask = 0
238 
239 #define PCIE_EVENT_TO_EVENT_MAP(x) \
240 	{ PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x }
241 
242 #define SEC_ERROR_TO_EVENT_MAP(x) \
243 	{ SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x }
244 
245 #define DED_ERROR_TO_EVENT_MAP(x) \
246 	{ DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x }
247 
248 #define LOCAL_STATUS_TO_EVENT_MAP(x) \
249 	{ x ## _MASK, EVENT_LOCAL_ ## x }
250 
251 struct event_map {
252 	u32 reg_mask;
253 	u32 event_bit;
254 };
255 
256 struct mc_msi {
257 	struct mutex lock;		/* Protect used bitmap */
258 	struct irq_domain *msi_domain;
259 	struct irq_domain *dev_domain;
260 	u32 num_vectors;
261 	u64 vector_phy;
262 	DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);
263 };
264 
265 struct mc_port {
266 	void __iomem *axi_base_addr;
267 	struct device *dev;
268 	struct irq_domain *intx_domain;
269 	struct irq_domain *event_domain;
270 	raw_spinlock_t lock;
271 	struct mc_msi msi;
272 };
273 
274 struct cause {
275 	const char *sym;
276 	const char *str;
277 };
278 
279 static const struct cause event_cause[NUM_EVENTS] = {
280 	PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"),
281 	PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"),
282 	PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"),
283 	SEC_ERROR_CAUSE(TX_RAM_SEC_ERR,  "sec error in tx buffer"),
284 	SEC_ERROR_CAUSE(RX_RAM_SEC_ERR,  "sec error in rx buffer"),
285 	SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR,  "sec error in pcie2axi buffer"),
286 	SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR,  "sec error in axi2pcie buffer"),
287 	DED_ERROR_CAUSE(TX_RAM_DED_ERR,  "ded error in tx buffer"),
288 	DED_ERROR_CAUSE(RX_RAM_DED_ERR,  "ded error in rx buffer"),
289 	DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR,  "ded error in pcie2axi buffer"),
290 	DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR,  "ded error in axi2pcie buffer"),
291 	LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
292 	LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
293 	LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
294 	LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
295 	LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
296 	LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
297 	LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
298 	LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
299 	LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"),
300 	LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"),
301 	LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"),
302 };
303 
304 static struct event_map pcie_event_to_event[] = {
305 	PCIE_EVENT_TO_EVENT_MAP(L2_EXIT),
306 	PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT),
307 	PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT),
308 };
309 
310 static struct event_map sec_error_to_event[] = {
311 	SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR),
312 	SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR),
313 	SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR),
314 	SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR),
315 };
316 
317 static struct event_map ded_error_to_event[] = {
318 	DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR),
319 	DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR),
320 	DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR),
321 	DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR),
322 };
323 
324 static struct event_map local_status_to_event[] = {
325 	LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0),
326 	LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1),
327 	LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0),
328 	LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1),
329 	LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR),
330 	LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR),
331 	LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR),
332 	LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL),
333 	LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR),
334 	LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR),
335 	LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR),
336 	LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL),
337 	LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX),
338 	LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI),
339 	LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT),
340 	LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS),
341 	LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR),
342 };
343 
344 static struct {
345 	u32 base;
346 	u32 offset;
347 	u32 mask;
348 	u32 shift;
349 	u32 enb_mask;
350 	u32 mask_high;
351 	u32 mask_offset;
352 } event_descs[] = {
353 	{ PCIE_EVENT(L2_EXIT) },
354 	{ PCIE_EVENT(HOTRST_EXIT) },
355 	{ PCIE_EVENT(DLUP_EXIT) },
356 	{ SEC_EVENT(TX_RAM_SEC_ERR) },
357 	{ SEC_EVENT(RX_RAM_SEC_ERR) },
358 	{ SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) },
359 	{ SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) },
360 	{ DED_EVENT(TX_RAM_DED_ERR) },
361 	{ DED_EVENT(RX_RAM_DED_ERR) },
362 	{ DED_EVENT(PCIE2AXI_RAM_DED_ERR) },
363 	{ DED_EVENT(AXI2PCIE_RAM_DED_ERR) },
364 	{ LOCAL_EVENT(DMA_END_ENGINE_0) },
365 	{ LOCAL_EVENT(DMA_END_ENGINE_1) },
366 	{ LOCAL_EVENT(DMA_ERROR_ENGINE_0) },
367 	{ LOCAL_EVENT(DMA_ERROR_ENGINE_1) },
368 	{ LOCAL_EVENT(A_ATR_EVT_POST_ERR) },
369 	{ LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) },
370 	{ LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) },
371 	{ LOCAL_EVENT(A_ATR_EVT_DOORBELL) },
372 	{ LOCAL_EVENT(P_ATR_EVT_POST_ERR) },
373 	{ LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) },
374 	{ LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) },
375 	{ LOCAL_EVENT(P_ATR_EVT_DOORBELL) },
376 	{ LOCAL_EVENT(PM_MSI_INT_INTX) },
377 	{ LOCAL_EVENT(PM_MSI_INT_MSI) },
378 	{ LOCAL_EVENT(PM_MSI_INT_AER_EVT) },
379 	{ LOCAL_EVENT(PM_MSI_INT_EVENTS) },
380 	{ LOCAL_EVENT(PM_MSI_INT_SYS_ERR) },
381 };
382 
383 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
384 
385 static void mc_pcie_enable_msi(struct mc_port *port, void __iomem *base)
386 {
387 	struct mc_msi *msi = &port->msi;
388 	u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;
389 	u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);
390 
391 	msg_ctrl |= PCI_MSI_FLAGS_ENABLE;
392 	msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;
393 	msg_ctrl |= MC_MSI_MAX_Q_AVAIL;
394 	msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
395 	msg_ctrl |= MC_MSI_Q_SIZE;
396 	msg_ctrl |= PCI_MSI_FLAGS_64BIT;
397 
398 	writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
399 
400 	writel_relaxed(lower_32_bits(msi->vector_phy),
401 		       base + cap_offset + PCI_MSI_ADDRESS_LO);
402 	writel_relaxed(upper_32_bits(msi->vector_phy),
403 		       base + cap_offset + PCI_MSI_ADDRESS_HI);
404 }
405 
406 static void mc_handle_msi(struct irq_desc *desc)
407 {
408 	struct mc_port *port = irq_desc_get_handler_data(desc);
409 	struct device *dev = port->dev;
410 	struct mc_msi *msi = &port->msi;
411 	void __iomem *bridge_base_addr =
412 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
413 	unsigned long status;
414 	u32 bit;
415 	u32 virq;
416 
417 	status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
418 	if (status & PM_MSI_INT_MSI_MASK) {
419 		status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
420 		for_each_set_bit(bit, &status, msi->num_vectors) {
421 			virq = irq_find_mapping(msi->dev_domain, bit);
422 			if (virq)
423 				generic_handle_irq(virq);
424 			else
425 				dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
426 						    bit);
427 		}
428 	}
429 }
430 
431 static void mc_msi_bottom_irq_ack(struct irq_data *data)
432 {
433 	struct mc_port *port = irq_data_get_irq_chip_data(data);
434 	void __iomem *bridge_base_addr =
435 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
436 	u32 bitpos = data->hwirq;
437 	unsigned long status;
438 
439 	writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
440 	status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
441 	if (!status)
442 		writel_relaxed(BIT(PM_MSI_INT_MSI_SHIFT),
443 			       bridge_base_addr + ISTATUS_LOCAL);
444 }
445 
446 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
447 {
448 	struct mc_port *port = irq_data_get_irq_chip_data(data);
449 	phys_addr_t addr = port->msi.vector_phy;
450 
451 	msg->address_lo = lower_32_bits(addr);
452 	msg->address_hi = upper_32_bits(addr);
453 	msg->data = data->hwirq;
454 
455 	dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n",
456 		(int)data->hwirq, msg->address_hi, msg->address_lo);
457 }
458 
459 static int mc_msi_set_affinity(struct irq_data *irq_data,
460 			       const struct cpumask *mask, bool force)
461 {
462 	return -EINVAL;
463 }
464 
465 static struct irq_chip mc_msi_bottom_irq_chip = {
466 	.name = "Microchip MSI",
467 	.irq_ack = mc_msi_bottom_irq_ack,
468 	.irq_compose_msi_msg = mc_compose_msi_msg,
469 	.irq_set_affinity = mc_msi_set_affinity,
470 };
471 
472 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
473 				   unsigned int nr_irqs, void *args)
474 {
475 	struct mc_port *port = domain->host_data;
476 	struct mc_msi *msi = &port->msi;
477 	void __iomem *bridge_base_addr =
478 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
479 	unsigned long bit;
480 	u32 val;
481 
482 	mutex_lock(&msi->lock);
483 	bit = find_first_zero_bit(msi->used, msi->num_vectors);
484 	if (bit >= msi->num_vectors) {
485 		mutex_unlock(&msi->lock);
486 		return -ENOSPC;
487 	}
488 
489 	set_bit(bit, msi->used);
490 
491 	irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,
492 			    domain->host_data, handle_edge_irq, NULL, NULL);
493 
494 	/* Enable MSI interrupts */
495 	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
496 	val |= PM_MSI_INT_MSI_MASK;
497 	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
498 
499 	mutex_unlock(&msi->lock);
500 
501 	return 0;
502 }
503 
504 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq,
505 				   unsigned int nr_irqs)
506 {
507 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
508 	struct mc_port *port = irq_data_get_irq_chip_data(d);
509 	struct mc_msi *msi = &port->msi;
510 
511 	mutex_lock(&msi->lock);
512 
513 	if (test_bit(d->hwirq, msi->used))
514 		__clear_bit(d->hwirq, msi->used);
515 	else
516 		dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq);
517 
518 	mutex_unlock(&msi->lock);
519 }
520 
521 static const struct irq_domain_ops msi_domain_ops = {
522 	.alloc	= mc_irq_msi_domain_alloc,
523 	.free	= mc_irq_msi_domain_free,
524 };
525 
526 static struct irq_chip mc_msi_irq_chip = {
527 	.name = "Microchip PCIe MSI",
528 	.irq_ack = irq_chip_ack_parent,
529 	.irq_mask = pci_msi_mask_irq,
530 	.irq_unmask = pci_msi_unmask_irq,
531 };
532 
533 static struct msi_domain_info mc_msi_domain_info = {
534 	.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
535 		  MSI_FLAG_PCI_MSIX),
536 	.chip = &mc_msi_irq_chip,
537 };
538 
539 static int mc_allocate_msi_domains(struct mc_port *port)
540 {
541 	struct device *dev = port->dev;
542 	struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
543 	struct mc_msi *msi = &port->msi;
544 
545 	mutex_init(&port->msi.lock);
546 
547 	msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors,
548 						&msi_domain_ops, port);
549 	if (!msi->dev_domain) {
550 		dev_err(dev, "failed to create IRQ domain\n");
551 		return -ENOMEM;
552 	}
553 
554 	msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info,
555 						    msi->dev_domain);
556 	if (!msi->msi_domain) {
557 		dev_err(dev, "failed to create MSI domain\n");
558 		irq_domain_remove(msi->dev_domain);
559 		return -ENOMEM;
560 	}
561 
562 	return 0;
563 }
564 
565 static void mc_handle_intx(struct irq_desc *desc)
566 {
567 	struct mc_port *port = irq_desc_get_handler_data(desc);
568 	struct device *dev = port->dev;
569 	void __iomem *bridge_base_addr =
570 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
571 	unsigned long status;
572 	u32 bit;
573 	u32 virq;
574 
575 	status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
576 	if (status & PM_MSI_INT_INTX_MASK) {
577 		status &= PM_MSI_INT_INTX_MASK;
578 		status >>= PM_MSI_INT_INTX_SHIFT;
579 		for_each_set_bit(bit, &status, PCI_NUM_INTX) {
580 			virq = irq_find_mapping(port->intx_domain, bit);
581 			if (virq)
582 				generic_handle_irq(virq);
583 			else
584 				dev_err_ratelimited(dev, "bad INTx IRQ %d\n",
585 						    bit);
586 		}
587 	}
588 }
589 
590 static void mc_ack_intx_irq(struct irq_data *data)
591 {
592 	struct mc_port *port = irq_data_get_irq_chip_data(data);
593 	void __iomem *bridge_base_addr =
594 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
595 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
596 
597 	writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
598 }
599 
600 static void mc_mask_intx_irq(struct irq_data *data)
601 {
602 	struct mc_port *port = irq_data_get_irq_chip_data(data);
603 	void __iomem *bridge_base_addr =
604 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
605 	unsigned long flags;
606 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
607 	u32 val;
608 
609 	raw_spin_lock_irqsave(&port->lock, flags);
610 	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
611 	val &= ~mask;
612 	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
613 	raw_spin_unlock_irqrestore(&port->lock, flags);
614 }
615 
616 static void mc_unmask_intx_irq(struct irq_data *data)
617 {
618 	struct mc_port *port = irq_data_get_irq_chip_data(data);
619 	void __iomem *bridge_base_addr =
620 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
621 	unsigned long flags;
622 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
623 	u32 val;
624 
625 	raw_spin_lock_irqsave(&port->lock, flags);
626 	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
627 	val |= mask;
628 	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
629 	raw_spin_unlock_irqrestore(&port->lock, flags);
630 }
631 
632 static struct irq_chip mc_intx_irq_chip = {
633 	.name = "Microchip PCIe INTx",
634 	.irq_ack = mc_ack_intx_irq,
635 	.irq_mask = mc_mask_intx_irq,
636 	.irq_unmask = mc_unmask_intx_irq,
637 };
638 
639 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
640 			    irq_hw_number_t hwirq)
641 {
642 	irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq);
643 	irq_set_chip_data(irq, domain->host_data);
644 
645 	return 0;
646 }
647 
648 static const struct irq_domain_ops intx_domain_ops = {
649 	.map = mc_pcie_intx_map,
650 };
651 
652 static inline u32 reg_to_event(u32 reg, struct event_map field)
653 {
654 	return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
655 }
656 
657 static u32 pcie_events(void __iomem *addr)
658 {
659 	u32 reg = readl_relaxed(addr);
660 	u32 val = 0;
661 	int i;
662 
663 	for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++)
664 		val |= reg_to_event(reg, pcie_event_to_event[i]);
665 
666 	return val;
667 }
668 
669 static u32 sec_errors(void __iomem *addr)
670 {
671 	u32 reg = readl_relaxed(addr);
672 	u32 val = 0;
673 	int i;
674 
675 	for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++)
676 		val |= reg_to_event(reg, sec_error_to_event[i]);
677 
678 	return val;
679 }
680 
681 static u32 ded_errors(void __iomem *addr)
682 {
683 	u32 reg = readl_relaxed(addr);
684 	u32 val = 0;
685 	int i;
686 
687 	for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++)
688 		val |= reg_to_event(reg, ded_error_to_event[i]);
689 
690 	return val;
691 }
692 
693 static u32 local_events(void __iomem *addr)
694 {
695 	u32 reg = readl_relaxed(addr);
696 	u32 val = 0;
697 	int i;
698 
699 	for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++)
700 		val |= reg_to_event(reg, local_status_to_event[i]);
701 
702 	return val;
703 }
704 
705 static u32 get_events(struct mc_port *port)
706 {
707 	void __iomem *bridge_base_addr =
708 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
709 	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
710 	u32 events = 0;
711 
712 	events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);
713 	events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);
714 	events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);
715 	events |= local_events(bridge_base_addr + ISTATUS_LOCAL);
716 
717 	return events;
718 }
719 
720 static irqreturn_t mc_event_handler(int irq, void *dev_id)
721 {
722 	struct mc_port *port = dev_id;
723 	struct device *dev = port->dev;
724 	struct irq_data *data;
725 
726 	data = irq_domain_get_irq_data(port->event_domain, irq);
727 
728 	if (event_cause[data->hwirq].str)
729 		dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);
730 	else
731 		dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);
732 
733 	return IRQ_HANDLED;
734 }
735 
736 static void mc_handle_event(struct irq_desc *desc)
737 {
738 	struct mc_port *port = irq_desc_get_handler_data(desc);
739 	unsigned long events;
740 	u32 bit;
741 	struct irq_chip *chip = irq_desc_get_chip(desc);
742 
743 	chained_irq_enter(chip, desc);
744 
745 	events = get_events(port);
746 
747 	for_each_set_bit(bit, &events, NUM_EVENTS)
748 		generic_handle_irq(irq_find_mapping(port->event_domain, bit));
749 
750 	chained_irq_exit(chip, desc);
751 }
752 
753 static void mc_ack_event_irq(struct irq_data *data)
754 {
755 	struct mc_port *port = irq_data_get_irq_chip_data(data);
756 	u32 event = data->hwirq;
757 	void __iomem *addr;
758 	u32 mask;
759 
760 	addr = port->axi_base_addr + event_descs[event].base +
761 		event_descs[event].offset;
762 	mask = event_descs[event].mask;
763 	mask |= event_descs[event].enb_mask;
764 
765 	writel_relaxed(mask, addr);
766 }
767 
768 static void mc_mask_event_irq(struct irq_data *data)
769 {
770 	struct mc_port *port = irq_data_get_irq_chip_data(data);
771 	u32 event = data->hwirq;
772 	void __iomem *addr;
773 	u32 mask;
774 	u32 val;
775 
776 	addr = port->axi_base_addr + event_descs[event].base +
777 		event_descs[event].mask_offset;
778 	mask = event_descs[event].mask;
779 	if (event_descs[event].enb_mask) {
780 		mask <<= PCIE_EVENT_INT_ENB_SHIFT;
781 		mask &= PCIE_EVENT_INT_ENB_MASK;
782 	}
783 
784 	if (!event_descs[event].mask_high)
785 		mask = ~mask;
786 
787 	raw_spin_lock(&port->lock);
788 	val = readl_relaxed(addr);
789 	if (event_descs[event].mask_high)
790 		val |= mask;
791 	else
792 		val &= mask;
793 
794 	writel_relaxed(val, addr);
795 	raw_spin_unlock(&port->lock);
796 }
797 
798 static void mc_unmask_event_irq(struct irq_data *data)
799 {
800 	struct mc_port *port = irq_data_get_irq_chip_data(data);
801 	u32 event = data->hwirq;
802 	void __iomem *addr;
803 	u32 mask;
804 	u32 val;
805 
806 	addr = port->axi_base_addr + event_descs[event].base +
807 		event_descs[event].mask_offset;
808 	mask = event_descs[event].mask;
809 
810 	if (event_descs[event].enb_mask)
811 		mask <<= PCIE_EVENT_INT_ENB_SHIFT;
812 
813 	if (event_descs[event].mask_high)
814 		mask = ~mask;
815 
816 	if (event_descs[event].enb_mask)
817 		mask &= PCIE_EVENT_INT_ENB_MASK;
818 
819 	raw_spin_lock(&port->lock);
820 	val = readl_relaxed(addr);
821 	if (event_descs[event].mask_high)
822 		val &= mask;
823 	else
824 		val |= mask;
825 	writel_relaxed(val, addr);
826 	raw_spin_unlock(&port->lock);
827 }
828 
829 static struct irq_chip mc_event_irq_chip = {
830 	.name = "Microchip PCIe EVENT",
831 	.irq_ack = mc_ack_event_irq,
832 	.irq_mask = mc_mask_event_irq,
833 	.irq_unmask = mc_unmask_event_irq,
834 };
835 
836 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq,
837 			     irq_hw_number_t hwirq)
838 {
839 	irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
840 	irq_set_chip_data(irq, domain->host_data);
841 
842 	return 0;
843 }
844 
845 static const struct irq_domain_ops event_domain_ops = {
846 	.map = mc_pcie_event_map,
847 };
848 
849 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id)
850 {
851 	struct clk *clk;
852 	int ret;
853 
854 	clk = devm_clk_get_optional(dev, id);
855 	if (IS_ERR(clk))
856 		return clk;
857 	if (!clk)
858 		return clk;
859 
860 	ret = clk_prepare_enable(clk);
861 	if (ret)
862 		return ERR_PTR(ret);
863 
864 	devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare,
865 				 clk);
866 
867 	return clk;
868 }
869 
870 static int mc_pcie_init_clks(struct device *dev)
871 {
872 	int i;
873 	struct clk *fic;
874 
875 	/*
876 	 * PCIe may be clocked via Fabric Interface using between 1 and 4
877 	 * clocks. Scan DT for clocks and enable them if present
878 	 */
879 	for (i = 0; i < ARRAY_SIZE(poss_clks); i++) {
880 		fic = mc_pcie_init_clk(dev, poss_clks[i]);
881 		if (IS_ERR(fic))
882 			return PTR_ERR(fic);
883 	}
884 
885 	return 0;
886 }
887 
888 static int mc_pcie_init_irq_domains(struct mc_port *port)
889 {
890 	struct device *dev = port->dev;
891 	struct device_node *node = dev->of_node;
892 	struct device_node *pcie_intc_node;
893 
894 	/* Setup INTx */
895 	pcie_intc_node = of_get_next_child(node, NULL);
896 	if (!pcie_intc_node) {
897 		dev_err(dev, "failed to find PCIe Intc node\n");
898 		return -EINVAL;
899 	}
900 
901 	port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS,
902 						   &event_domain_ops, port);
903 	if (!port->event_domain) {
904 		dev_err(dev, "failed to get event domain\n");
905 		return -ENOMEM;
906 	}
907 
908 	irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS);
909 
910 	port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
911 						  &intx_domain_ops, port);
912 	if (!port->intx_domain) {
913 		dev_err(dev, "failed to get an INTx IRQ domain\n");
914 		return -ENOMEM;
915 	}
916 
917 	irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
918 
919 	of_node_put(pcie_intc_node);
920 	raw_spin_lock_init(&port->lock);
921 
922 	return mc_allocate_msi_domains(port);
923 }
924 
925 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
926 				 phys_addr_t axi_addr, phys_addr_t pci_addr,
927 				 size_t size)
928 {
929 	u32 atr_sz = ilog2(size) - 1;
930 	u32 val;
931 
932 	if (index == 0)
933 		val = PCIE_CONFIG_INTERFACE;
934 	else
935 		val = PCIE_TX_RX_INTERFACE;
936 
937 	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
938 	       ATR0_AXI4_SLV0_TRSL_PARAM);
939 
940 	val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
941 			    ATR_IMPL_ENABLE;
942 	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
943 	       ATR0_AXI4_SLV0_SRCADDR_PARAM);
944 
945 	val = upper_32_bits(axi_addr);
946 	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
947 	       ATR0_AXI4_SLV0_SRC_ADDR);
948 
949 	val = lower_32_bits(pci_addr);
950 	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
951 	       ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
952 
953 	val = upper_32_bits(pci_addr);
954 	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
955 	       ATR0_AXI4_SLV0_TRSL_ADDR_UDW);
956 
957 	val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
958 	val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
959 	writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
960 	writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
961 }
962 
963 static int mc_pcie_setup_windows(struct platform_device *pdev,
964 				 struct mc_port *port)
965 {
966 	void __iomem *bridge_base_addr =
967 		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
968 	struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
969 	struct resource_entry *entry;
970 	u64 pci_addr;
971 	u32 index = 1;
972 
973 	resource_list_for_each_entry(entry, &bridge->windows) {
974 		if (resource_type(entry->res) == IORESOURCE_MEM) {
975 			pci_addr = entry->res->start - entry->offset;
976 			mc_pcie_setup_window(bridge_base_addr, index,
977 					     entry->res->start, pci_addr,
978 					     resource_size(entry->res));
979 			index++;
980 		}
981 	}
982 
983 	return 0;
984 }
985 
986 static int mc_platform_init(struct pci_config_window *cfg)
987 {
988 	struct device *dev = cfg->parent;
989 	struct platform_device *pdev = to_platform_device(dev);
990 	struct mc_port *port;
991 	void __iomem *bridge_base_addr;
992 	void __iomem *ctrl_base_addr;
993 	int ret;
994 	int irq;
995 	int i, intx_irq, msi_irq, event_irq;
996 	u32 val;
997 	int err;
998 
999 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1000 	if (!port)
1001 		return -ENOMEM;
1002 	port->dev = dev;
1003 
1004 	ret = mc_pcie_init_clks(dev);
1005 	if (ret) {
1006 		dev_err(dev, "failed to get clock resources, error %d\n", ret);
1007 		return -ENODEV;
1008 	}
1009 
1010 	port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
1011 	if (IS_ERR(port->axi_base_addr))
1012 		return PTR_ERR(port->axi_base_addr);
1013 
1014 	bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
1015 	ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
1016 
1017 	port->msi.vector_phy = MSI_ADDR;
1018 	port->msi.num_vectors = MC_NUM_MSI_IRQS;
1019 	ret = mc_pcie_init_irq_domains(port);
1020 	if (ret) {
1021 		dev_err(dev, "failed creating IRQ domains\n");
1022 		return ret;
1023 	}
1024 
1025 	irq = platform_get_irq(pdev, 0);
1026 	if (irq < 0)
1027 		return -ENODEV;
1028 
1029 	for (i = 0; i < NUM_EVENTS; i++) {
1030 		event_irq = irq_create_mapping(port->event_domain, i);
1031 		if (!event_irq) {
1032 			dev_err(dev, "failed to map hwirq %d\n", i);
1033 			return -ENXIO;
1034 		}
1035 
1036 		err = devm_request_irq(dev, event_irq, mc_event_handler,
1037 				       0, event_cause[i].sym, port);
1038 		if (err) {
1039 			dev_err(dev, "failed to request IRQ %d\n", event_irq);
1040 			return err;
1041 		}
1042 	}
1043 
1044 	intx_irq = irq_create_mapping(port->event_domain,
1045 				      EVENT_LOCAL_PM_MSI_INT_INTX);
1046 	if (!intx_irq) {
1047 		dev_err(dev, "failed to map INTx interrupt\n");
1048 		return -ENXIO;
1049 	}
1050 
1051 	/* Plug the INTx chained handler */
1052 	irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port);
1053 
1054 	msi_irq = irq_create_mapping(port->event_domain,
1055 				     EVENT_LOCAL_PM_MSI_INT_MSI);
1056 	if (!msi_irq)
1057 		return -ENXIO;
1058 
1059 	/* Plug the MSI chained handler */
1060 	irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port);
1061 
1062 	/* Plug the main event chained handler */
1063 	irq_set_chained_handler_and_data(irq, mc_handle_event, port);
1064 
1065 	/* Hardware doesn't setup MSI by default */
1066 	mc_pcie_enable_msi(port, cfg->win);
1067 
1068 	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
1069 	val |= PM_MSI_INT_INTX_MASK;
1070 	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
1071 
1072 	writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
1073 
1074 	val = PCIE_EVENT_INT_L2_EXIT_INT |
1075 	      PCIE_EVENT_INT_HOTRST_EXIT_INT |
1076 	      PCIE_EVENT_INT_DLUP_EXIT_INT;
1077 	writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
1078 
1079 	val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT |
1080 	      SEC_ERROR_INT_RX_RAM_SEC_ERR_INT |
1081 	      SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT |
1082 	      SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
1083 	writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
1084 	writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
1085 	writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
1086 
1087 	val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
1088 	      DED_ERROR_INT_RX_RAM_DED_ERR_INT |
1089 	      DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |
1090 	      DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
1091 	writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
1092 	writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
1093 	writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
1094 
1095 	writel_relaxed(0, bridge_base_addr + IMASK_HOST);
1096 	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
1097 
1098 	/* Configure Address Translation Table 0 for PCIe config space */
1099 	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
1100 			     cfg->res.start, resource_size(&cfg->res));
1101 
1102 	return mc_pcie_setup_windows(pdev, port);
1103 }
1104 
1105 static const struct pci_ecam_ops mc_ecam_ops = {
1106 	.init = mc_platform_init,
1107 	.pci_ops = {
1108 		.map_bus = pci_ecam_map_bus,
1109 		.read = pci_generic_config_read,
1110 		.write = pci_generic_config_write,
1111 	}
1112 };
1113 
1114 static const struct of_device_id mc_pcie_of_match[] = {
1115 	{
1116 		.compatible = "microchip,pcie-host-1.0",
1117 		.data = &mc_ecam_ops,
1118 	},
1119 	{},
1120 };
1121 
1122 MODULE_DEVICE_TABLE(of, mc_pcie_of_match)
1123 
1124 static struct platform_driver mc_pcie_driver = {
1125 	.probe = pci_host_common_probe,
1126 	.driver = {
1127 		.name = "microchip-pcie",
1128 		.of_match_table = mc_pcie_of_match,
1129 		.suppress_bind_attrs = true,
1130 	},
1131 };
1132 
1133 builtin_platform_driver(mc_pcie_driver);
1134 MODULE_LICENSE("GPL");
1135 MODULE_DESCRIPTION("Microchip PCIe host controller driver");
1136 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
1137