1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek PCIe host controller driver.
4  *
5  * Copyright (c) 2017 MediaTek Inc.
6  * Author: Ryder Lee <ryder.lee@mediatek.com>
7  *	   Honghui Zhang <honghui.zhang@mediatek.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27 
28 #include "../pci.h"
29 
30 /* PCIe shared registers */
31 #define PCIE_SYS_CFG		0x00
32 #define PCIE_INT_ENABLE		0x0c
33 #define PCIE_CFG_ADDR		0x20
34 #define PCIE_CFG_DATA		0x24
35 
36 /* PCIe per port registers */
37 #define PCIE_BAR0_SETUP		0x10
38 #define PCIE_CLASS		0x34
39 #define PCIE_LINK_STATUS	0x50
40 
41 #define PCIE_PORT_INT_EN(x)	BIT(20 + (x))
42 #define PCIE_PORT_PERST(x)	BIT(1 + (x))
43 #define PCIE_PORT_LINKUP	BIT(0)
44 #define PCIE_BAR_MAP_MAX	GENMASK(31, 16)
45 
46 #define PCIE_BAR_ENABLE		BIT(0)
47 #define PCIE_REVISION_ID	BIT(0)
48 #define PCIE_CLASS_CODE		(0x60400 << 8)
49 #define PCIE_CONF_REG(regn)	(((regn) & GENMASK(7, 2)) | \
50 				((((regn) >> 8) & GENMASK(3, 0)) << 24))
51 #define PCIE_CONF_FUN(fun)	(((fun) << 8) & GENMASK(10, 8))
52 #define PCIE_CONF_DEV(dev)	(((dev) << 11) & GENMASK(15, 11))
53 #define PCIE_CONF_BUS(bus)	(((bus) << 16) & GENMASK(23, 16))
54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 	(PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 	 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57 
58 /* MediaTek specific configuration registers */
59 #define PCIE_FTS_NUM		0x70c
60 #define PCIE_FTS_NUM_MASK	GENMASK(15, 8)
61 #define PCIE_FTS_NUM_L0(x)	((x) & 0xff << 8)
62 
63 #define PCIE_FC_CREDIT		0x73c
64 #define PCIE_FC_CREDIT_MASK	(GENMASK(31, 31) | GENMASK(28, 16))
65 #define PCIE_FC_CREDIT_VAL(x)	((x) << 16)
66 
67 /* PCIe V2 share registers */
68 #define PCIE_SYS_CFG_V2		0x0
69 #define PCIE_CSR_LTSSM_EN(x)	BIT(0 + (x) * 8)
70 #define PCIE_CSR_ASPM_L1_EN(x)	BIT(1 + (x) * 8)
71 
72 /* PCIe V2 per-port registers */
73 #define PCIE_MSI_VECTOR		0x0c0
74 
75 #define PCIE_CONF_VEND_ID	0x100
76 #define PCIE_CONF_DEVICE_ID	0x102
77 #define PCIE_CONF_CLASS_ID	0x106
78 
79 #define PCIE_INT_MASK		0x420
80 #define INTX_MASK		GENMASK(19, 16)
81 #define INTX_SHIFT		16
82 #define PCIE_INT_STATUS		0x424
83 #define MSI_STATUS		BIT(23)
84 #define PCIE_IMSI_STATUS	0x42c
85 #define PCIE_IMSI_ADDR		0x430
86 #define MSI_MASK		BIT(23)
87 #define MTK_MSI_IRQS_NUM	32
88 
89 #define PCIE_AHB_TRANS_BASE0_L	0x438
90 #define PCIE_AHB_TRANS_BASE0_H	0x43c
91 #define AHB2PCIE_SIZE(x)	((x) & GENMASK(4, 0))
92 #define PCIE_AXI_WINDOW0	0x448
93 #define WIN_ENABLE		BIT(7)
94 /*
95  * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96  * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97  * start from 0x40000000).
98  */
99 #define PCIE2AHB_SIZE	0x21
100 
101 /* PCIe V2 configuration transaction header */
102 #define PCIE_CFG_HEADER0	0x460
103 #define PCIE_CFG_HEADER1	0x464
104 #define PCIE_CFG_HEADER2	0x468
105 #define PCIE_CFG_WDATA		0x470
106 #define PCIE_APP_TLP_REQ	0x488
107 #define PCIE_CFG_RDATA		0x48c
108 #define APP_CFG_REQ		BIT(0)
109 #define APP_CPL_STATUS		GENMASK(7, 5)
110 
111 #define CFG_WRRD_TYPE_0		4
112 #define CFG_WR_FMT		2
113 #define CFG_RD_FMT		0
114 
115 #define CFG_DW0_LENGTH(length)	((length) & GENMASK(9, 0))
116 #define CFG_DW0_TYPE(type)	(((type) << 24) & GENMASK(28, 24))
117 #define CFG_DW0_FMT(fmt)	(((fmt) << 29) & GENMASK(31, 29))
118 #define CFG_DW2_REGN(regn)	((regn) & GENMASK(11, 2))
119 #define CFG_DW2_FUN(fun)	(((fun) << 16) & GENMASK(18, 16))
120 #define CFG_DW2_DEV(dev)	(((dev) << 19) & GENMASK(23, 19))
121 #define CFG_DW2_BUS(bus)	(((bus) << 24) & GENMASK(31, 24))
122 #define CFG_HEADER_DW0(type, fmt) \
123 	(CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124 #define CFG_HEADER_DW1(where, size) \
125 	(GENMASK(((size) - 1), 0) << ((where) & 0x3))
126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 	(CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 	CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
129 
130 #define PCIE_RST_CTRL		0x510
131 #define PCIE_PHY_RSTB		BIT(0)
132 #define PCIE_PIPE_SRSTB		BIT(1)
133 #define PCIE_MAC_SRSTB		BIT(2)
134 #define PCIE_CRSTB		BIT(3)
135 #define PCIE_PERSTB		BIT(8)
136 #define PCIE_LINKDOWN_RST_EN	GENMASK(15, 13)
137 #define PCIE_LINK_STATUS_V2	0x804
138 #define PCIE_PORT_LINKUP_V2	BIT(10)
139 
140 struct mtk_pcie_port;
141 
142 /**
143  * struct mtk_pcie_soc - differentiate between host generations
144  * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145  * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146  * @device_id: device ID which this host need to be fixed
147  * @ops: pointer to configuration access functions
148  * @startup: pointer to controller setting functions
149  * @setup_irq: pointer to initialize IRQ functions
150  */
151 struct mtk_pcie_soc {
152 	bool need_fix_class_id;
153 	bool need_fix_device_id;
154 	unsigned int device_id;
155 	struct pci_ops *ops;
156 	int (*startup)(struct mtk_pcie_port *port);
157 	int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
158 };
159 
160 /**
161  * struct mtk_pcie_port - PCIe port information
162  * @base: IO mapped register base
163  * @list: port list
164  * @pcie: pointer to PCIe host info
165  * @reset: pointer to port reset control
166  * @sys_ck: pointer to transaction/data link layer clock
167  * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
168  *          and RC initiated MMIO access
169  * @axi_ck: pointer to application layer MMIO channel operating clock
170  * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
171  *          when pcie_mac_ck/pcie_pipe_ck is turned off
172  * @obff_ck: pointer to OBFF functional block operating clock
173  * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
174  * @phy: pointer to PHY control block
175  * @slot: port slot
176  * @irq: GIC irq
177  * @irq_domain: legacy INTx IRQ domain
178  * @inner_domain: inner IRQ domain
179  * @msi_domain: MSI IRQ domain
180  * @lock: protect the msi_irq_in_use bitmap
181  * @msi_irq_in_use: bit map for assigned MSI IRQ
182  */
183 struct mtk_pcie_port {
184 	void __iomem *base;
185 	struct list_head list;
186 	struct mtk_pcie *pcie;
187 	struct reset_control *reset;
188 	struct clk *sys_ck;
189 	struct clk *ahb_ck;
190 	struct clk *axi_ck;
191 	struct clk *aux_ck;
192 	struct clk *obff_ck;
193 	struct clk *pipe_ck;
194 	struct phy *phy;
195 	u32 slot;
196 	int irq;
197 	struct irq_domain *irq_domain;
198 	struct irq_domain *inner_domain;
199 	struct irq_domain *msi_domain;
200 	struct mutex lock;
201 	DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
202 };
203 
204 /**
205  * struct mtk_pcie - PCIe host information
206  * @dev: pointer to PCIe device
207  * @base: IO mapped register base
208  * @free_ck: free-run reference clock
209  * @mem: non-prefetchable memory resource
210  * @ports: pointer to PCIe port information
211  * @soc: pointer to SoC-dependent operations
212  */
213 struct mtk_pcie {
214 	struct device *dev;
215 	void __iomem *base;
216 	struct clk *free_ck;
217 
218 	struct list_head ports;
219 	const struct mtk_pcie_soc *soc;
220 };
221 
222 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
223 {
224 	struct device *dev = pcie->dev;
225 
226 	clk_disable_unprepare(pcie->free_ck);
227 
228 	pm_runtime_put_sync(dev);
229 	pm_runtime_disable(dev);
230 }
231 
232 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
233 {
234 	struct mtk_pcie *pcie = port->pcie;
235 	struct device *dev = pcie->dev;
236 
237 	devm_iounmap(dev, port->base);
238 	list_del(&port->list);
239 	devm_kfree(dev, port);
240 }
241 
242 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
243 {
244 	struct mtk_pcie_port *port, *tmp;
245 
246 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
247 		phy_power_off(port->phy);
248 		phy_exit(port->phy);
249 		clk_disable_unprepare(port->pipe_ck);
250 		clk_disable_unprepare(port->obff_ck);
251 		clk_disable_unprepare(port->axi_ck);
252 		clk_disable_unprepare(port->aux_ck);
253 		clk_disable_unprepare(port->ahb_ck);
254 		clk_disable_unprepare(port->sys_ck);
255 		mtk_pcie_port_free(port);
256 	}
257 
258 	mtk_pcie_subsys_powerdown(pcie);
259 }
260 
261 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
262 {
263 	u32 val;
264 	int err;
265 
266 	err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
267 					!(val & APP_CFG_REQ), 10,
268 					100 * USEC_PER_MSEC);
269 	if (err)
270 		return PCIBIOS_SET_FAILED;
271 
272 	if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
273 		return PCIBIOS_SET_FAILED;
274 
275 	return PCIBIOS_SUCCESSFUL;
276 }
277 
278 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
279 			      int where, int size, u32 *val)
280 {
281 	u32 tmp;
282 
283 	/* Write PCIe configuration transaction header for Cfgrd */
284 	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
285 	       port->base + PCIE_CFG_HEADER0);
286 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
287 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
288 	       port->base + PCIE_CFG_HEADER2);
289 
290 	/* Trigger h/w to transmit Cfgrd TLP */
291 	tmp = readl(port->base + PCIE_APP_TLP_REQ);
292 	tmp |= APP_CFG_REQ;
293 	writel(tmp, port->base + PCIE_APP_TLP_REQ);
294 
295 	/* Check completion status */
296 	if (mtk_pcie_check_cfg_cpld(port))
297 		return PCIBIOS_SET_FAILED;
298 
299 	/* Read cpld payload of Cfgrd */
300 	*val = readl(port->base + PCIE_CFG_RDATA);
301 
302 	if (size == 1)
303 		*val = (*val >> (8 * (where & 3))) & 0xff;
304 	else if (size == 2)
305 		*val = (*val >> (8 * (where & 3))) & 0xffff;
306 
307 	return PCIBIOS_SUCCESSFUL;
308 }
309 
310 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
311 			      int where, int size, u32 val)
312 {
313 	/* Write PCIe configuration transaction header for Cfgwr */
314 	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
315 	       port->base + PCIE_CFG_HEADER0);
316 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
317 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
318 	       port->base + PCIE_CFG_HEADER2);
319 
320 	/* Write Cfgwr data */
321 	val = val << 8 * (where & 3);
322 	writel(val, port->base + PCIE_CFG_WDATA);
323 
324 	/* Trigger h/w to transmit Cfgwr TLP */
325 	val = readl(port->base + PCIE_APP_TLP_REQ);
326 	val |= APP_CFG_REQ;
327 	writel(val, port->base + PCIE_APP_TLP_REQ);
328 
329 	/* Check completion status */
330 	return mtk_pcie_check_cfg_cpld(port);
331 }
332 
333 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
334 						unsigned int devfn)
335 {
336 	struct mtk_pcie *pcie = bus->sysdata;
337 	struct mtk_pcie_port *port;
338 	struct pci_dev *dev = NULL;
339 
340 	/*
341 	 * Walk the bus hierarchy to get the devfn value
342 	 * of the port in the root bus.
343 	 */
344 	while (bus && bus->number) {
345 		dev = bus->self;
346 		bus = dev->bus;
347 		devfn = dev->devfn;
348 	}
349 
350 	list_for_each_entry(port, &pcie->ports, list)
351 		if (port->slot == PCI_SLOT(devfn))
352 			return port;
353 
354 	return NULL;
355 }
356 
357 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
358 				int where, int size, u32 *val)
359 {
360 	struct mtk_pcie_port *port;
361 	u32 bn = bus->number;
362 	int ret;
363 
364 	port = mtk_pcie_find_port(bus, devfn);
365 	if (!port) {
366 		*val = ~0;
367 		return PCIBIOS_DEVICE_NOT_FOUND;
368 	}
369 
370 	ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
371 	if (ret)
372 		*val = ~0;
373 
374 	return ret;
375 }
376 
377 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
378 				 int where, int size, u32 val)
379 {
380 	struct mtk_pcie_port *port;
381 	u32 bn = bus->number;
382 
383 	port = mtk_pcie_find_port(bus, devfn);
384 	if (!port)
385 		return PCIBIOS_DEVICE_NOT_FOUND;
386 
387 	return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
388 }
389 
390 static struct pci_ops mtk_pcie_ops_v2 = {
391 	.read  = mtk_pcie_config_read,
392 	.write = mtk_pcie_config_write,
393 };
394 
395 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
396 {
397 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
398 	phys_addr_t addr;
399 
400 	/* MT2712/MT7622 only support 32-bit MSI addresses */
401 	addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
402 	msg->address_hi = 0;
403 	msg->address_lo = lower_32_bits(addr);
404 
405 	msg->data = data->hwirq;
406 
407 	dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
408 		(int)data->hwirq, msg->address_hi, msg->address_lo);
409 }
410 
411 static int mtk_msi_set_affinity(struct irq_data *irq_data,
412 				const struct cpumask *mask, bool force)
413 {
414 	 return -EINVAL;
415 }
416 
417 static void mtk_msi_ack_irq(struct irq_data *data)
418 {
419 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
420 	u32 hwirq = data->hwirq;
421 
422 	writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
423 }
424 
425 static struct irq_chip mtk_msi_bottom_irq_chip = {
426 	.name			= "MTK MSI",
427 	.irq_compose_msi_msg	= mtk_compose_msi_msg,
428 	.irq_set_affinity	= mtk_msi_set_affinity,
429 	.irq_ack		= mtk_msi_ack_irq,
430 };
431 
432 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
433 				     unsigned int nr_irqs, void *args)
434 {
435 	struct mtk_pcie_port *port = domain->host_data;
436 	unsigned long bit;
437 
438 	WARN_ON(nr_irqs != 1);
439 	mutex_lock(&port->lock);
440 
441 	bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
442 	if (bit >= MTK_MSI_IRQS_NUM) {
443 		mutex_unlock(&port->lock);
444 		return -ENOSPC;
445 	}
446 
447 	__set_bit(bit, port->msi_irq_in_use);
448 
449 	mutex_unlock(&port->lock);
450 
451 	irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
452 			    domain->host_data, handle_edge_irq,
453 			    NULL, NULL);
454 
455 	return 0;
456 }
457 
458 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
459 				     unsigned int virq, unsigned int nr_irqs)
460 {
461 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
462 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
463 
464 	mutex_lock(&port->lock);
465 
466 	if (!test_bit(d->hwirq, port->msi_irq_in_use))
467 		dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
468 			d->hwirq);
469 	else
470 		__clear_bit(d->hwirq, port->msi_irq_in_use);
471 
472 	mutex_unlock(&port->lock);
473 
474 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
475 }
476 
477 static const struct irq_domain_ops msi_domain_ops = {
478 	.alloc	= mtk_pcie_irq_domain_alloc,
479 	.free	= mtk_pcie_irq_domain_free,
480 };
481 
482 static struct irq_chip mtk_msi_irq_chip = {
483 	.name		= "MTK PCIe MSI",
484 	.irq_ack	= irq_chip_ack_parent,
485 	.irq_mask	= pci_msi_mask_irq,
486 	.irq_unmask	= pci_msi_unmask_irq,
487 };
488 
489 static struct msi_domain_info mtk_msi_domain_info = {
490 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
491 		   MSI_FLAG_PCI_MSIX),
492 	.chip	= &mtk_msi_irq_chip,
493 };
494 
495 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
496 {
497 	struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
498 
499 	mutex_init(&port->lock);
500 
501 	port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
502 						      &msi_domain_ops, port);
503 	if (!port->inner_domain) {
504 		dev_err(port->pcie->dev, "failed to create IRQ domain\n");
505 		return -ENOMEM;
506 	}
507 
508 	port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
509 						     port->inner_domain);
510 	if (!port->msi_domain) {
511 		dev_err(port->pcie->dev, "failed to create MSI domain\n");
512 		irq_domain_remove(port->inner_domain);
513 		return -ENOMEM;
514 	}
515 
516 	return 0;
517 }
518 
519 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
520 {
521 	u32 val;
522 	phys_addr_t msg_addr;
523 
524 	msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
525 	val = lower_32_bits(msg_addr);
526 	writel(val, port->base + PCIE_IMSI_ADDR);
527 
528 	val = readl(port->base + PCIE_INT_MASK);
529 	val &= ~MSI_MASK;
530 	writel(val, port->base + PCIE_INT_MASK);
531 }
532 
533 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
534 {
535 	struct mtk_pcie_port *port, *tmp;
536 
537 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
538 		irq_set_chained_handler_and_data(port->irq, NULL, NULL);
539 
540 		if (port->irq_domain)
541 			irq_domain_remove(port->irq_domain);
542 
543 		if (IS_ENABLED(CONFIG_PCI_MSI)) {
544 			if (port->msi_domain)
545 				irq_domain_remove(port->msi_domain);
546 			if (port->inner_domain)
547 				irq_domain_remove(port->inner_domain);
548 		}
549 
550 		irq_dispose_mapping(port->irq);
551 	}
552 }
553 
554 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
555 			     irq_hw_number_t hwirq)
556 {
557 	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
558 	irq_set_chip_data(irq, domain->host_data);
559 
560 	return 0;
561 }
562 
563 static const struct irq_domain_ops intx_domain_ops = {
564 	.map = mtk_pcie_intx_map,
565 };
566 
567 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
568 				    struct device_node *node)
569 {
570 	struct device *dev = port->pcie->dev;
571 	struct device_node *pcie_intc_node;
572 	int ret;
573 
574 	/* Setup INTx */
575 	pcie_intc_node = of_get_next_child(node, NULL);
576 	if (!pcie_intc_node) {
577 		dev_err(dev, "no PCIe Intc node found\n");
578 		return -ENODEV;
579 	}
580 
581 	port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
582 						 &intx_domain_ops, port);
583 	of_node_put(pcie_intc_node);
584 	if (!port->irq_domain) {
585 		dev_err(dev, "failed to get INTx IRQ domain\n");
586 		return -ENODEV;
587 	}
588 
589 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
590 		ret = mtk_pcie_allocate_msi_domains(port);
591 		if (ret)
592 			return ret;
593 	}
594 
595 	return 0;
596 }
597 
598 static void mtk_pcie_intr_handler(struct irq_desc *desc)
599 {
600 	struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
601 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
602 	unsigned long status;
603 	u32 virq;
604 	u32 bit = INTX_SHIFT;
605 
606 	chained_irq_enter(irqchip, desc);
607 
608 	status = readl(port->base + PCIE_INT_STATUS);
609 	if (status & INTX_MASK) {
610 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
611 			/* Clear the INTx */
612 			writel(1 << bit, port->base + PCIE_INT_STATUS);
613 			virq = irq_find_mapping(port->irq_domain,
614 						bit - INTX_SHIFT);
615 			generic_handle_irq(virq);
616 		}
617 	}
618 
619 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
620 		if (status & MSI_STATUS){
621 			unsigned long imsi_status;
622 
623 			while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
624 				for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
625 					virq = irq_find_mapping(port->inner_domain, bit);
626 					generic_handle_irq(virq);
627 				}
628 			}
629 			/* Clear MSI interrupt status */
630 			writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
631 		}
632 	}
633 
634 	chained_irq_exit(irqchip, desc);
635 }
636 
637 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
638 			      struct device_node *node)
639 {
640 	struct mtk_pcie *pcie = port->pcie;
641 	struct device *dev = pcie->dev;
642 	struct platform_device *pdev = to_platform_device(dev);
643 	int err;
644 
645 	err = mtk_pcie_init_irq_domain(port, node);
646 	if (err) {
647 		dev_err(dev, "failed to init PCIe IRQ domain\n");
648 		return err;
649 	}
650 
651 	port->irq = platform_get_irq(pdev, port->slot);
652 	if (port->irq < 0)
653 		return port->irq;
654 
655 	irq_set_chained_handler_and_data(port->irq,
656 					 mtk_pcie_intr_handler, port);
657 
658 	return 0;
659 }
660 
661 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
662 {
663 	struct mtk_pcie *pcie = port->pcie;
664 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
665 	struct resource *mem = NULL;
666 	struct resource_entry *entry;
667 	const struct mtk_pcie_soc *soc = port->pcie->soc;
668 	u32 val;
669 	int err;
670 
671 	entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
672 	if (entry)
673 		mem = entry->res;
674 	if (!mem)
675 		return -EINVAL;
676 
677 	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
678 	if (pcie->base) {
679 		val = readl(pcie->base + PCIE_SYS_CFG_V2);
680 		val |= PCIE_CSR_LTSSM_EN(port->slot) |
681 		       PCIE_CSR_ASPM_L1_EN(port->slot);
682 		writel(val, pcie->base + PCIE_SYS_CFG_V2);
683 	}
684 
685 	/* Assert all reset signals */
686 	writel(0, port->base + PCIE_RST_CTRL);
687 
688 	/*
689 	 * Enable PCIe link down reset, if link status changed from link up to
690 	 * link down, this will reset MAC control registers and configuration
691 	 * space.
692 	 */
693 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
694 
695 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
696 	val = readl(port->base + PCIE_RST_CTRL);
697 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
698 	       PCIE_MAC_SRSTB | PCIE_CRSTB;
699 	writel(val, port->base + PCIE_RST_CTRL);
700 
701 	/* Set up vendor ID and class code */
702 	if (soc->need_fix_class_id) {
703 		val = PCI_VENDOR_ID_MEDIATEK;
704 		writew(val, port->base + PCIE_CONF_VEND_ID);
705 
706 		val = PCI_CLASS_BRIDGE_PCI;
707 		writew(val, port->base + PCIE_CONF_CLASS_ID);
708 	}
709 
710 	if (soc->need_fix_device_id)
711 		writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
712 
713 	/* 100ms timeout value should be enough for Gen1/2 training */
714 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
715 				 !!(val & PCIE_PORT_LINKUP_V2), 20,
716 				 100 * USEC_PER_MSEC);
717 	if (err)
718 		return -ETIMEDOUT;
719 
720 	/* Set INTx mask */
721 	val = readl(port->base + PCIE_INT_MASK);
722 	val &= ~INTX_MASK;
723 	writel(val, port->base + PCIE_INT_MASK);
724 
725 	if (IS_ENABLED(CONFIG_PCI_MSI))
726 		mtk_pcie_enable_msi(port);
727 
728 	/* Set AHB to PCIe translation windows */
729 	val = lower_32_bits(mem->start) |
730 	      AHB2PCIE_SIZE(fls(resource_size(mem)));
731 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
732 
733 	val = upper_32_bits(mem->start);
734 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
735 
736 	/* Set PCIe to AXI translation memory space.*/
737 	val = PCIE2AHB_SIZE | WIN_ENABLE;
738 	writel(val, port->base + PCIE_AXI_WINDOW0);
739 
740 	return 0;
741 }
742 
743 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
744 				      unsigned int devfn, int where)
745 {
746 	struct mtk_pcie *pcie = bus->sysdata;
747 
748 	writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
749 			      bus->number), pcie->base + PCIE_CFG_ADDR);
750 
751 	return pcie->base + PCIE_CFG_DATA + (where & 3);
752 }
753 
754 static struct pci_ops mtk_pcie_ops = {
755 	.map_bus = mtk_pcie_map_bus,
756 	.read  = pci_generic_config_read,
757 	.write = pci_generic_config_write,
758 };
759 
760 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
761 {
762 	struct mtk_pcie *pcie = port->pcie;
763 	u32 func = PCI_FUNC(port->slot << 3);
764 	u32 slot = PCI_SLOT(port->slot << 3);
765 	u32 val;
766 	int err;
767 
768 	/* assert port PERST_N */
769 	val = readl(pcie->base + PCIE_SYS_CFG);
770 	val |= PCIE_PORT_PERST(port->slot);
771 	writel(val, pcie->base + PCIE_SYS_CFG);
772 
773 	/* de-assert port PERST_N */
774 	val = readl(pcie->base + PCIE_SYS_CFG);
775 	val &= ~PCIE_PORT_PERST(port->slot);
776 	writel(val, pcie->base + PCIE_SYS_CFG);
777 
778 	/* 100ms timeout value should be enough for Gen1/2 training */
779 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
780 				 !!(val & PCIE_PORT_LINKUP), 20,
781 				 100 * USEC_PER_MSEC);
782 	if (err)
783 		return -ETIMEDOUT;
784 
785 	/* enable interrupt */
786 	val = readl(pcie->base + PCIE_INT_ENABLE);
787 	val |= PCIE_PORT_INT_EN(port->slot);
788 	writel(val, pcie->base + PCIE_INT_ENABLE);
789 
790 	/* map to all DDR region. We need to set it before cfg operation. */
791 	writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
792 	       port->base + PCIE_BAR0_SETUP);
793 
794 	/* configure class code and revision ID */
795 	writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
796 
797 	/* configure FC credit */
798 	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
799 	       pcie->base + PCIE_CFG_ADDR);
800 	val = readl(pcie->base + PCIE_CFG_DATA);
801 	val &= ~PCIE_FC_CREDIT_MASK;
802 	val |= PCIE_FC_CREDIT_VAL(0x806c);
803 	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
804 	       pcie->base + PCIE_CFG_ADDR);
805 	writel(val, pcie->base + PCIE_CFG_DATA);
806 
807 	/* configure RC FTS number to 250 when it leaves L0s */
808 	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
809 	       pcie->base + PCIE_CFG_ADDR);
810 	val = readl(pcie->base + PCIE_CFG_DATA);
811 	val &= ~PCIE_FTS_NUM_MASK;
812 	val |= PCIE_FTS_NUM_L0(0x50);
813 	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
814 	       pcie->base + PCIE_CFG_ADDR);
815 	writel(val, pcie->base + PCIE_CFG_DATA);
816 
817 	return 0;
818 }
819 
820 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
821 {
822 	struct mtk_pcie *pcie = port->pcie;
823 	struct device *dev = pcie->dev;
824 	int err;
825 
826 	err = clk_prepare_enable(port->sys_ck);
827 	if (err) {
828 		dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
829 		goto err_sys_clk;
830 	}
831 
832 	err = clk_prepare_enable(port->ahb_ck);
833 	if (err) {
834 		dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
835 		goto err_ahb_clk;
836 	}
837 
838 	err = clk_prepare_enable(port->aux_ck);
839 	if (err) {
840 		dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
841 		goto err_aux_clk;
842 	}
843 
844 	err = clk_prepare_enable(port->axi_ck);
845 	if (err) {
846 		dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
847 		goto err_axi_clk;
848 	}
849 
850 	err = clk_prepare_enable(port->obff_ck);
851 	if (err) {
852 		dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
853 		goto err_obff_clk;
854 	}
855 
856 	err = clk_prepare_enable(port->pipe_ck);
857 	if (err) {
858 		dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
859 		goto err_pipe_clk;
860 	}
861 
862 	reset_control_assert(port->reset);
863 	reset_control_deassert(port->reset);
864 
865 	err = phy_init(port->phy);
866 	if (err) {
867 		dev_err(dev, "failed to initialize port%d phy\n", port->slot);
868 		goto err_phy_init;
869 	}
870 
871 	err = phy_power_on(port->phy);
872 	if (err) {
873 		dev_err(dev, "failed to power on port%d phy\n", port->slot);
874 		goto err_phy_on;
875 	}
876 
877 	if (!pcie->soc->startup(port))
878 		return;
879 
880 	dev_info(dev, "Port%d link down\n", port->slot);
881 
882 	phy_power_off(port->phy);
883 err_phy_on:
884 	phy_exit(port->phy);
885 err_phy_init:
886 	clk_disable_unprepare(port->pipe_ck);
887 err_pipe_clk:
888 	clk_disable_unprepare(port->obff_ck);
889 err_obff_clk:
890 	clk_disable_unprepare(port->axi_ck);
891 err_axi_clk:
892 	clk_disable_unprepare(port->aux_ck);
893 err_aux_clk:
894 	clk_disable_unprepare(port->ahb_ck);
895 err_ahb_clk:
896 	clk_disable_unprepare(port->sys_ck);
897 err_sys_clk:
898 	mtk_pcie_port_free(port);
899 }
900 
901 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
902 			       struct device_node *node,
903 			       int slot)
904 {
905 	struct mtk_pcie_port *port;
906 	struct device *dev = pcie->dev;
907 	struct platform_device *pdev = to_platform_device(dev);
908 	char name[10];
909 	int err;
910 
911 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
912 	if (!port)
913 		return -ENOMEM;
914 
915 	snprintf(name, sizeof(name), "port%d", slot);
916 	port->base = devm_platform_ioremap_resource_byname(pdev, name);
917 	if (IS_ERR(port->base)) {
918 		dev_err(dev, "failed to map port%d base\n", slot);
919 		return PTR_ERR(port->base);
920 	}
921 
922 	snprintf(name, sizeof(name), "sys_ck%d", slot);
923 	port->sys_ck = devm_clk_get(dev, name);
924 	if (IS_ERR(port->sys_ck)) {
925 		dev_err(dev, "failed to get sys_ck%d clock\n", slot);
926 		return PTR_ERR(port->sys_ck);
927 	}
928 
929 	/* sys_ck might be divided into the following parts in some chips */
930 	snprintf(name, sizeof(name), "ahb_ck%d", slot);
931 	port->ahb_ck = devm_clk_get_optional(dev, name);
932 	if (IS_ERR(port->ahb_ck))
933 		return PTR_ERR(port->ahb_ck);
934 
935 	snprintf(name, sizeof(name), "axi_ck%d", slot);
936 	port->axi_ck = devm_clk_get_optional(dev, name);
937 	if (IS_ERR(port->axi_ck))
938 		return PTR_ERR(port->axi_ck);
939 
940 	snprintf(name, sizeof(name), "aux_ck%d", slot);
941 	port->aux_ck = devm_clk_get_optional(dev, name);
942 	if (IS_ERR(port->aux_ck))
943 		return PTR_ERR(port->aux_ck);
944 
945 	snprintf(name, sizeof(name), "obff_ck%d", slot);
946 	port->obff_ck = devm_clk_get_optional(dev, name);
947 	if (IS_ERR(port->obff_ck))
948 		return PTR_ERR(port->obff_ck);
949 
950 	snprintf(name, sizeof(name), "pipe_ck%d", slot);
951 	port->pipe_ck = devm_clk_get_optional(dev, name);
952 	if (IS_ERR(port->pipe_ck))
953 		return PTR_ERR(port->pipe_ck);
954 
955 	snprintf(name, sizeof(name), "pcie-rst%d", slot);
956 	port->reset = devm_reset_control_get_optional_exclusive(dev, name);
957 	if (PTR_ERR(port->reset) == -EPROBE_DEFER)
958 		return PTR_ERR(port->reset);
959 
960 	/* some platforms may use default PHY setting */
961 	snprintf(name, sizeof(name), "pcie-phy%d", slot);
962 	port->phy = devm_phy_optional_get(dev, name);
963 	if (IS_ERR(port->phy))
964 		return PTR_ERR(port->phy);
965 
966 	port->slot = slot;
967 	port->pcie = pcie;
968 
969 	if (pcie->soc->setup_irq) {
970 		err = pcie->soc->setup_irq(port, node);
971 		if (err)
972 			return err;
973 	}
974 
975 	INIT_LIST_HEAD(&port->list);
976 	list_add_tail(&port->list, &pcie->ports);
977 
978 	return 0;
979 }
980 
981 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
982 {
983 	struct device *dev = pcie->dev;
984 	struct platform_device *pdev = to_platform_device(dev);
985 	struct resource *regs;
986 	int err;
987 
988 	/* get shared registers, which are optional */
989 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
990 	if (regs) {
991 		pcie->base = devm_ioremap_resource(dev, regs);
992 		if (IS_ERR(pcie->base)) {
993 			dev_err(dev, "failed to map shared register\n");
994 			return PTR_ERR(pcie->base);
995 		}
996 	}
997 
998 	pcie->free_ck = devm_clk_get(dev, "free_ck");
999 	if (IS_ERR(pcie->free_ck)) {
1000 		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1001 			return -EPROBE_DEFER;
1002 
1003 		pcie->free_ck = NULL;
1004 	}
1005 
1006 	pm_runtime_enable(dev);
1007 	pm_runtime_get_sync(dev);
1008 
1009 	/* enable top level clock */
1010 	err = clk_prepare_enable(pcie->free_ck);
1011 	if (err) {
1012 		dev_err(dev, "failed to enable free_ck\n");
1013 		goto err_free_ck;
1014 	}
1015 
1016 	return 0;
1017 
1018 err_free_ck:
1019 	pm_runtime_put_sync(dev);
1020 	pm_runtime_disable(dev);
1021 
1022 	return err;
1023 }
1024 
1025 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1026 {
1027 	struct device *dev = pcie->dev;
1028 	struct device_node *node = dev->of_node, *child;
1029 	struct mtk_pcie_port *port, *tmp;
1030 	int err;
1031 
1032 	for_each_available_child_of_node(node, child) {
1033 		int slot;
1034 
1035 		err = of_pci_get_devfn(child);
1036 		if (err < 0) {
1037 			dev_err(dev, "failed to parse devfn: %d\n", err);
1038 			return err;
1039 		}
1040 
1041 		slot = PCI_SLOT(err);
1042 
1043 		err = mtk_pcie_parse_port(pcie, child, slot);
1044 		if (err)
1045 			return err;
1046 	}
1047 
1048 	err = mtk_pcie_subsys_powerup(pcie);
1049 	if (err)
1050 		return err;
1051 
1052 	/* enable each port, and then check link status */
1053 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1054 		mtk_pcie_enable_port(port);
1055 
1056 	/* power down PCIe subsys if slots are all empty (link down) */
1057 	if (list_empty(&pcie->ports))
1058 		mtk_pcie_subsys_powerdown(pcie);
1059 
1060 	return 0;
1061 }
1062 
1063 static int mtk_pcie_probe(struct platform_device *pdev)
1064 {
1065 	struct device *dev = &pdev->dev;
1066 	struct mtk_pcie *pcie;
1067 	struct pci_host_bridge *host;
1068 	int err;
1069 
1070 	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1071 	if (!host)
1072 		return -ENOMEM;
1073 
1074 	pcie = pci_host_bridge_priv(host);
1075 
1076 	pcie->dev = dev;
1077 	pcie->soc = of_device_get_match_data(dev);
1078 	platform_set_drvdata(pdev, pcie);
1079 	INIT_LIST_HEAD(&pcie->ports);
1080 
1081 	err = mtk_pcie_setup(pcie);
1082 	if (err)
1083 		return err;
1084 
1085 	host->ops = pcie->soc->ops;
1086 	host->sysdata = pcie;
1087 
1088 	err = pci_host_probe(host);
1089 	if (err)
1090 		goto put_resources;
1091 
1092 	return 0;
1093 
1094 put_resources:
1095 	if (!list_empty(&pcie->ports))
1096 		mtk_pcie_put_resources(pcie);
1097 
1098 	return err;
1099 }
1100 
1101 
1102 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1103 {
1104 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1105 	struct list_head *windows = &host->windows;
1106 
1107 	pci_free_resource_list(windows);
1108 }
1109 
1110 static int mtk_pcie_remove(struct platform_device *pdev)
1111 {
1112 	struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1113 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1114 
1115 	pci_stop_root_bus(host->bus);
1116 	pci_remove_root_bus(host->bus);
1117 	mtk_pcie_free_resources(pcie);
1118 
1119 	mtk_pcie_irq_teardown(pcie);
1120 
1121 	mtk_pcie_put_resources(pcie);
1122 
1123 	return 0;
1124 }
1125 
1126 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1127 {
1128 	struct mtk_pcie *pcie = dev_get_drvdata(dev);
1129 	struct mtk_pcie_port *port;
1130 
1131 	if (list_empty(&pcie->ports))
1132 		return 0;
1133 
1134 	list_for_each_entry(port, &pcie->ports, list) {
1135 		clk_disable_unprepare(port->pipe_ck);
1136 		clk_disable_unprepare(port->obff_ck);
1137 		clk_disable_unprepare(port->axi_ck);
1138 		clk_disable_unprepare(port->aux_ck);
1139 		clk_disable_unprepare(port->ahb_ck);
1140 		clk_disable_unprepare(port->sys_ck);
1141 		phy_power_off(port->phy);
1142 		phy_exit(port->phy);
1143 	}
1144 
1145 	clk_disable_unprepare(pcie->free_ck);
1146 
1147 	return 0;
1148 }
1149 
1150 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1151 {
1152 	struct mtk_pcie *pcie = dev_get_drvdata(dev);
1153 	struct mtk_pcie_port *port, *tmp;
1154 
1155 	if (list_empty(&pcie->ports))
1156 		return 0;
1157 
1158 	clk_prepare_enable(pcie->free_ck);
1159 
1160 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1161 		mtk_pcie_enable_port(port);
1162 
1163 	/* In case of EP was removed while system suspend. */
1164 	if (list_empty(&pcie->ports))
1165 		clk_disable_unprepare(pcie->free_ck);
1166 
1167 	return 0;
1168 }
1169 
1170 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1171 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1172 				      mtk_pcie_resume_noirq)
1173 };
1174 
1175 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1176 	.ops = &mtk_pcie_ops,
1177 	.startup = mtk_pcie_startup_port,
1178 };
1179 
1180 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1181 	.ops = &mtk_pcie_ops_v2,
1182 	.startup = mtk_pcie_startup_port_v2,
1183 	.setup_irq = mtk_pcie_setup_irq,
1184 };
1185 
1186 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1187 	.need_fix_class_id = true,
1188 	.ops = &mtk_pcie_ops_v2,
1189 	.startup = mtk_pcie_startup_port_v2,
1190 	.setup_irq = mtk_pcie_setup_irq,
1191 };
1192 
1193 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1194 	.need_fix_class_id = true,
1195 	.need_fix_device_id = true,
1196 	.device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1197 	.ops = &mtk_pcie_ops_v2,
1198 	.startup = mtk_pcie_startup_port_v2,
1199 	.setup_irq = mtk_pcie_setup_irq,
1200 };
1201 
1202 static const struct of_device_id mtk_pcie_ids[] = {
1203 	{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1204 	{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1205 	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1206 	{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1207 	{ .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1208 	{},
1209 };
1210 
1211 static struct platform_driver mtk_pcie_driver = {
1212 	.probe = mtk_pcie_probe,
1213 	.remove = mtk_pcie_remove,
1214 	.driver = {
1215 		.name = "mtk-pcie",
1216 		.of_match_table = mtk_pcie_ids,
1217 		.suppress_bind_attrs = true,
1218 		.pm = &mtk_pcie_pm_ops,
1219 	},
1220 };
1221 module_platform_driver(mtk_pcie_driver);
1222 MODULE_LICENSE("GPL v2");
1223