1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek PCIe host controller driver.
4  *
5  * Copyright (c) 2017 MediaTek Inc.
6  * Author: Ryder Lee <ryder.lee@mediatek.com>
7  *	   Honghui Zhang <honghui.zhang@mediatek.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27 
28 #include "../pci.h"
29 
30 /* PCIe shared registers */
31 #define PCIE_SYS_CFG		0x00
32 #define PCIE_INT_ENABLE		0x0c
33 #define PCIE_CFG_ADDR		0x20
34 #define PCIE_CFG_DATA		0x24
35 
36 /* PCIe per port registers */
37 #define PCIE_BAR0_SETUP		0x10
38 #define PCIE_CLASS		0x34
39 #define PCIE_LINK_STATUS	0x50
40 
41 #define PCIE_PORT_INT_EN(x)	BIT(20 + (x))
42 #define PCIE_PORT_PERST(x)	BIT(1 + (x))
43 #define PCIE_PORT_LINKUP	BIT(0)
44 #define PCIE_BAR_MAP_MAX	GENMASK(31, 16)
45 
46 #define PCIE_BAR_ENABLE		BIT(0)
47 #define PCIE_REVISION_ID	BIT(0)
48 #define PCIE_CLASS_CODE		(0x60400 << 8)
49 #define PCIE_CONF_REG(regn)	(((regn) & GENMASK(7, 2)) | \
50 				((((regn) >> 8) & GENMASK(3, 0)) << 24))
51 #define PCIE_CONF_FUN(fun)	(((fun) << 8) & GENMASK(10, 8))
52 #define PCIE_CONF_DEV(dev)	(((dev) << 11) & GENMASK(15, 11))
53 #define PCIE_CONF_BUS(bus)	(((bus) << 16) & GENMASK(23, 16))
54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 	(PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 	 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57 
58 /* MediaTek specific configuration registers */
59 #define PCIE_FTS_NUM		0x70c
60 #define PCIE_FTS_NUM_MASK	GENMASK(15, 8)
61 #define PCIE_FTS_NUM_L0(x)	((x) & 0xff << 8)
62 
63 #define PCIE_FC_CREDIT		0x73c
64 #define PCIE_FC_CREDIT_MASK	(GENMASK(31, 31) | GENMASK(28, 16))
65 #define PCIE_FC_CREDIT_VAL(x)	((x) << 16)
66 
67 /* PCIe V2 share registers */
68 #define PCIE_SYS_CFG_V2		0x0
69 #define PCIE_CSR_LTSSM_EN(x)	BIT(0 + (x) * 8)
70 #define PCIE_CSR_ASPM_L1_EN(x)	BIT(1 + (x) * 8)
71 
72 /* PCIe V2 per-port registers */
73 #define PCIE_MSI_VECTOR		0x0c0
74 
75 #define PCIE_CONF_VEND_ID	0x100
76 #define PCIE_CONF_DEVICE_ID	0x102
77 #define PCIE_CONF_CLASS_ID	0x106
78 
79 #define PCIE_INT_MASK		0x420
80 #define INTX_MASK		GENMASK(19, 16)
81 #define INTX_SHIFT		16
82 #define PCIE_INT_STATUS		0x424
83 #define MSI_STATUS		BIT(23)
84 #define PCIE_IMSI_STATUS	0x42c
85 #define PCIE_IMSI_ADDR		0x430
86 #define MSI_MASK		BIT(23)
87 #define MTK_MSI_IRQS_NUM	32
88 
89 #define PCIE_AHB_TRANS_BASE0_L	0x438
90 #define PCIE_AHB_TRANS_BASE0_H	0x43c
91 #define AHB2PCIE_SIZE(x)	((x) & GENMASK(4, 0))
92 #define PCIE_AXI_WINDOW0	0x448
93 #define WIN_ENABLE		BIT(7)
94 /*
95  * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96  * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97  * start from 0x40000000).
98  */
99 #define PCIE2AHB_SIZE	0x21
100 
101 /* PCIe V2 configuration transaction header */
102 #define PCIE_CFG_HEADER0	0x460
103 #define PCIE_CFG_HEADER1	0x464
104 #define PCIE_CFG_HEADER2	0x468
105 #define PCIE_CFG_WDATA		0x470
106 #define PCIE_APP_TLP_REQ	0x488
107 #define PCIE_CFG_RDATA		0x48c
108 #define APP_CFG_REQ		BIT(0)
109 #define APP_CPL_STATUS		GENMASK(7, 5)
110 
111 #define CFG_WRRD_TYPE_0		4
112 #define CFG_WR_FMT		2
113 #define CFG_RD_FMT		0
114 
115 #define CFG_DW0_LENGTH(length)	((length) & GENMASK(9, 0))
116 #define CFG_DW0_TYPE(type)	(((type) << 24) & GENMASK(28, 24))
117 #define CFG_DW0_FMT(fmt)	(((fmt) << 29) & GENMASK(31, 29))
118 #define CFG_DW2_REGN(regn)	((regn) & GENMASK(11, 2))
119 #define CFG_DW2_FUN(fun)	(((fun) << 16) & GENMASK(18, 16))
120 #define CFG_DW2_DEV(dev)	(((dev) << 19) & GENMASK(23, 19))
121 #define CFG_DW2_BUS(bus)	(((bus) << 24) & GENMASK(31, 24))
122 #define CFG_HEADER_DW0(type, fmt) \
123 	(CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124 #define CFG_HEADER_DW1(where, size) \
125 	(GENMASK(((size) - 1), 0) << ((where) & 0x3))
126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 	(CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 	CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
129 
130 #define PCIE_RST_CTRL		0x510
131 #define PCIE_PHY_RSTB		BIT(0)
132 #define PCIE_PIPE_SRSTB		BIT(1)
133 #define PCIE_MAC_SRSTB		BIT(2)
134 #define PCIE_CRSTB		BIT(3)
135 #define PCIE_PERSTB		BIT(8)
136 #define PCIE_LINKDOWN_RST_EN	GENMASK(15, 13)
137 #define PCIE_LINK_STATUS_V2	0x804
138 #define PCIE_PORT_LINKUP_V2	BIT(10)
139 
140 struct mtk_pcie_port;
141 
142 /**
143  * struct mtk_pcie_soc - differentiate between host generations
144  * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145  * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146  * @device_id: device ID which this host need to be fixed
147  * @ops: pointer to configuration access functions
148  * @startup: pointer to controller setting functions
149  * @setup_irq: pointer to initialize IRQ functions
150  */
151 struct mtk_pcie_soc {
152 	bool need_fix_class_id;
153 	bool need_fix_device_id;
154 	unsigned int device_id;
155 	struct pci_ops *ops;
156 	int (*startup)(struct mtk_pcie_port *port);
157 	int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
158 };
159 
160 /**
161  * struct mtk_pcie_port - PCIe port information
162  * @base: IO mapped register base
163  * @list: port list
164  * @pcie: pointer to PCIe host info
165  * @reset: pointer to port reset control
166  * @sys_ck: pointer to transaction/data link layer clock
167  * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
168  *          and RC initiated MMIO access
169  * @axi_ck: pointer to application layer MMIO channel operating clock
170  * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
171  *          when pcie_mac_ck/pcie_pipe_ck is turned off
172  * @obff_ck: pointer to OBFF functional block operating clock
173  * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
174  * @phy: pointer to PHY control block
175  * @slot: port slot
176  * @irq: GIC irq
177  * @irq_domain: legacy INTx IRQ domain
178  * @inner_domain: inner IRQ domain
179  * @msi_domain: MSI IRQ domain
180  * @lock: protect the msi_irq_in_use bitmap
181  * @msi_irq_in_use: bit map for assigned MSI IRQ
182  */
183 struct mtk_pcie_port {
184 	void __iomem *base;
185 	struct list_head list;
186 	struct mtk_pcie *pcie;
187 	struct reset_control *reset;
188 	struct clk *sys_ck;
189 	struct clk *ahb_ck;
190 	struct clk *axi_ck;
191 	struct clk *aux_ck;
192 	struct clk *obff_ck;
193 	struct clk *pipe_ck;
194 	struct phy *phy;
195 	u32 slot;
196 	int irq;
197 	struct irq_domain *irq_domain;
198 	struct irq_domain *inner_domain;
199 	struct irq_domain *msi_domain;
200 	struct mutex lock;
201 	DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
202 };
203 
204 /**
205  * struct mtk_pcie - PCIe host information
206  * @dev: pointer to PCIe device
207  * @base: IO mapped register base
208  * @free_ck: free-run reference clock
209  * @mem: non-prefetchable memory resource
210  * @ports: pointer to PCIe port information
211  * @soc: pointer to SoC-dependent operations
212  * @busnr: root bus number
213  */
214 struct mtk_pcie {
215 	struct device *dev;
216 	void __iomem *base;
217 	struct clk *free_ck;
218 
219 	struct resource mem;
220 	struct list_head ports;
221 	const struct mtk_pcie_soc *soc;
222 	unsigned int busnr;
223 };
224 
225 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
226 {
227 	struct device *dev = pcie->dev;
228 
229 	clk_disable_unprepare(pcie->free_ck);
230 
231 	pm_runtime_put_sync(dev);
232 	pm_runtime_disable(dev);
233 }
234 
235 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
236 {
237 	struct mtk_pcie *pcie = port->pcie;
238 	struct device *dev = pcie->dev;
239 
240 	devm_iounmap(dev, port->base);
241 	list_del(&port->list);
242 	devm_kfree(dev, port);
243 }
244 
245 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
246 {
247 	struct mtk_pcie_port *port, *tmp;
248 
249 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
250 		phy_power_off(port->phy);
251 		phy_exit(port->phy);
252 		clk_disable_unprepare(port->pipe_ck);
253 		clk_disable_unprepare(port->obff_ck);
254 		clk_disable_unprepare(port->axi_ck);
255 		clk_disable_unprepare(port->aux_ck);
256 		clk_disable_unprepare(port->ahb_ck);
257 		clk_disable_unprepare(port->sys_ck);
258 		mtk_pcie_port_free(port);
259 	}
260 
261 	mtk_pcie_subsys_powerdown(pcie);
262 }
263 
264 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
265 {
266 	u32 val;
267 	int err;
268 
269 	err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
270 					!(val & APP_CFG_REQ), 10,
271 					100 * USEC_PER_MSEC);
272 	if (err)
273 		return PCIBIOS_SET_FAILED;
274 
275 	if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
276 		return PCIBIOS_SET_FAILED;
277 
278 	return PCIBIOS_SUCCESSFUL;
279 }
280 
281 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
282 			      int where, int size, u32 *val)
283 {
284 	u32 tmp;
285 
286 	/* Write PCIe configuration transaction header for Cfgrd */
287 	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
288 	       port->base + PCIE_CFG_HEADER0);
289 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
290 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
291 	       port->base + PCIE_CFG_HEADER2);
292 
293 	/* Trigger h/w to transmit Cfgrd TLP */
294 	tmp = readl(port->base + PCIE_APP_TLP_REQ);
295 	tmp |= APP_CFG_REQ;
296 	writel(tmp, port->base + PCIE_APP_TLP_REQ);
297 
298 	/* Check completion status */
299 	if (mtk_pcie_check_cfg_cpld(port))
300 		return PCIBIOS_SET_FAILED;
301 
302 	/* Read cpld payload of Cfgrd */
303 	*val = readl(port->base + PCIE_CFG_RDATA);
304 
305 	if (size == 1)
306 		*val = (*val >> (8 * (where & 3))) & 0xff;
307 	else if (size == 2)
308 		*val = (*val >> (8 * (where & 3))) & 0xffff;
309 
310 	return PCIBIOS_SUCCESSFUL;
311 }
312 
313 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
314 			      int where, int size, u32 val)
315 {
316 	/* Write PCIe configuration transaction header for Cfgwr */
317 	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
318 	       port->base + PCIE_CFG_HEADER0);
319 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
320 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
321 	       port->base + PCIE_CFG_HEADER2);
322 
323 	/* Write Cfgwr data */
324 	val = val << 8 * (where & 3);
325 	writel(val, port->base + PCIE_CFG_WDATA);
326 
327 	/* Trigger h/w to transmit Cfgwr TLP */
328 	val = readl(port->base + PCIE_APP_TLP_REQ);
329 	val |= APP_CFG_REQ;
330 	writel(val, port->base + PCIE_APP_TLP_REQ);
331 
332 	/* Check completion status */
333 	return mtk_pcie_check_cfg_cpld(port);
334 }
335 
336 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
337 						unsigned int devfn)
338 {
339 	struct mtk_pcie *pcie = bus->sysdata;
340 	struct mtk_pcie_port *port;
341 	struct pci_dev *dev = NULL;
342 
343 	/*
344 	 * Walk the bus hierarchy to get the devfn value
345 	 * of the port in the root bus.
346 	 */
347 	while (bus && bus->number) {
348 		dev = bus->self;
349 		bus = dev->bus;
350 		devfn = dev->devfn;
351 	}
352 
353 	list_for_each_entry(port, &pcie->ports, list)
354 		if (port->slot == PCI_SLOT(devfn))
355 			return port;
356 
357 	return NULL;
358 }
359 
360 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
361 				int where, int size, u32 *val)
362 {
363 	struct mtk_pcie_port *port;
364 	u32 bn = bus->number;
365 	int ret;
366 
367 	port = mtk_pcie_find_port(bus, devfn);
368 	if (!port) {
369 		*val = ~0;
370 		return PCIBIOS_DEVICE_NOT_FOUND;
371 	}
372 
373 	ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
374 	if (ret)
375 		*val = ~0;
376 
377 	return ret;
378 }
379 
380 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
381 				 int where, int size, u32 val)
382 {
383 	struct mtk_pcie_port *port;
384 	u32 bn = bus->number;
385 
386 	port = mtk_pcie_find_port(bus, devfn);
387 	if (!port)
388 		return PCIBIOS_DEVICE_NOT_FOUND;
389 
390 	return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
391 }
392 
393 static struct pci_ops mtk_pcie_ops_v2 = {
394 	.read  = mtk_pcie_config_read,
395 	.write = mtk_pcie_config_write,
396 };
397 
398 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
399 {
400 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
401 	phys_addr_t addr;
402 
403 	/* MT2712/MT7622 only support 32-bit MSI addresses */
404 	addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
405 	msg->address_hi = 0;
406 	msg->address_lo = lower_32_bits(addr);
407 
408 	msg->data = data->hwirq;
409 
410 	dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
411 		(int)data->hwirq, msg->address_hi, msg->address_lo);
412 }
413 
414 static int mtk_msi_set_affinity(struct irq_data *irq_data,
415 				const struct cpumask *mask, bool force)
416 {
417 	 return -EINVAL;
418 }
419 
420 static void mtk_msi_ack_irq(struct irq_data *data)
421 {
422 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
423 	u32 hwirq = data->hwirq;
424 
425 	writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
426 }
427 
428 static struct irq_chip mtk_msi_bottom_irq_chip = {
429 	.name			= "MTK MSI",
430 	.irq_compose_msi_msg	= mtk_compose_msi_msg,
431 	.irq_set_affinity	= mtk_msi_set_affinity,
432 	.irq_ack		= mtk_msi_ack_irq,
433 };
434 
435 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
436 				     unsigned int nr_irqs, void *args)
437 {
438 	struct mtk_pcie_port *port = domain->host_data;
439 	unsigned long bit;
440 
441 	WARN_ON(nr_irqs != 1);
442 	mutex_lock(&port->lock);
443 
444 	bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
445 	if (bit >= MTK_MSI_IRQS_NUM) {
446 		mutex_unlock(&port->lock);
447 		return -ENOSPC;
448 	}
449 
450 	__set_bit(bit, port->msi_irq_in_use);
451 
452 	mutex_unlock(&port->lock);
453 
454 	irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
455 			    domain->host_data, handle_edge_irq,
456 			    NULL, NULL);
457 
458 	return 0;
459 }
460 
461 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
462 				     unsigned int virq, unsigned int nr_irqs)
463 {
464 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
465 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
466 
467 	mutex_lock(&port->lock);
468 
469 	if (!test_bit(d->hwirq, port->msi_irq_in_use))
470 		dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
471 			d->hwirq);
472 	else
473 		__clear_bit(d->hwirq, port->msi_irq_in_use);
474 
475 	mutex_unlock(&port->lock);
476 
477 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
478 }
479 
480 static const struct irq_domain_ops msi_domain_ops = {
481 	.alloc	= mtk_pcie_irq_domain_alloc,
482 	.free	= mtk_pcie_irq_domain_free,
483 };
484 
485 static struct irq_chip mtk_msi_irq_chip = {
486 	.name		= "MTK PCIe MSI",
487 	.irq_ack	= irq_chip_ack_parent,
488 	.irq_mask	= pci_msi_mask_irq,
489 	.irq_unmask	= pci_msi_unmask_irq,
490 };
491 
492 static struct msi_domain_info mtk_msi_domain_info = {
493 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
494 		   MSI_FLAG_PCI_MSIX),
495 	.chip	= &mtk_msi_irq_chip,
496 };
497 
498 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
499 {
500 	struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
501 
502 	mutex_init(&port->lock);
503 
504 	port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
505 						      &msi_domain_ops, port);
506 	if (!port->inner_domain) {
507 		dev_err(port->pcie->dev, "failed to create IRQ domain\n");
508 		return -ENOMEM;
509 	}
510 
511 	port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
512 						     port->inner_domain);
513 	if (!port->msi_domain) {
514 		dev_err(port->pcie->dev, "failed to create MSI domain\n");
515 		irq_domain_remove(port->inner_domain);
516 		return -ENOMEM;
517 	}
518 
519 	return 0;
520 }
521 
522 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
523 {
524 	u32 val;
525 	phys_addr_t msg_addr;
526 
527 	msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
528 	val = lower_32_bits(msg_addr);
529 	writel(val, port->base + PCIE_IMSI_ADDR);
530 
531 	val = readl(port->base + PCIE_INT_MASK);
532 	val &= ~MSI_MASK;
533 	writel(val, port->base + PCIE_INT_MASK);
534 }
535 
536 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
537 {
538 	struct mtk_pcie_port *port, *tmp;
539 
540 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
541 		irq_set_chained_handler_and_data(port->irq, NULL, NULL);
542 
543 		if (port->irq_domain)
544 			irq_domain_remove(port->irq_domain);
545 
546 		if (IS_ENABLED(CONFIG_PCI_MSI)) {
547 			if (port->msi_domain)
548 				irq_domain_remove(port->msi_domain);
549 			if (port->inner_domain)
550 				irq_domain_remove(port->inner_domain);
551 		}
552 
553 		irq_dispose_mapping(port->irq);
554 	}
555 }
556 
557 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
558 			     irq_hw_number_t hwirq)
559 {
560 	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
561 	irq_set_chip_data(irq, domain->host_data);
562 
563 	return 0;
564 }
565 
566 static const struct irq_domain_ops intx_domain_ops = {
567 	.map = mtk_pcie_intx_map,
568 };
569 
570 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
571 				    struct device_node *node)
572 {
573 	struct device *dev = port->pcie->dev;
574 	struct device_node *pcie_intc_node;
575 	int ret;
576 
577 	/* Setup INTx */
578 	pcie_intc_node = of_get_next_child(node, NULL);
579 	if (!pcie_intc_node) {
580 		dev_err(dev, "no PCIe Intc node found\n");
581 		return -ENODEV;
582 	}
583 
584 	port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
585 						 &intx_domain_ops, port);
586 	of_node_put(pcie_intc_node);
587 	if (!port->irq_domain) {
588 		dev_err(dev, "failed to get INTx IRQ domain\n");
589 		return -ENODEV;
590 	}
591 
592 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
593 		ret = mtk_pcie_allocate_msi_domains(port);
594 		if (ret)
595 			return ret;
596 	}
597 
598 	return 0;
599 }
600 
601 static void mtk_pcie_intr_handler(struct irq_desc *desc)
602 {
603 	struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
604 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
605 	unsigned long status;
606 	u32 virq;
607 	u32 bit = INTX_SHIFT;
608 
609 	chained_irq_enter(irqchip, desc);
610 
611 	status = readl(port->base + PCIE_INT_STATUS);
612 	if (status & INTX_MASK) {
613 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
614 			/* Clear the INTx */
615 			writel(1 << bit, port->base + PCIE_INT_STATUS);
616 			virq = irq_find_mapping(port->irq_domain,
617 						bit - INTX_SHIFT);
618 			generic_handle_irq(virq);
619 		}
620 	}
621 
622 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
623 		if (status & MSI_STATUS){
624 			unsigned long imsi_status;
625 
626 			while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
627 				for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
628 					virq = irq_find_mapping(port->inner_domain, bit);
629 					generic_handle_irq(virq);
630 				}
631 			}
632 			/* Clear MSI interrupt status */
633 			writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
634 		}
635 	}
636 
637 	chained_irq_exit(irqchip, desc);
638 }
639 
640 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
641 			      struct device_node *node)
642 {
643 	struct mtk_pcie *pcie = port->pcie;
644 	struct device *dev = pcie->dev;
645 	struct platform_device *pdev = to_platform_device(dev);
646 	int err;
647 
648 	err = mtk_pcie_init_irq_domain(port, node);
649 	if (err) {
650 		dev_err(dev, "failed to init PCIe IRQ domain\n");
651 		return err;
652 	}
653 
654 	port->irq = platform_get_irq(pdev, port->slot);
655 	irq_set_chained_handler_and_data(port->irq,
656 					 mtk_pcie_intr_handler, port);
657 
658 	return 0;
659 }
660 
661 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
662 {
663 	struct mtk_pcie *pcie = port->pcie;
664 	struct resource *mem = &pcie->mem;
665 	const struct mtk_pcie_soc *soc = port->pcie->soc;
666 	u32 val;
667 	int err;
668 
669 	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
670 	if (pcie->base) {
671 		val = readl(pcie->base + PCIE_SYS_CFG_V2);
672 		val |= PCIE_CSR_LTSSM_EN(port->slot) |
673 		       PCIE_CSR_ASPM_L1_EN(port->slot);
674 		writel(val, pcie->base + PCIE_SYS_CFG_V2);
675 	}
676 
677 	/* Assert all reset signals */
678 	writel(0, port->base + PCIE_RST_CTRL);
679 
680 	/*
681 	 * Enable PCIe link down reset, if link status changed from link up to
682 	 * link down, this will reset MAC control registers and configuration
683 	 * space.
684 	 */
685 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
686 
687 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
688 	val = readl(port->base + PCIE_RST_CTRL);
689 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
690 	       PCIE_MAC_SRSTB | PCIE_CRSTB;
691 	writel(val, port->base + PCIE_RST_CTRL);
692 
693 	/* Set up vendor ID and class code */
694 	if (soc->need_fix_class_id) {
695 		val = PCI_VENDOR_ID_MEDIATEK;
696 		writew(val, port->base + PCIE_CONF_VEND_ID);
697 
698 		val = PCI_CLASS_BRIDGE_PCI;
699 		writew(val, port->base + PCIE_CONF_CLASS_ID);
700 	}
701 
702 	if (soc->need_fix_device_id)
703 		writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
704 
705 	/* 100ms timeout value should be enough for Gen1/2 training */
706 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
707 				 !!(val & PCIE_PORT_LINKUP_V2), 20,
708 				 100 * USEC_PER_MSEC);
709 	if (err)
710 		return -ETIMEDOUT;
711 
712 	/* Set INTx mask */
713 	val = readl(port->base + PCIE_INT_MASK);
714 	val &= ~INTX_MASK;
715 	writel(val, port->base + PCIE_INT_MASK);
716 
717 	if (IS_ENABLED(CONFIG_PCI_MSI))
718 		mtk_pcie_enable_msi(port);
719 
720 	/* Set AHB to PCIe translation windows */
721 	val = lower_32_bits(mem->start) |
722 	      AHB2PCIE_SIZE(fls(resource_size(mem)));
723 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
724 
725 	val = upper_32_bits(mem->start);
726 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
727 
728 	/* Set PCIe to AXI translation memory space.*/
729 	val = PCIE2AHB_SIZE | WIN_ENABLE;
730 	writel(val, port->base + PCIE_AXI_WINDOW0);
731 
732 	return 0;
733 }
734 
735 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
736 				      unsigned int devfn, int where)
737 {
738 	struct mtk_pcie *pcie = bus->sysdata;
739 
740 	writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
741 			      bus->number), pcie->base + PCIE_CFG_ADDR);
742 
743 	return pcie->base + PCIE_CFG_DATA + (where & 3);
744 }
745 
746 static struct pci_ops mtk_pcie_ops = {
747 	.map_bus = mtk_pcie_map_bus,
748 	.read  = pci_generic_config_read,
749 	.write = pci_generic_config_write,
750 };
751 
752 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
753 {
754 	struct mtk_pcie *pcie = port->pcie;
755 	u32 func = PCI_FUNC(port->slot << 3);
756 	u32 slot = PCI_SLOT(port->slot << 3);
757 	u32 val;
758 	int err;
759 
760 	/* assert port PERST_N */
761 	val = readl(pcie->base + PCIE_SYS_CFG);
762 	val |= PCIE_PORT_PERST(port->slot);
763 	writel(val, pcie->base + PCIE_SYS_CFG);
764 
765 	/* de-assert port PERST_N */
766 	val = readl(pcie->base + PCIE_SYS_CFG);
767 	val &= ~PCIE_PORT_PERST(port->slot);
768 	writel(val, pcie->base + PCIE_SYS_CFG);
769 
770 	/* 100ms timeout value should be enough for Gen1/2 training */
771 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
772 				 !!(val & PCIE_PORT_LINKUP), 20,
773 				 100 * USEC_PER_MSEC);
774 	if (err)
775 		return -ETIMEDOUT;
776 
777 	/* enable interrupt */
778 	val = readl(pcie->base + PCIE_INT_ENABLE);
779 	val |= PCIE_PORT_INT_EN(port->slot);
780 	writel(val, pcie->base + PCIE_INT_ENABLE);
781 
782 	/* map to all DDR region. We need to set it before cfg operation. */
783 	writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
784 	       port->base + PCIE_BAR0_SETUP);
785 
786 	/* configure class code and revision ID */
787 	writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
788 
789 	/* configure FC credit */
790 	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
791 	       pcie->base + PCIE_CFG_ADDR);
792 	val = readl(pcie->base + PCIE_CFG_DATA);
793 	val &= ~PCIE_FC_CREDIT_MASK;
794 	val |= PCIE_FC_CREDIT_VAL(0x806c);
795 	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
796 	       pcie->base + PCIE_CFG_ADDR);
797 	writel(val, pcie->base + PCIE_CFG_DATA);
798 
799 	/* configure RC FTS number to 250 when it leaves L0s */
800 	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
801 	       pcie->base + PCIE_CFG_ADDR);
802 	val = readl(pcie->base + PCIE_CFG_DATA);
803 	val &= ~PCIE_FTS_NUM_MASK;
804 	val |= PCIE_FTS_NUM_L0(0x50);
805 	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
806 	       pcie->base + PCIE_CFG_ADDR);
807 	writel(val, pcie->base + PCIE_CFG_DATA);
808 
809 	return 0;
810 }
811 
812 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
813 {
814 	struct mtk_pcie *pcie = port->pcie;
815 	struct device *dev = pcie->dev;
816 	int err;
817 
818 	err = clk_prepare_enable(port->sys_ck);
819 	if (err) {
820 		dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
821 		goto err_sys_clk;
822 	}
823 
824 	err = clk_prepare_enable(port->ahb_ck);
825 	if (err) {
826 		dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
827 		goto err_ahb_clk;
828 	}
829 
830 	err = clk_prepare_enable(port->aux_ck);
831 	if (err) {
832 		dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
833 		goto err_aux_clk;
834 	}
835 
836 	err = clk_prepare_enable(port->axi_ck);
837 	if (err) {
838 		dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
839 		goto err_axi_clk;
840 	}
841 
842 	err = clk_prepare_enable(port->obff_ck);
843 	if (err) {
844 		dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
845 		goto err_obff_clk;
846 	}
847 
848 	err = clk_prepare_enable(port->pipe_ck);
849 	if (err) {
850 		dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
851 		goto err_pipe_clk;
852 	}
853 
854 	reset_control_assert(port->reset);
855 	reset_control_deassert(port->reset);
856 
857 	err = phy_init(port->phy);
858 	if (err) {
859 		dev_err(dev, "failed to initialize port%d phy\n", port->slot);
860 		goto err_phy_init;
861 	}
862 
863 	err = phy_power_on(port->phy);
864 	if (err) {
865 		dev_err(dev, "failed to power on port%d phy\n", port->slot);
866 		goto err_phy_on;
867 	}
868 
869 	if (!pcie->soc->startup(port))
870 		return;
871 
872 	dev_info(dev, "Port%d link down\n", port->slot);
873 
874 	phy_power_off(port->phy);
875 err_phy_on:
876 	phy_exit(port->phy);
877 err_phy_init:
878 	clk_disable_unprepare(port->pipe_ck);
879 err_pipe_clk:
880 	clk_disable_unprepare(port->obff_ck);
881 err_obff_clk:
882 	clk_disable_unprepare(port->axi_ck);
883 err_axi_clk:
884 	clk_disable_unprepare(port->aux_ck);
885 err_aux_clk:
886 	clk_disable_unprepare(port->ahb_ck);
887 err_ahb_clk:
888 	clk_disable_unprepare(port->sys_ck);
889 err_sys_clk:
890 	mtk_pcie_port_free(port);
891 }
892 
893 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
894 			       struct device_node *node,
895 			       int slot)
896 {
897 	struct mtk_pcie_port *port;
898 	struct resource *regs;
899 	struct device *dev = pcie->dev;
900 	struct platform_device *pdev = to_platform_device(dev);
901 	char name[10];
902 	int err;
903 
904 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
905 	if (!port)
906 		return -ENOMEM;
907 
908 	snprintf(name, sizeof(name), "port%d", slot);
909 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
910 	port->base = devm_ioremap_resource(dev, regs);
911 	if (IS_ERR(port->base)) {
912 		dev_err(dev, "failed to map port%d base\n", slot);
913 		return PTR_ERR(port->base);
914 	}
915 
916 	snprintf(name, sizeof(name), "sys_ck%d", slot);
917 	port->sys_ck = devm_clk_get(dev, name);
918 	if (IS_ERR(port->sys_ck)) {
919 		dev_err(dev, "failed to get sys_ck%d clock\n", slot);
920 		return PTR_ERR(port->sys_ck);
921 	}
922 
923 	/* sys_ck might be divided into the following parts in some chips */
924 	snprintf(name, sizeof(name), "ahb_ck%d", slot);
925 	port->ahb_ck = devm_clk_get_optional(dev, name);
926 	if (IS_ERR(port->ahb_ck))
927 		return PTR_ERR(port->ahb_ck);
928 
929 	snprintf(name, sizeof(name), "axi_ck%d", slot);
930 	port->axi_ck = devm_clk_get_optional(dev, name);
931 	if (IS_ERR(port->axi_ck))
932 		return PTR_ERR(port->axi_ck);
933 
934 	snprintf(name, sizeof(name), "aux_ck%d", slot);
935 	port->aux_ck = devm_clk_get_optional(dev, name);
936 	if (IS_ERR(port->aux_ck))
937 		return PTR_ERR(port->aux_ck);
938 
939 	snprintf(name, sizeof(name), "obff_ck%d", slot);
940 	port->obff_ck = devm_clk_get_optional(dev, name);
941 	if (IS_ERR(port->obff_ck))
942 		return PTR_ERR(port->obff_ck);
943 
944 	snprintf(name, sizeof(name), "pipe_ck%d", slot);
945 	port->pipe_ck = devm_clk_get_optional(dev, name);
946 	if (IS_ERR(port->pipe_ck))
947 		return PTR_ERR(port->pipe_ck);
948 
949 	snprintf(name, sizeof(name), "pcie-rst%d", slot);
950 	port->reset = devm_reset_control_get_optional_exclusive(dev, name);
951 	if (PTR_ERR(port->reset) == -EPROBE_DEFER)
952 		return PTR_ERR(port->reset);
953 
954 	/* some platforms may use default PHY setting */
955 	snprintf(name, sizeof(name), "pcie-phy%d", slot);
956 	port->phy = devm_phy_optional_get(dev, name);
957 	if (IS_ERR(port->phy))
958 		return PTR_ERR(port->phy);
959 
960 	port->slot = slot;
961 	port->pcie = pcie;
962 
963 	if (pcie->soc->setup_irq) {
964 		err = pcie->soc->setup_irq(port, node);
965 		if (err)
966 			return err;
967 	}
968 
969 	INIT_LIST_HEAD(&port->list);
970 	list_add_tail(&port->list, &pcie->ports);
971 
972 	return 0;
973 }
974 
975 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
976 {
977 	struct device *dev = pcie->dev;
978 	struct platform_device *pdev = to_platform_device(dev);
979 	struct resource *regs;
980 	int err;
981 
982 	/* get shared registers, which are optional */
983 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
984 	if (regs) {
985 		pcie->base = devm_ioremap_resource(dev, regs);
986 		if (IS_ERR(pcie->base)) {
987 			dev_err(dev, "failed to map shared register\n");
988 			return PTR_ERR(pcie->base);
989 		}
990 	}
991 
992 	pcie->free_ck = devm_clk_get(dev, "free_ck");
993 	if (IS_ERR(pcie->free_ck)) {
994 		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
995 			return -EPROBE_DEFER;
996 
997 		pcie->free_ck = NULL;
998 	}
999 
1000 	pm_runtime_enable(dev);
1001 	pm_runtime_get_sync(dev);
1002 
1003 	/* enable top level clock */
1004 	err = clk_prepare_enable(pcie->free_ck);
1005 	if (err) {
1006 		dev_err(dev, "failed to enable free_ck\n");
1007 		goto err_free_ck;
1008 	}
1009 
1010 	return 0;
1011 
1012 err_free_ck:
1013 	pm_runtime_put_sync(dev);
1014 	pm_runtime_disable(dev);
1015 
1016 	return err;
1017 }
1018 
1019 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1020 {
1021 	struct device *dev = pcie->dev;
1022 	struct device_node *node = dev->of_node, *child;
1023 	struct mtk_pcie_port *port, *tmp;
1024 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1025 	struct list_head *windows = &host->windows;
1026 	struct resource_entry *win, *tmp_win;
1027 	resource_size_t io_base;
1028 	int err;
1029 
1030 	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
1031 						    windows, &io_base);
1032 	if (err)
1033 		return err;
1034 
1035 	err = devm_request_pci_bus_resources(dev, windows);
1036 	if (err < 0)
1037 		return err;
1038 
1039 	/* Get the I/O and memory ranges from DT */
1040 	resource_list_for_each_entry_safe(win, tmp_win, windows) {
1041 		switch (resource_type(win->res)) {
1042 		case IORESOURCE_IO:
1043 			err = devm_pci_remap_iospace(dev, win->res, io_base);
1044 			if (err) {
1045 				dev_warn(dev, "error %d: failed to map resource %pR\n",
1046 					 err, win->res);
1047 				resource_list_destroy_entry(win);
1048 			}
1049 			break;
1050 		case IORESOURCE_MEM:
1051 			memcpy(&pcie->mem, win->res, sizeof(*win->res));
1052 			pcie->mem.name = "non-prefetchable";
1053 			break;
1054 		case IORESOURCE_BUS:
1055 			pcie->busnr = win->res->start;
1056 			break;
1057 		}
1058 	}
1059 
1060 	for_each_available_child_of_node(node, child) {
1061 		int slot;
1062 
1063 		err = of_pci_get_devfn(child);
1064 		if (err < 0) {
1065 			dev_err(dev, "failed to parse devfn: %d\n", err);
1066 			return err;
1067 		}
1068 
1069 		slot = PCI_SLOT(err);
1070 
1071 		err = mtk_pcie_parse_port(pcie, child, slot);
1072 		if (err)
1073 			return err;
1074 	}
1075 
1076 	err = mtk_pcie_subsys_powerup(pcie);
1077 	if (err)
1078 		return err;
1079 
1080 	/* enable each port, and then check link status */
1081 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1082 		mtk_pcie_enable_port(port);
1083 
1084 	/* power down PCIe subsys if slots are all empty (link down) */
1085 	if (list_empty(&pcie->ports))
1086 		mtk_pcie_subsys_powerdown(pcie);
1087 
1088 	return 0;
1089 }
1090 
1091 static int mtk_pcie_probe(struct platform_device *pdev)
1092 {
1093 	struct device *dev = &pdev->dev;
1094 	struct mtk_pcie *pcie;
1095 	struct pci_host_bridge *host;
1096 	int err;
1097 
1098 	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1099 	if (!host)
1100 		return -ENOMEM;
1101 
1102 	pcie = pci_host_bridge_priv(host);
1103 
1104 	pcie->dev = dev;
1105 	pcie->soc = of_device_get_match_data(dev);
1106 	platform_set_drvdata(pdev, pcie);
1107 	INIT_LIST_HEAD(&pcie->ports);
1108 
1109 	err = mtk_pcie_setup(pcie);
1110 	if (err)
1111 		return err;
1112 
1113 	host->busnr = pcie->busnr;
1114 	host->dev.parent = pcie->dev;
1115 	host->ops = pcie->soc->ops;
1116 	host->map_irq = of_irq_parse_and_map_pci;
1117 	host->swizzle_irq = pci_common_swizzle;
1118 	host->sysdata = pcie;
1119 
1120 	err = pci_host_probe(host);
1121 	if (err)
1122 		goto put_resources;
1123 
1124 	return 0;
1125 
1126 put_resources:
1127 	if (!list_empty(&pcie->ports))
1128 		mtk_pcie_put_resources(pcie);
1129 
1130 	return err;
1131 }
1132 
1133 
1134 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1135 {
1136 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1137 	struct list_head *windows = &host->windows;
1138 
1139 	pci_free_resource_list(windows);
1140 }
1141 
1142 static int mtk_pcie_remove(struct platform_device *pdev)
1143 {
1144 	struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1145 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1146 
1147 	pci_stop_root_bus(host->bus);
1148 	pci_remove_root_bus(host->bus);
1149 	mtk_pcie_free_resources(pcie);
1150 
1151 	mtk_pcie_irq_teardown(pcie);
1152 
1153 	mtk_pcie_put_resources(pcie);
1154 
1155 	return 0;
1156 }
1157 
1158 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1159 {
1160 	struct mtk_pcie *pcie = dev_get_drvdata(dev);
1161 	struct mtk_pcie_port *port;
1162 
1163 	if (list_empty(&pcie->ports))
1164 		return 0;
1165 
1166 	list_for_each_entry(port, &pcie->ports, list) {
1167 		clk_disable_unprepare(port->pipe_ck);
1168 		clk_disable_unprepare(port->obff_ck);
1169 		clk_disable_unprepare(port->axi_ck);
1170 		clk_disable_unprepare(port->aux_ck);
1171 		clk_disable_unprepare(port->ahb_ck);
1172 		clk_disable_unprepare(port->sys_ck);
1173 		phy_power_off(port->phy);
1174 		phy_exit(port->phy);
1175 	}
1176 
1177 	clk_disable_unprepare(pcie->free_ck);
1178 
1179 	return 0;
1180 }
1181 
1182 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1183 {
1184 	struct mtk_pcie *pcie = dev_get_drvdata(dev);
1185 	struct mtk_pcie_port *port, *tmp;
1186 
1187 	if (list_empty(&pcie->ports))
1188 		return 0;
1189 
1190 	clk_prepare_enable(pcie->free_ck);
1191 
1192 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1193 		mtk_pcie_enable_port(port);
1194 
1195 	/* In case of EP was removed while system suspend. */
1196 	if (list_empty(&pcie->ports))
1197 		clk_disable_unprepare(pcie->free_ck);
1198 
1199 	return 0;
1200 }
1201 
1202 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1203 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1204 				      mtk_pcie_resume_noirq)
1205 };
1206 
1207 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1208 	.ops = &mtk_pcie_ops,
1209 	.startup = mtk_pcie_startup_port,
1210 };
1211 
1212 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1213 	.ops = &mtk_pcie_ops_v2,
1214 	.startup = mtk_pcie_startup_port_v2,
1215 	.setup_irq = mtk_pcie_setup_irq,
1216 };
1217 
1218 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1219 	.need_fix_class_id = true,
1220 	.ops = &mtk_pcie_ops_v2,
1221 	.startup = mtk_pcie_startup_port_v2,
1222 	.setup_irq = mtk_pcie_setup_irq,
1223 };
1224 
1225 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1226 	.need_fix_class_id = true,
1227 	.need_fix_device_id = true,
1228 	.device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1229 	.ops = &mtk_pcie_ops_v2,
1230 	.startup = mtk_pcie_startup_port_v2,
1231 	.setup_irq = mtk_pcie_setup_irq,
1232 };
1233 
1234 static const struct of_device_id mtk_pcie_ids[] = {
1235 	{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1236 	{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1237 	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1238 	{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1239 	{ .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1240 	{},
1241 };
1242 
1243 static struct platform_driver mtk_pcie_driver = {
1244 	.probe = mtk_pcie_probe,
1245 	.remove = mtk_pcie_remove,
1246 	.driver = {
1247 		.name = "mtk-pcie",
1248 		.of_match_table = mtk_pcie_ids,
1249 		.suppress_bind_attrs = true,
1250 		.pm = &mtk_pcie_pm_ops,
1251 	},
1252 };
1253 module_platform_driver(mtk_pcie_driver);
1254 MODULE_LICENSE("GPL v2");
1255