1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/msi.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 #include <linux/of_platform.h> 22 #include <linux/pci.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/reset.h> 27 28 #include "../pci.h" 29 30 /* PCIe shared registers */ 31 #define PCIE_SYS_CFG 0x00 32 #define PCIE_INT_ENABLE 0x0c 33 #define PCIE_CFG_ADDR 0x20 34 #define PCIE_CFG_DATA 0x24 35 36 /* PCIe per port registers */ 37 #define PCIE_BAR0_SETUP 0x10 38 #define PCIE_CLASS 0x34 39 #define PCIE_LINK_STATUS 0x50 40 41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 42 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 43 #define PCIE_PORT_LINKUP BIT(0) 44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 45 46 #define PCIE_BAR_ENABLE BIT(0) 47 #define PCIE_REVISION_ID BIT(0) 48 #define PCIE_CLASS_CODE (0x60400 << 8) 49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 50 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 57 58 /* MediaTek specific configuration registers */ 59 #define PCIE_FTS_NUM 0x70c 60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) 62 63 #define PCIE_FC_CREDIT 0x73c 64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 66 67 /* PCIe V2 share registers */ 68 #define PCIE_SYS_CFG_V2 0x0 69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 71 72 /* PCIe V2 per-port registers */ 73 #define PCIE_MSI_VECTOR 0x0c0 74 75 #define PCIE_CONF_VEND_ID 0x100 76 #define PCIE_CONF_CLASS_ID 0x106 77 78 #define PCIE_INT_MASK 0x420 79 #define INTX_MASK GENMASK(19, 16) 80 #define INTX_SHIFT 16 81 #define PCIE_INT_STATUS 0x424 82 #define MSI_STATUS BIT(23) 83 #define PCIE_IMSI_STATUS 0x42c 84 #define PCIE_IMSI_ADDR 0x430 85 #define MSI_MASK BIT(23) 86 #define MTK_MSI_IRQS_NUM 32 87 88 #define PCIE_AHB_TRANS_BASE0_L 0x438 89 #define PCIE_AHB_TRANS_BASE0_H 0x43c 90 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 91 #define PCIE_AXI_WINDOW0 0x448 92 #define WIN_ENABLE BIT(7) 93 /* 94 * Define PCIe to AHB window size as 2^33 to support max 8GB address space 95 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM 96 * start from 0x40000000). 97 */ 98 #define PCIE2AHB_SIZE 0x21 99 100 /* PCIe V2 configuration transaction header */ 101 #define PCIE_CFG_HEADER0 0x460 102 #define PCIE_CFG_HEADER1 0x464 103 #define PCIE_CFG_HEADER2 0x468 104 #define PCIE_CFG_WDATA 0x470 105 #define PCIE_APP_TLP_REQ 0x488 106 #define PCIE_CFG_RDATA 0x48c 107 #define APP_CFG_REQ BIT(0) 108 #define APP_CPL_STATUS GENMASK(7, 5) 109 110 #define CFG_WRRD_TYPE_0 4 111 #define CFG_WR_FMT 2 112 #define CFG_RD_FMT 0 113 114 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 115 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 116 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 117 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 118 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 119 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 120 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 121 #define CFG_HEADER_DW0(type, fmt) \ 122 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 123 #define CFG_HEADER_DW1(where, size) \ 124 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 125 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 126 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 127 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 128 129 #define PCIE_RST_CTRL 0x510 130 #define PCIE_PHY_RSTB BIT(0) 131 #define PCIE_PIPE_SRSTB BIT(1) 132 #define PCIE_MAC_SRSTB BIT(2) 133 #define PCIE_CRSTB BIT(3) 134 #define PCIE_PERSTB BIT(8) 135 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 136 #define PCIE_LINK_STATUS_V2 0x804 137 #define PCIE_PORT_LINKUP_V2 BIT(10) 138 139 struct mtk_pcie_port; 140 141 /** 142 * struct mtk_pcie_soc - differentiate between host generations 143 * @need_fix_class_id: whether this host's class ID needed to be fixed or not 144 * @ops: pointer to configuration access functions 145 * @startup: pointer to controller setting functions 146 * @setup_irq: pointer to initialize IRQ functions 147 */ 148 struct mtk_pcie_soc { 149 bool need_fix_class_id; 150 struct pci_ops *ops; 151 int (*startup)(struct mtk_pcie_port *port); 152 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 153 }; 154 155 /** 156 * struct mtk_pcie_port - PCIe port information 157 * @base: IO mapped register base 158 * @list: port list 159 * @pcie: pointer to PCIe host info 160 * @reset: pointer to port reset control 161 * @sys_ck: pointer to transaction/data link layer clock 162 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 163 * and RC initiated MMIO access 164 * @axi_ck: pointer to application layer MMIO channel operating clock 165 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 166 * when pcie_mac_ck/pcie_pipe_ck is turned off 167 * @obff_ck: pointer to OBFF functional block operating clock 168 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 169 * @phy: pointer to PHY control block 170 * @slot: port slot 171 * @irq: GIC irq 172 * @irq_domain: legacy INTx IRQ domain 173 * @inner_domain: inner IRQ domain 174 * @msi_domain: MSI IRQ domain 175 * @lock: protect the msi_irq_in_use bitmap 176 * @msi_irq_in_use: bit map for assigned MSI IRQ 177 */ 178 struct mtk_pcie_port { 179 void __iomem *base; 180 struct list_head list; 181 struct mtk_pcie *pcie; 182 struct reset_control *reset; 183 struct clk *sys_ck; 184 struct clk *ahb_ck; 185 struct clk *axi_ck; 186 struct clk *aux_ck; 187 struct clk *obff_ck; 188 struct clk *pipe_ck; 189 struct phy *phy; 190 u32 slot; 191 int irq; 192 struct irq_domain *irq_domain; 193 struct irq_domain *inner_domain; 194 struct irq_domain *msi_domain; 195 struct mutex lock; 196 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 197 }; 198 199 /** 200 * struct mtk_pcie - PCIe host information 201 * @dev: pointer to PCIe device 202 * @base: IO mapped register base 203 * @free_ck: free-run reference clock 204 * @mem: non-prefetchable memory resource 205 * @ports: pointer to PCIe port information 206 * @soc: pointer to SoC-dependent operations 207 * @busnr: root bus number 208 */ 209 struct mtk_pcie { 210 struct device *dev; 211 void __iomem *base; 212 struct clk *free_ck; 213 214 struct resource mem; 215 struct list_head ports; 216 const struct mtk_pcie_soc *soc; 217 unsigned int busnr; 218 }; 219 220 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 221 { 222 struct device *dev = pcie->dev; 223 224 clk_disable_unprepare(pcie->free_ck); 225 226 pm_runtime_put_sync(dev); 227 pm_runtime_disable(dev); 228 } 229 230 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 231 { 232 struct mtk_pcie *pcie = port->pcie; 233 struct device *dev = pcie->dev; 234 235 devm_iounmap(dev, port->base); 236 list_del(&port->list); 237 devm_kfree(dev, port); 238 } 239 240 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 241 { 242 struct mtk_pcie_port *port, *tmp; 243 244 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 245 phy_power_off(port->phy); 246 phy_exit(port->phy); 247 clk_disable_unprepare(port->pipe_ck); 248 clk_disable_unprepare(port->obff_ck); 249 clk_disable_unprepare(port->axi_ck); 250 clk_disable_unprepare(port->aux_ck); 251 clk_disable_unprepare(port->ahb_ck); 252 clk_disable_unprepare(port->sys_ck); 253 mtk_pcie_port_free(port); 254 } 255 256 mtk_pcie_subsys_powerdown(pcie); 257 } 258 259 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 260 { 261 u32 val; 262 int err; 263 264 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 265 !(val & APP_CFG_REQ), 10, 266 100 * USEC_PER_MSEC); 267 if (err) 268 return PCIBIOS_SET_FAILED; 269 270 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 271 return PCIBIOS_SET_FAILED; 272 273 return PCIBIOS_SUCCESSFUL; 274 } 275 276 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 277 int where, int size, u32 *val) 278 { 279 u32 tmp; 280 281 /* Write PCIe configuration transaction header for Cfgrd */ 282 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT), 283 port->base + PCIE_CFG_HEADER0); 284 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 285 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 286 port->base + PCIE_CFG_HEADER2); 287 288 /* Trigger h/w to transmit Cfgrd TLP */ 289 tmp = readl(port->base + PCIE_APP_TLP_REQ); 290 tmp |= APP_CFG_REQ; 291 writel(tmp, port->base + PCIE_APP_TLP_REQ); 292 293 /* Check completion status */ 294 if (mtk_pcie_check_cfg_cpld(port)) 295 return PCIBIOS_SET_FAILED; 296 297 /* Read cpld payload of Cfgrd */ 298 *val = readl(port->base + PCIE_CFG_RDATA); 299 300 if (size == 1) 301 *val = (*val >> (8 * (where & 3))) & 0xff; 302 else if (size == 2) 303 *val = (*val >> (8 * (where & 3))) & 0xffff; 304 305 return PCIBIOS_SUCCESSFUL; 306 } 307 308 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 309 int where, int size, u32 val) 310 { 311 /* Write PCIe configuration transaction header for Cfgwr */ 312 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT), 313 port->base + PCIE_CFG_HEADER0); 314 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 315 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 316 port->base + PCIE_CFG_HEADER2); 317 318 /* Write Cfgwr data */ 319 val = val << 8 * (where & 3); 320 writel(val, port->base + PCIE_CFG_WDATA); 321 322 /* Trigger h/w to transmit Cfgwr TLP */ 323 val = readl(port->base + PCIE_APP_TLP_REQ); 324 val |= APP_CFG_REQ; 325 writel(val, port->base + PCIE_APP_TLP_REQ); 326 327 /* Check completion status */ 328 return mtk_pcie_check_cfg_cpld(port); 329 } 330 331 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 332 unsigned int devfn) 333 { 334 struct mtk_pcie *pcie = bus->sysdata; 335 struct mtk_pcie_port *port; 336 struct pci_dev *dev = NULL; 337 338 /* 339 * Walk the bus hierarchy to get the devfn value 340 * of the port in the root bus. 341 */ 342 while (bus && bus->number) { 343 dev = bus->self; 344 bus = dev->bus; 345 devfn = dev->devfn; 346 } 347 348 list_for_each_entry(port, &pcie->ports, list) 349 if (port->slot == PCI_SLOT(devfn)) 350 return port; 351 352 return NULL; 353 } 354 355 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 356 int where, int size, u32 *val) 357 { 358 struct mtk_pcie_port *port; 359 u32 bn = bus->number; 360 int ret; 361 362 port = mtk_pcie_find_port(bus, devfn); 363 if (!port) { 364 *val = ~0; 365 return PCIBIOS_DEVICE_NOT_FOUND; 366 } 367 368 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 369 if (ret) 370 *val = ~0; 371 372 return ret; 373 } 374 375 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 376 int where, int size, u32 val) 377 { 378 struct mtk_pcie_port *port; 379 u32 bn = bus->number; 380 381 port = mtk_pcie_find_port(bus, devfn); 382 if (!port) 383 return PCIBIOS_DEVICE_NOT_FOUND; 384 385 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 386 } 387 388 static struct pci_ops mtk_pcie_ops_v2 = { 389 .read = mtk_pcie_config_read, 390 .write = mtk_pcie_config_write, 391 }; 392 393 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 394 { 395 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 396 phys_addr_t addr; 397 398 /* MT2712/MT7622 only support 32-bit MSI addresses */ 399 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 400 msg->address_hi = 0; 401 msg->address_lo = lower_32_bits(addr); 402 403 msg->data = data->hwirq; 404 405 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 406 (int)data->hwirq, msg->address_hi, msg->address_lo); 407 } 408 409 static int mtk_msi_set_affinity(struct irq_data *irq_data, 410 const struct cpumask *mask, bool force) 411 { 412 return -EINVAL; 413 } 414 415 static void mtk_msi_ack_irq(struct irq_data *data) 416 { 417 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 418 u32 hwirq = data->hwirq; 419 420 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 421 } 422 423 static struct irq_chip mtk_msi_bottom_irq_chip = { 424 .name = "MTK MSI", 425 .irq_compose_msi_msg = mtk_compose_msi_msg, 426 .irq_set_affinity = mtk_msi_set_affinity, 427 .irq_ack = mtk_msi_ack_irq, 428 }; 429 430 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 431 unsigned int nr_irqs, void *args) 432 { 433 struct mtk_pcie_port *port = domain->host_data; 434 unsigned long bit; 435 436 WARN_ON(nr_irqs != 1); 437 mutex_lock(&port->lock); 438 439 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 440 if (bit >= MTK_MSI_IRQS_NUM) { 441 mutex_unlock(&port->lock); 442 return -ENOSPC; 443 } 444 445 __set_bit(bit, port->msi_irq_in_use); 446 447 mutex_unlock(&port->lock); 448 449 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 450 domain->host_data, handle_edge_irq, 451 NULL, NULL); 452 453 return 0; 454 } 455 456 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 457 unsigned int virq, unsigned int nr_irqs) 458 { 459 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 460 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 461 462 mutex_lock(&port->lock); 463 464 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 465 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 466 d->hwirq); 467 else 468 __clear_bit(d->hwirq, port->msi_irq_in_use); 469 470 mutex_unlock(&port->lock); 471 472 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 473 } 474 475 static const struct irq_domain_ops msi_domain_ops = { 476 .alloc = mtk_pcie_irq_domain_alloc, 477 .free = mtk_pcie_irq_domain_free, 478 }; 479 480 static struct irq_chip mtk_msi_irq_chip = { 481 .name = "MTK PCIe MSI", 482 .irq_ack = irq_chip_ack_parent, 483 .irq_mask = pci_msi_mask_irq, 484 .irq_unmask = pci_msi_unmask_irq, 485 }; 486 487 static struct msi_domain_info mtk_msi_domain_info = { 488 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 489 MSI_FLAG_PCI_MSIX), 490 .chip = &mtk_msi_irq_chip, 491 }; 492 493 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 494 { 495 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); 496 497 mutex_init(&port->lock); 498 499 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, 500 &msi_domain_ops, port); 501 if (!port->inner_domain) { 502 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 503 return -ENOMEM; 504 } 505 506 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, 507 port->inner_domain); 508 if (!port->msi_domain) { 509 dev_err(port->pcie->dev, "failed to create MSI domain\n"); 510 irq_domain_remove(port->inner_domain); 511 return -ENOMEM; 512 } 513 514 return 0; 515 } 516 517 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 518 { 519 u32 val; 520 phys_addr_t msg_addr; 521 522 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 523 val = lower_32_bits(msg_addr); 524 writel(val, port->base + PCIE_IMSI_ADDR); 525 526 val = readl(port->base + PCIE_INT_MASK); 527 val &= ~MSI_MASK; 528 writel(val, port->base + PCIE_INT_MASK); 529 } 530 531 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 532 { 533 struct mtk_pcie_port *port, *tmp; 534 535 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 536 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 537 538 if (port->irq_domain) 539 irq_domain_remove(port->irq_domain); 540 541 if (IS_ENABLED(CONFIG_PCI_MSI)) { 542 if (port->msi_domain) 543 irq_domain_remove(port->msi_domain); 544 if (port->inner_domain) 545 irq_domain_remove(port->inner_domain); 546 } 547 548 irq_dispose_mapping(port->irq); 549 } 550 } 551 552 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 553 irq_hw_number_t hwirq) 554 { 555 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 556 irq_set_chip_data(irq, domain->host_data); 557 558 return 0; 559 } 560 561 static const struct irq_domain_ops intx_domain_ops = { 562 .map = mtk_pcie_intx_map, 563 }; 564 565 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 566 struct device_node *node) 567 { 568 struct device *dev = port->pcie->dev; 569 struct device_node *pcie_intc_node; 570 int ret; 571 572 /* Setup INTx */ 573 pcie_intc_node = of_get_next_child(node, NULL); 574 if (!pcie_intc_node) { 575 dev_err(dev, "no PCIe Intc node found\n"); 576 return -ENODEV; 577 } 578 579 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 580 &intx_domain_ops, port); 581 if (!port->irq_domain) { 582 dev_err(dev, "failed to get INTx IRQ domain\n"); 583 return -ENODEV; 584 } 585 586 if (IS_ENABLED(CONFIG_PCI_MSI)) { 587 ret = mtk_pcie_allocate_msi_domains(port); 588 if (ret) 589 return ret; 590 } 591 592 return 0; 593 } 594 595 static void mtk_pcie_intr_handler(struct irq_desc *desc) 596 { 597 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 598 struct irq_chip *irqchip = irq_desc_get_chip(desc); 599 unsigned long status; 600 u32 virq; 601 u32 bit = INTX_SHIFT; 602 603 chained_irq_enter(irqchip, desc); 604 605 status = readl(port->base + PCIE_INT_STATUS); 606 if (status & INTX_MASK) { 607 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 608 /* Clear the INTx */ 609 writel(1 << bit, port->base + PCIE_INT_STATUS); 610 virq = irq_find_mapping(port->irq_domain, 611 bit - INTX_SHIFT); 612 generic_handle_irq(virq); 613 } 614 } 615 616 if (IS_ENABLED(CONFIG_PCI_MSI)) { 617 if (status & MSI_STATUS){ 618 unsigned long imsi_status; 619 620 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 621 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { 622 virq = irq_find_mapping(port->inner_domain, bit); 623 generic_handle_irq(virq); 624 } 625 } 626 /* Clear MSI interrupt status */ 627 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 628 } 629 } 630 631 chained_irq_exit(irqchip, desc); 632 633 return; 634 } 635 636 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 637 struct device_node *node) 638 { 639 struct mtk_pcie *pcie = port->pcie; 640 struct device *dev = pcie->dev; 641 struct platform_device *pdev = to_platform_device(dev); 642 int err; 643 644 err = mtk_pcie_init_irq_domain(port, node); 645 if (err) { 646 dev_err(dev, "failed to init PCIe IRQ domain\n"); 647 return err; 648 } 649 650 port->irq = platform_get_irq(pdev, port->slot); 651 irq_set_chained_handler_and_data(port->irq, 652 mtk_pcie_intr_handler, port); 653 654 return 0; 655 } 656 657 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 658 { 659 struct mtk_pcie *pcie = port->pcie; 660 struct resource *mem = &pcie->mem; 661 const struct mtk_pcie_soc *soc = port->pcie->soc; 662 u32 val; 663 int err; 664 665 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 666 if (pcie->base) { 667 val = readl(pcie->base + PCIE_SYS_CFG_V2); 668 val |= PCIE_CSR_LTSSM_EN(port->slot) | 669 PCIE_CSR_ASPM_L1_EN(port->slot); 670 writel(val, pcie->base + PCIE_SYS_CFG_V2); 671 } 672 673 /* Assert all reset signals */ 674 writel(0, port->base + PCIE_RST_CTRL); 675 676 /* 677 * Enable PCIe link down reset, if link status changed from link up to 678 * link down, this will reset MAC control registers and configuration 679 * space. 680 */ 681 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 682 683 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 684 val = readl(port->base + PCIE_RST_CTRL); 685 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 686 PCIE_MAC_SRSTB | PCIE_CRSTB; 687 writel(val, port->base + PCIE_RST_CTRL); 688 689 /* Set up vendor ID and class code */ 690 if (soc->need_fix_class_id) { 691 val = PCI_VENDOR_ID_MEDIATEK; 692 writew(val, port->base + PCIE_CONF_VEND_ID); 693 694 val = PCI_CLASS_BRIDGE_PCI; 695 writew(val, port->base + PCIE_CONF_CLASS_ID); 696 } 697 698 /* 100ms timeout value should be enough for Gen1/2 training */ 699 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 700 !!(val & PCIE_PORT_LINKUP_V2), 20, 701 100 * USEC_PER_MSEC); 702 if (err) 703 return -ETIMEDOUT; 704 705 /* Set INTx mask */ 706 val = readl(port->base + PCIE_INT_MASK); 707 val &= ~INTX_MASK; 708 writel(val, port->base + PCIE_INT_MASK); 709 710 if (IS_ENABLED(CONFIG_PCI_MSI)) 711 mtk_pcie_enable_msi(port); 712 713 /* Set AHB to PCIe translation windows */ 714 val = lower_32_bits(mem->start) | 715 AHB2PCIE_SIZE(fls(resource_size(mem))); 716 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 717 718 val = upper_32_bits(mem->start); 719 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 720 721 /* Set PCIe to AXI translation memory space.*/ 722 val = PCIE2AHB_SIZE | WIN_ENABLE; 723 writel(val, port->base + PCIE_AXI_WINDOW0); 724 725 return 0; 726 } 727 728 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 729 unsigned int devfn, int where) 730 { 731 struct mtk_pcie *pcie = bus->sysdata; 732 733 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 734 bus->number), pcie->base + PCIE_CFG_ADDR); 735 736 return pcie->base + PCIE_CFG_DATA + (where & 3); 737 } 738 739 static struct pci_ops mtk_pcie_ops = { 740 .map_bus = mtk_pcie_map_bus, 741 .read = pci_generic_config_read, 742 .write = pci_generic_config_write, 743 }; 744 745 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 746 { 747 struct mtk_pcie *pcie = port->pcie; 748 u32 func = PCI_FUNC(port->slot << 3); 749 u32 slot = PCI_SLOT(port->slot << 3); 750 u32 val; 751 int err; 752 753 /* assert port PERST_N */ 754 val = readl(pcie->base + PCIE_SYS_CFG); 755 val |= PCIE_PORT_PERST(port->slot); 756 writel(val, pcie->base + PCIE_SYS_CFG); 757 758 /* de-assert port PERST_N */ 759 val = readl(pcie->base + PCIE_SYS_CFG); 760 val &= ~PCIE_PORT_PERST(port->slot); 761 writel(val, pcie->base + PCIE_SYS_CFG); 762 763 /* 100ms timeout value should be enough for Gen1/2 training */ 764 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 765 !!(val & PCIE_PORT_LINKUP), 20, 766 100 * USEC_PER_MSEC); 767 if (err) 768 return -ETIMEDOUT; 769 770 /* enable interrupt */ 771 val = readl(pcie->base + PCIE_INT_ENABLE); 772 val |= PCIE_PORT_INT_EN(port->slot); 773 writel(val, pcie->base + PCIE_INT_ENABLE); 774 775 /* map to all DDR region. We need to set it before cfg operation. */ 776 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 777 port->base + PCIE_BAR0_SETUP); 778 779 /* configure class code and revision ID */ 780 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 781 782 /* configure FC credit */ 783 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 784 pcie->base + PCIE_CFG_ADDR); 785 val = readl(pcie->base + PCIE_CFG_DATA); 786 val &= ~PCIE_FC_CREDIT_MASK; 787 val |= PCIE_FC_CREDIT_VAL(0x806c); 788 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 789 pcie->base + PCIE_CFG_ADDR); 790 writel(val, pcie->base + PCIE_CFG_DATA); 791 792 /* configure RC FTS number to 250 when it leaves L0s */ 793 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 794 pcie->base + PCIE_CFG_ADDR); 795 val = readl(pcie->base + PCIE_CFG_DATA); 796 val &= ~PCIE_FTS_NUM_MASK; 797 val |= PCIE_FTS_NUM_L0(0x50); 798 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 799 pcie->base + PCIE_CFG_ADDR); 800 writel(val, pcie->base + PCIE_CFG_DATA); 801 802 return 0; 803 } 804 805 static void mtk_pcie_enable_port(struct mtk_pcie_port *port) 806 { 807 struct mtk_pcie *pcie = port->pcie; 808 struct device *dev = pcie->dev; 809 int err; 810 811 err = clk_prepare_enable(port->sys_ck); 812 if (err) { 813 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 814 goto err_sys_clk; 815 } 816 817 err = clk_prepare_enable(port->ahb_ck); 818 if (err) { 819 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 820 goto err_ahb_clk; 821 } 822 823 err = clk_prepare_enable(port->aux_ck); 824 if (err) { 825 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 826 goto err_aux_clk; 827 } 828 829 err = clk_prepare_enable(port->axi_ck); 830 if (err) { 831 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 832 goto err_axi_clk; 833 } 834 835 err = clk_prepare_enable(port->obff_ck); 836 if (err) { 837 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 838 goto err_obff_clk; 839 } 840 841 err = clk_prepare_enable(port->pipe_ck); 842 if (err) { 843 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 844 goto err_pipe_clk; 845 } 846 847 reset_control_assert(port->reset); 848 reset_control_deassert(port->reset); 849 850 err = phy_init(port->phy); 851 if (err) { 852 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 853 goto err_phy_init; 854 } 855 856 err = phy_power_on(port->phy); 857 if (err) { 858 dev_err(dev, "failed to power on port%d phy\n", port->slot); 859 goto err_phy_on; 860 } 861 862 if (!pcie->soc->startup(port)) 863 return; 864 865 dev_info(dev, "Port%d link down\n", port->slot); 866 867 phy_power_off(port->phy); 868 err_phy_on: 869 phy_exit(port->phy); 870 err_phy_init: 871 clk_disable_unprepare(port->pipe_ck); 872 err_pipe_clk: 873 clk_disable_unprepare(port->obff_ck); 874 err_obff_clk: 875 clk_disable_unprepare(port->axi_ck); 876 err_axi_clk: 877 clk_disable_unprepare(port->aux_ck); 878 err_aux_clk: 879 clk_disable_unprepare(port->ahb_ck); 880 err_ahb_clk: 881 clk_disable_unprepare(port->sys_ck); 882 err_sys_clk: 883 mtk_pcie_port_free(port); 884 } 885 886 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 887 struct device_node *node, 888 int slot) 889 { 890 struct mtk_pcie_port *port; 891 struct resource *regs; 892 struct device *dev = pcie->dev; 893 struct platform_device *pdev = to_platform_device(dev); 894 char name[10]; 895 int err; 896 897 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 898 if (!port) 899 return -ENOMEM; 900 901 snprintf(name, sizeof(name), "port%d", slot); 902 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 903 port->base = devm_ioremap_resource(dev, regs); 904 if (IS_ERR(port->base)) { 905 dev_err(dev, "failed to map port%d base\n", slot); 906 return PTR_ERR(port->base); 907 } 908 909 snprintf(name, sizeof(name), "sys_ck%d", slot); 910 port->sys_ck = devm_clk_get(dev, name); 911 if (IS_ERR(port->sys_ck)) { 912 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 913 return PTR_ERR(port->sys_ck); 914 } 915 916 /* sys_ck might be divided into the following parts in some chips */ 917 snprintf(name, sizeof(name), "ahb_ck%d", slot); 918 port->ahb_ck = devm_clk_get(dev, name); 919 if (IS_ERR(port->ahb_ck)) { 920 if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER) 921 return -EPROBE_DEFER; 922 923 port->ahb_ck = NULL; 924 } 925 926 snprintf(name, sizeof(name), "axi_ck%d", slot); 927 port->axi_ck = devm_clk_get(dev, name); 928 if (IS_ERR(port->axi_ck)) { 929 if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER) 930 return -EPROBE_DEFER; 931 932 port->axi_ck = NULL; 933 } 934 935 snprintf(name, sizeof(name), "aux_ck%d", slot); 936 port->aux_ck = devm_clk_get(dev, name); 937 if (IS_ERR(port->aux_ck)) { 938 if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER) 939 return -EPROBE_DEFER; 940 941 port->aux_ck = NULL; 942 } 943 944 snprintf(name, sizeof(name), "obff_ck%d", slot); 945 port->obff_ck = devm_clk_get(dev, name); 946 if (IS_ERR(port->obff_ck)) { 947 if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER) 948 return -EPROBE_DEFER; 949 950 port->obff_ck = NULL; 951 } 952 953 snprintf(name, sizeof(name), "pipe_ck%d", slot); 954 port->pipe_ck = devm_clk_get(dev, name); 955 if (IS_ERR(port->pipe_ck)) { 956 if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER) 957 return -EPROBE_DEFER; 958 959 port->pipe_ck = NULL; 960 } 961 962 snprintf(name, sizeof(name), "pcie-rst%d", slot); 963 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 964 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 965 return PTR_ERR(port->reset); 966 967 /* some platforms may use default PHY setting */ 968 snprintf(name, sizeof(name), "pcie-phy%d", slot); 969 port->phy = devm_phy_optional_get(dev, name); 970 if (IS_ERR(port->phy)) 971 return PTR_ERR(port->phy); 972 973 port->slot = slot; 974 port->pcie = pcie; 975 976 if (pcie->soc->setup_irq) { 977 err = pcie->soc->setup_irq(port, node); 978 if (err) 979 return err; 980 } 981 982 INIT_LIST_HEAD(&port->list); 983 list_add_tail(&port->list, &pcie->ports); 984 985 return 0; 986 } 987 988 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 989 { 990 struct device *dev = pcie->dev; 991 struct platform_device *pdev = to_platform_device(dev); 992 struct resource *regs; 993 int err; 994 995 /* get shared registers, which are optional */ 996 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 997 if (regs) { 998 pcie->base = devm_ioremap_resource(dev, regs); 999 if (IS_ERR(pcie->base)) { 1000 dev_err(dev, "failed to map shared register\n"); 1001 return PTR_ERR(pcie->base); 1002 } 1003 } 1004 1005 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1006 if (IS_ERR(pcie->free_ck)) { 1007 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1008 return -EPROBE_DEFER; 1009 1010 pcie->free_ck = NULL; 1011 } 1012 1013 pm_runtime_enable(dev); 1014 pm_runtime_get_sync(dev); 1015 1016 /* enable top level clock */ 1017 err = clk_prepare_enable(pcie->free_ck); 1018 if (err) { 1019 dev_err(dev, "failed to enable free_ck\n"); 1020 goto err_free_ck; 1021 } 1022 1023 return 0; 1024 1025 err_free_ck: 1026 pm_runtime_put_sync(dev); 1027 pm_runtime_disable(dev); 1028 1029 return err; 1030 } 1031 1032 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1033 { 1034 struct device *dev = pcie->dev; 1035 struct device_node *node = dev->of_node, *child; 1036 struct mtk_pcie_port *port, *tmp; 1037 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1038 struct list_head *windows = &host->windows; 1039 struct resource_entry *win, *tmp_win; 1040 resource_size_t io_base; 1041 int err; 1042 1043 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 1044 windows, &io_base); 1045 if (err) 1046 return err; 1047 1048 err = devm_request_pci_bus_resources(dev, windows); 1049 if (err < 0) 1050 return err; 1051 1052 /* Get the I/O and memory ranges from DT */ 1053 resource_list_for_each_entry_safe(win, tmp_win, windows) { 1054 switch (resource_type(win->res)) { 1055 case IORESOURCE_IO: 1056 err = devm_pci_remap_iospace(dev, win->res, io_base); 1057 if (err) { 1058 dev_warn(dev, "error %d: failed to map resource %pR\n", 1059 err, win->res); 1060 resource_list_destroy_entry(win); 1061 } 1062 break; 1063 case IORESOURCE_MEM: 1064 memcpy(&pcie->mem, win->res, sizeof(*win->res)); 1065 pcie->mem.name = "non-prefetchable"; 1066 break; 1067 case IORESOURCE_BUS: 1068 pcie->busnr = win->res->start; 1069 break; 1070 } 1071 } 1072 1073 for_each_available_child_of_node(node, child) { 1074 int slot; 1075 1076 err = of_pci_get_devfn(child); 1077 if (err < 0) { 1078 dev_err(dev, "failed to parse devfn: %d\n", err); 1079 return err; 1080 } 1081 1082 slot = PCI_SLOT(err); 1083 1084 err = mtk_pcie_parse_port(pcie, child, slot); 1085 if (err) 1086 return err; 1087 } 1088 1089 err = mtk_pcie_subsys_powerup(pcie); 1090 if (err) 1091 return err; 1092 1093 /* enable each port, and then check link status */ 1094 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1095 mtk_pcie_enable_port(port); 1096 1097 /* power down PCIe subsys if slots are all empty (link down) */ 1098 if (list_empty(&pcie->ports)) 1099 mtk_pcie_subsys_powerdown(pcie); 1100 1101 return 0; 1102 } 1103 1104 static int mtk_pcie_probe(struct platform_device *pdev) 1105 { 1106 struct device *dev = &pdev->dev; 1107 struct mtk_pcie *pcie; 1108 struct pci_host_bridge *host; 1109 int err; 1110 1111 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1112 if (!host) 1113 return -ENOMEM; 1114 1115 pcie = pci_host_bridge_priv(host); 1116 1117 pcie->dev = dev; 1118 pcie->soc = of_device_get_match_data(dev); 1119 platform_set_drvdata(pdev, pcie); 1120 INIT_LIST_HEAD(&pcie->ports); 1121 1122 err = mtk_pcie_setup(pcie); 1123 if (err) 1124 return err; 1125 1126 host->busnr = pcie->busnr; 1127 host->dev.parent = pcie->dev; 1128 host->ops = pcie->soc->ops; 1129 host->map_irq = of_irq_parse_and_map_pci; 1130 host->swizzle_irq = pci_common_swizzle; 1131 host->sysdata = pcie; 1132 1133 err = pci_host_probe(host); 1134 if (err) 1135 goto put_resources; 1136 1137 return 0; 1138 1139 put_resources: 1140 if (!list_empty(&pcie->ports)) 1141 mtk_pcie_put_resources(pcie); 1142 1143 return err; 1144 } 1145 1146 1147 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1148 { 1149 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1150 struct list_head *windows = &host->windows; 1151 1152 pci_free_resource_list(windows); 1153 } 1154 1155 static int mtk_pcie_remove(struct platform_device *pdev) 1156 { 1157 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1158 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1159 1160 pci_stop_root_bus(host->bus); 1161 pci_remove_root_bus(host->bus); 1162 mtk_pcie_free_resources(pcie); 1163 1164 mtk_pcie_irq_teardown(pcie); 1165 1166 mtk_pcie_put_resources(pcie); 1167 1168 return 0; 1169 } 1170 1171 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) 1172 { 1173 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1174 struct mtk_pcie_port *port; 1175 1176 if (list_empty(&pcie->ports)) 1177 return 0; 1178 1179 list_for_each_entry(port, &pcie->ports, list) { 1180 clk_disable_unprepare(port->pipe_ck); 1181 clk_disable_unprepare(port->obff_ck); 1182 clk_disable_unprepare(port->axi_ck); 1183 clk_disable_unprepare(port->aux_ck); 1184 clk_disable_unprepare(port->ahb_ck); 1185 clk_disable_unprepare(port->sys_ck); 1186 phy_power_off(port->phy); 1187 phy_exit(port->phy); 1188 } 1189 1190 clk_disable_unprepare(pcie->free_ck); 1191 1192 return 0; 1193 } 1194 1195 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) 1196 { 1197 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1198 struct mtk_pcie_port *port, *tmp; 1199 1200 if (list_empty(&pcie->ports)) 1201 return 0; 1202 1203 clk_prepare_enable(pcie->free_ck); 1204 1205 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1206 mtk_pcie_enable_port(port); 1207 1208 /* In case of EP was removed while system suspend. */ 1209 if (list_empty(&pcie->ports)) 1210 clk_disable_unprepare(pcie->free_ck); 1211 1212 return 0; 1213 } 1214 1215 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1216 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1217 mtk_pcie_resume_noirq) 1218 }; 1219 1220 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1221 .ops = &mtk_pcie_ops, 1222 .startup = mtk_pcie_startup_port, 1223 }; 1224 1225 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1226 .ops = &mtk_pcie_ops_v2, 1227 .startup = mtk_pcie_startup_port_v2, 1228 .setup_irq = mtk_pcie_setup_irq, 1229 }; 1230 1231 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1232 .need_fix_class_id = true, 1233 .ops = &mtk_pcie_ops_v2, 1234 .startup = mtk_pcie_startup_port_v2, 1235 .setup_irq = mtk_pcie_setup_irq, 1236 }; 1237 1238 static const struct of_device_id mtk_pcie_ids[] = { 1239 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1240 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1241 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1242 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1243 {}, 1244 }; 1245 1246 static struct platform_driver mtk_pcie_driver = { 1247 .probe = mtk_pcie_probe, 1248 .remove = mtk_pcie_remove, 1249 .driver = { 1250 .name = "mtk-pcie", 1251 .of_match_table = mtk_pcie_ids, 1252 .suppress_bind_attrs = true, 1253 .pm = &mtk_pcie_pm_ops, 1254 }, 1255 }; 1256 module_platform_driver(mtk_pcie_driver); 1257 MODULE_LICENSE("GPL v2"); 1258