1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2015 Broadcom Corporation
4  */
5 
6 #include <linux/interrupt.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/msi.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci.h>
13 
14 #include "pcie-iproc.h"
15 
16 #define IPROC_MSI_INTR_EN_SHIFT        11
17 #define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
18 #define IPROC_MSI_INT_N_EVENT_SHIFT    1
19 #define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
20 #define IPROC_MSI_EQ_EN_SHIFT          0
21 #define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
22 
23 #define IPROC_MSI_EQ_MASK              0x3f
24 
25 /* Max number of GIC interrupts */
26 #define NR_HW_IRQS                     6
27 
28 /* Number of entries in each event queue */
29 #define EQ_LEN                         64
30 
31 /* Size of each event queue memory region */
32 #define EQ_MEM_REGION_SIZE             SZ_4K
33 
34 /* Size of each MSI address region */
35 #define MSI_MEM_REGION_SIZE            SZ_4K
36 
37 enum iproc_msi_reg {
38 	IPROC_MSI_EQ_PAGE = 0,
39 	IPROC_MSI_EQ_PAGE_UPPER,
40 	IPROC_MSI_PAGE,
41 	IPROC_MSI_PAGE_UPPER,
42 	IPROC_MSI_CTRL,
43 	IPROC_MSI_EQ_HEAD,
44 	IPROC_MSI_EQ_TAIL,
45 	IPROC_MSI_INTS_EN,
46 	IPROC_MSI_REG_SIZE,
47 };
48 
49 struct iproc_msi;
50 
51 /**
52  * iProc MSI group
53  *
54  * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
55  * event queue.
56  *
57  * @msi: pointer to iProc MSI data
58  * @gic_irq: GIC interrupt
59  * @eq: Event queue number
60  */
61 struct iproc_msi_grp {
62 	struct iproc_msi *msi;
63 	int gic_irq;
64 	unsigned int eq;
65 };
66 
67 /**
68  * iProc event queue based MSI
69  *
70  * Only meant to be used on platforms without MSI support integrated into the
71  * GIC.
72  *
73  * @pcie: pointer to iProc PCIe data
74  * @reg_offsets: MSI register offsets
75  * @grps: MSI groups
76  * @nr_irqs: number of total interrupts connected to GIC
77  * @nr_cpus: number of toal CPUs
78  * @has_inten_reg: indicates the MSI interrupt enable register needs to be
79  * set explicitly (required for some legacy platforms)
80  * @bitmap: MSI vector bitmap
81  * @bitmap_lock: lock to protect access to the MSI bitmap
82  * @nr_msi_vecs: total number of MSI vectors
83  * @inner_domain: inner IRQ domain
84  * @msi_domain: MSI IRQ domain
85  * @nr_eq_region: required number of 4K aligned memory region for MSI event
86  * queues
87  * @nr_msi_region: required number of 4K aligned address region for MSI posted
88  * writes
89  * @eq_cpu: pointer to allocated memory region for MSI event queues
90  * @eq_dma: DMA address of MSI event queues
91  * @msi_addr: MSI address
92  */
93 struct iproc_msi {
94 	struct iproc_pcie *pcie;
95 	const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
96 	struct iproc_msi_grp *grps;
97 	int nr_irqs;
98 	int nr_cpus;
99 	bool has_inten_reg;
100 	unsigned long *bitmap;
101 	struct mutex bitmap_lock;
102 	unsigned int nr_msi_vecs;
103 	struct irq_domain *inner_domain;
104 	struct irq_domain *msi_domain;
105 	unsigned int nr_eq_region;
106 	unsigned int nr_msi_region;
107 	void *eq_cpu;
108 	dma_addr_t eq_dma;
109 	phys_addr_t msi_addr;
110 };
111 
112 static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
113 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
114 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
115 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
116 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
117 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
118 	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
119 };
120 
121 static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
122 	{ 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
123 	{ 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
124 	{ 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
125 	{ 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
126 };
127 
128 static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
129 				     enum iproc_msi_reg reg,
130 				     unsigned int eq)
131 {
132 	struct iproc_pcie *pcie = msi->pcie;
133 
134 	return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
135 }
136 
137 static inline void iproc_msi_write_reg(struct iproc_msi *msi,
138 				       enum iproc_msi_reg reg,
139 				       int eq, u32 val)
140 {
141 	struct iproc_pcie *pcie = msi->pcie;
142 
143 	writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
144 }
145 
146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
147 {
148 	return (hwirq % msi->nr_irqs);
149 }
150 
151 static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
152 						 unsigned long hwirq)
153 {
154 	if (msi->nr_msi_region > 1)
155 		return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
156 	else
157 		return hwirq_to_group(msi, hwirq) * sizeof(u32);
158 }
159 
160 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
161 {
162 	if (msi->nr_eq_region > 1)
163 		return eq * EQ_MEM_REGION_SIZE;
164 	else
165 		return eq * EQ_LEN * sizeof(u32);
166 }
167 
168 static struct irq_chip iproc_msi_irq_chip = {
169 	.name = "iProc-MSI",
170 };
171 
172 static struct msi_domain_info iproc_msi_domain_info = {
173 	.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
174 		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
175 	.chip = &iproc_msi_irq_chip,
176 };
177 
178 /*
179  * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
180  * dedicated event queue.  Each MSI group can support up to 64 MSI vectors.
181  *
182  * The number of MSI groups varies between different iProc SoCs.  The total
183  * number of CPU cores also varies.  To support MSI IRQ affinity, we
184  * distribute GIC interrupts across all available CPUs.  MSI vector is moved
185  * from one GIC interrupt to another to steer to the target CPU.
186  *
187  * Assuming:
188  * - the number of MSI groups is M
189  * - the number of CPU cores is N
190  * - M is always a multiple of N
191  *
192  * Total number of raw MSI vectors = M * 64
193  * Total number of supported MSI vectors = (M * 64) / N
194  */
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
196 {
197 	return (hwirq % msi->nr_cpus);
198 }
199 
200 static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
201 						     unsigned long hwirq)
202 {
203 	return (hwirq - hwirq_to_cpu(msi, hwirq));
204 }
205 
206 static int iproc_msi_irq_set_affinity(struct irq_data *data,
207 				      const struct cpumask *mask, bool force)
208 {
209 	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
210 	int target_cpu = cpumask_first(mask);
211 	int curr_cpu;
212 	int ret;
213 
214 	curr_cpu = hwirq_to_cpu(msi, data->hwirq);
215 	if (curr_cpu == target_cpu)
216 		ret = IRQ_SET_MASK_OK_DONE;
217 	else {
218 		/* steer MSI to the target CPU */
219 		data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
220 		ret = IRQ_SET_MASK_OK;
221 	}
222 
223 	irq_data_update_effective_affinity(data, cpumask_of(target_cpu));
224 
225 	return ret;
226 }
227 
228 static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
229 					  struct msi_msg *msg)
230 {
231 	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
232 	dma_addr_t addr;
233 
234 	addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
235 	msg->address_lo = lower_32_bits(addr);
236 	msg->address_hi = upper_32_bits(addr);
237 	msg->data = data->hwirq << 5;
238 }
239 
240 static struct irq_chip iproc_msi_bottom_irq_chip = {
241 	.name = "MSI",
242 	.irq_set_affinity = iproc_msi_irq_set_affinity,
243 	.irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
244 };
245 
246 static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
247 				      unsigned int virq, unsigned int nr_irqs,
248 				      void *args)
249 {
250 	struct iproc_msi *msi = domain->host_data;
251 	int hwirq, i;
252 
253 	mutex_lock(&msi->bitmap_lock);
254 
255 	/* Allocate 'nr_cpus' number of MSI vectors each time */
256 	hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
257 					   msi->nr_cpus, 0);
258 	if (hwirq < msi->nr_msi_vecs) {
259 		bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
260 	} else {
261 		mutex_unlock(&msi->bitmap_lock);
262 		return -ENOSPC;
263 	}
264 
265 	mutex_unlock(&msi->bitmap_lock);
266 
267 	for (i = 0; i < nr_irqs; i++) {
268 		irq_domain_set_info(domain, virq + i, hwirq + i,
269 				    &iproc_msi_bottom_irq_chip,
270 				    domain->host_data, handle_simple_irq,
271 				    NULL, NULL);
272 	}
273 
274 	return hwirq;
275 }
276 
277 static void iproc_msi_irq_domain_free(struct irq_domain *domain,
278 				      unsigned int virq, unsigned int nr_irqs)
279 {
280 	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
281 	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
282 	unsigned int hwirq;
283 
284 	mutex_lock(&msi->bitmap_lock);
285 
286 	hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
287 	bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
288 
289 	mutex_unlock(&msi->bitmap_lock);
290 
291 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
292 }
293 
294 static const struct irq_domain_ops msi_domain_ops = {
295 	.alloc = iproc_msi_irq_domain_alloc,
296 	.free = iproc_msi_irq_domain_free,
297 };
298 
299 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
300 {
301 	u32 __iomem *msg;
302 	u32 hwirq;
303 	unsigned int offs;
304 
305 	offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
306 	msg = (u32 __iomem *)(msi->eq_cpu + offs);
307 	hwirq = readl(msg);
308 	hwirq = (hwirq >> 5) + (hwirq & 0x1f);
309 
310 	/*
311 	 * Since we have multiple hwirq mapped to a single MSI vector,
312 	 * now we need to derive the hwirq at CPU0.  It can then be used to
313 	 * mapped back to virq.
314 	 */
315 	return hwirq_to_canonical_hwirq(msi, hwirq);
316 }
317 
318 static void iproc_msi_handler(struct irq_desc *desc)
319 {
320 	struct irq_chip *chip = irq_desc_get_chip(desc);
321 	struct iproc_msi_grp *grp;
322 	struct iproc_msi *msi;
323 	u32 eq, head, tail, nr_events;
324 	unsigned long hwirq;
325 	int virq;
326 
327 	chained_irq_enter(chip, desc);
328 
329 	grp = irq_desc_get_handler_data(desc);
330 	msi = grp->msi;
331 	eq = grp->eq;
332 
333 	/*
334 	 * iProc MSI event queue is tracked by head and tail pointers.  Head
335 	 * pointer indicates the next entry (MSI data) to be consumed by SW in
336 	 * the queue and needs to be updated by SW.  iProc MSI core uses the
337 	 * tail pointer as the next data insertion point.
338 	 *
339 	 * Entries between head and tail pointers contain valid MSI data.  MSI
340 	 * data is guaranteed to be in the event queue memory before the tail
341 	 * pointer is updated by the iProc MSI core.
342 	 */
343 	head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
344 				  eq) & IPROC_MSI_EQ_MASK;
345 	do {
346 		tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
347 					  eq) & IPROC_MSI_EQ_MASK;
348 
349 		/*
350 		 * Figure out total number of events (MSI data) to be
351 		 * processed.
352 		 */
353 		nr_events = (tail < head) ?
354 			(EQ_LEN - (head - tail)) : (tail - head);
355 		if (!nr_events)
356 			break;
357 
358 		/* process all outstanding events */
359 		while (nr_events--) {
360 			hwirq = decode_msi_hwirq(msi, eq, head);
361 			virq = irq_find_mapping(msi->inner_domain, hwirq);
362 			generic_handle_irq(virq);
363 
364 			head++;
365 			head %= EQ_LEN;
366 		}
367 
368 		/*
369 		 * Now all outstanding events have been processed.  Update the
370 		 * head pointer.
371 		 */
372 		iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
373 
374 		/*
375 		 * Now go read the tail pointer again to see if there are new
376 		 * outstanding events that came in during the above window.
377 		 */
378 	} while (true);
379 
380 	chained_irq_exit(chip, desc);
381 }
382 
383 static void iproc_msi_enable(struct iproc_msi *msi)
384 {
385 	int i, eq;
386 	u32 val;
387 
388 	/* Program memory region for each event queue */
389 	for (i = 0; i < msi->nr_eq_region; i++) {
390 		dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
391 
392 		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
393 				    lower_32_bits(addr));
394 		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
395 				    upper_32_bits(addr));
396 	}
397 
398 	/* Program address region for MSI posted writes */
399 	for (i = 0; i < msi->nr_msi_region; i++) {
400 		phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
401 
402 		iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
403 				    lower_32_bits(addr));
404 		iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
405 				    upper_32_bits(addr));
406 	}
407 
408 	for (eq = 0; eq < msi->nr_irqs; eq++) {
409 		/* Enable MSI event queue */
410 		val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
411 			IPROC_MSI_EQ_EN;
412 		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
413 
414 		/*
415 		 * Some legacy platforms require the MSI interrupt enable
416 		 * register to be set explicitly.
417 		 */
418 		if (msi->has_inten_reg) {
419 			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
420 			val |= BIT(eq);
421 			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
422 		}
423 	}
424 }
425 
426 static void iproc_msi_disable(struct iproc_msi *msi)
427 {
428 	u32 eq, val;
429 
430 	for (eq = 0; eq < msi->nr_irqs; eq++) {
431 		if (msi->has_inten_reg) {
432 			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
433 			val &= ~BIT(eq);
434 			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
435 		}
436 
437 		val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
438 		val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
439 			 IPROC_MSI_EQ_EN);
440 		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
441 	}
442 }
443 
444 static int iproc_msi_alloc_domains(struct device_node *node,
445 				   struct iproc_msi *msi)
446 {
447 	msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
448 						  &msi_domain_ops, msi);
449 	if (!msi->inner_domain)
450 		return -ENOMEM;
451 
452 	msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
453 						    &iproc_msi_domain_info,
454 						    msi->inner_domain);
455 	if (!msi->msi_domain) {
456 		irq_domain_remove(msi->inner_domain);
457 		return -ENOMEM;
458 	}
459 
460 	return 0;
461 }
462 
463 static void iproc_msi_free_domains(struct iproc_msi *msi)
464 {
465 	if (msi->msi_domain)
466 		irq_domain_remove(msi->msi_domain);
467 
468 	if (msi->inner_domain)
469 		irq_domain_remove(msi->inner_domain);
470 }
471 
472 static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
473 {
474 	int i;
475 
476 	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
477 		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
478 						 NULL, NULL);
479 	}
480 }
481 
482 static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
483 {
484 	int i, ret;
485 	cpumask_var_t mask;
486 	struct iproc_pcie *pcie = msi->pcie;
487 
488 	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
489 		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
490 						 iproc_msi_handler,
491 						 &msi->grps[i]);
492 		/* Dedicate GIC interrupt to each CPU core */
493 		if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
494 			cpumask_clear(mask);
495 			cpumask_set_cpu(cpu, mask);
496 			ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
497 			if (ret)
498 				dev_err(pcie->dev,
499 					"failed to set affinity for IRQ%d\n",
500 					msi->grps[i].gic_irq);
501 			free_cpumask_var(mask);
502 		} else {
503 			dev_err(pcie->dev, "failed to alloc CPU mask\n");
504 			ret = -EINVAL;
505 		}
506 
507 		if (ret) {
508 			/* Free all configured/unconfigured IRQs */
509 			iproc_msi_irq_free(msi, cpu);
510 			return ret;
511 		}
512 	}
513 
514 	return 0;
515 }
516 
517 int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
518 {
519 	struct iproc_msi *msi;
520 	int i, ret;
521 	unsigned int cpu;
522 
523 	if (!of_device_is_compatible(node, "brcm,iproc-msi"))
524 		return -ENODEV;
525 
526 	if (!of_find_property(node, "msi-controller", NULL))
527 		return -ENODEV;
528 
529 	if (pcie->msi)
530 		return -EBUSY;
531 
532 	msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
533 	if (!msi)
534 		return -ENOMEM;
535 
536 	msi->pcie = pcie;
537 	pcie->msi = msi;
538 	msi->msi_addr = pcie->base_addr;
539 	mutex_init(&msi->bitmap_lock);
540 	msi->nr_cpus = num_possible_cpus();
541 
542 	msi->nr_irqs = of_irq_count(node);
543 	if (!msi->nr_irqs) {
544 		dev_err(pcie->dev, "found no MSI GIC interrupt\n");
545 		return -ENODEV;
546 	}
547 
548 	if (msi->nr_irqs > NR_HW_IRQS) {
549 		dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
550 			 msi->nr_irqs);
551 		msi->nr_irqs = NR_HW_IRQS;
552 	}
553 
554 	if (msi->nr_irqs < msi->nr_cpus) {
555 		dev_err(pcie->dev,
556 			"not enough GIC interrupts for MSI affinity\n");
557 		return -EINVAL;
558 	}
559 
560 	if (msi->nr_irqs % msi->nr_cpus != 0) {
561 		msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
562 		dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
563 			 msi->nr_irqs);
564 	}
565 
566 	switch (pcie->type) {
567 	case IPROC_PCIE_PAXB_BCMA:
568 	case IPROC_PCIE_PAXB:
569 		msi->reg_offsets = iproc_msi_reg_paxb;
570 		msi->nr_eq_region = 1;
571 		msi->nr_msi_region = 1;
572 		break;
573 	case IPROC_PCIE_PAXC:
574 		msi->reg_offsets = iproc_msi_reg_paxc;
575 		msi->nr_eq_region = msi->nr_irqs;
576 		msi->nr_msi_region = msi->nr_irqs;
577 		break;
578 	default:
579 		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
580 		return -EINVAL;
581 	}
582 
583 	if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
584 		msi->has_inten_reg = true;
585 
586 	msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
587 	msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
588 				   sizeof(*msi->bitmap), GFP_KERNEL);
589 	if (!msi->bitmap)
590 		return -ENOMEM;
591 
592 	msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
593 				 GFP_KERNEL);
594 	if (!msi->grps)
595 		return -ENOMEM;
596 
597 	for (i = 0; i < msi->nr_irqs; i++) {
598 		unsigned int irq = irq_of_parse_and_map(node, i);
599 
600 		if (!irq) {
601 			dev_err(pcie->dev, "unable to parse/map interrupt\n");
602 			ret = -ENODEV;
603 			goto free_irqs;
604 		}
605 		msi->grps[i].gic_irq = irq;
606 		msi->grps[i].msi = msi;
607 		msi->grps[i].eq = i;
608 	}
609 
610 	/* Reserve memory for event queue and make sure memories are zeroed */
611 	msi->eq_cpu = dma_alloc_coherent(pcie->dev,
612 					 msi->nr_eq_region * EQ_MEM_REGION_SIZE,
613 					 &msi->eq_dma, GFP_KERNEL);
614 	if (!msi->eq_cpu) {
615 		ret = -ENOMEM;
616 		goto free_irqs;
617 	}
618 
619 	ret = iproc_msi_alloc_domains(node, msi);
620 	if (ret) {
621 		dev_err(pcie->dev, "failed to create MSI domains\n");
622 		goto free_eq_dma;
623 	}
624 
625 	for_each_online_cpu(cpu) {
626 		ret = iproc_msi_irq_setup(msi, cpu);
627 		if (ret)
628 			goto free_msi_irq;
629 	}
630 
631 	iproc_msi_enable(msi);
632 
633 	return 0;
634 
635 free_msi_irq:
636 	for_each_online_cpu(cpu)
637 		iproc_msi_irq_free(msi, cpu);
638 	iproc_msi_free_domains(msi);
639 
640 free_eq_dma:
641 	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
642 			  msi->eq_cpu, msi->eq_dma);
643 
644 free_irqs:
645 	for (i = 0; i < msi->nr_irqs; i++) {
646 		if (msi->grps[i].gic_irq)
647 			irq_dispose_mapping(msi->grps[i].gic_irq);
648 	}
649 	pcie->msi = NULL;
650 	return ret;
651 }
652 EXPORT_SYMBOL(iproc_msi_init);
653 
654 void iproc_msi_exit(struct iproc_pcie *pcie)
655 {
656 	struct iproc_msi *msi = pcie->msi;
657 	unsigned int i, cpu;
658 
659 	if (!msi)
660 		return;
661 
662 	iproc_msi_disable(msi);
663 
664 	for_each_online_cpu(cpu)
665 		iproc_msi_irq_free(msi, cpu);
666 
667 	iproc_msi_free_domains(msi);
668 
669 	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
670 			  msi->eq_cpu, msi->eq_dma);
671 
672 	for (i = 0; i < msi->nr_irqs; i++) {
673 		if (msi->grps[i].gic_irq)
674 			irq_dispose_mapping(msi->grps[i].gic_irq);
675 	}
676 }
677 EXPORT_SYMBOL(iproc_msi_exit);
678