1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2009 - 2019 Broadcom */ 3 4 #include <linux/bitfield.h> 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/compiler.h> 8 #include <linux/delay.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/log2.h> 18 #include <linux/module.h> 19 #include <linux/msi.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_pci.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/pci-ecam.h> 26 #include <linux/printk.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/sizes.h> 30 #include <linux/slab.h> 31 #include <linux/string.h> 32 #include <linux/types.h> 33 34 #include "../pci.h" 35 36 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ 37 #define BRCM_PCIE_CAP_REGS 0x00ac 38 39 /* Broadcom STB PCIe Register Offsets */ 40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc 42 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 43 44 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c 45 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff 46 47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc 48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 49 50 #define PCIE_RC_DL_MDIO_ADDR 0x1100 51 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 52 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 53 54 #define PCIE_MISC_MISC_CTRL 0x4008 55 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 56 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 57 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 58 59 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 60 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000 61 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f 62 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK 63 64 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c 65 #define PCIE_MEM_WIN0_LO(win) \ 66 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8) 67 68 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 69 #define PCIE_MEM_WIN0_HI(win) \ 70 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) 71 72 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c 73 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f 74 75 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 76 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f 77 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 78 79 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c 80 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f 81 82 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 83 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 84 85 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c 86 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540 87 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540 88 89 #define PCIE_MISC_PCIE_CTRL 0x4064 90 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 91 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 92 93 #define PCIE_MISC_PCIE_STATUS 0x4068 94 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 95 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 96 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 97 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 98 99 #define PCIE_MISC_REVISION 0x406c 100 #define BRCM_PCIE_HW_REV_33 0x0303 101 #define BRCM_PCIE_HW_REV_3_20 0x0320 102 103 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 105 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 106 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \ 107 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) 108 109 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 110 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff 111 #define PCIE_MEM_WIN0_BASE_HI(win) \ 112 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) 113 114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 115 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff 116 #define PCIE_MEM_WIN0_LIMIT_HI(win) \ 117 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) 118 119 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 120 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 121 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 122 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 123 124 125 #define PCIE_INTR2_CPU_BASE 0x4300 126 #define PCIE_MSI_INTR2_BASE 0x4500 127 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ 128 #define MSI_INT_STATUS 0x0 129 #define MSI_INT_CLR 0x8 130 #define MSI_INT_MASK_SET 0x10 131 #define MSI_INT_MASK_CLR 0x14 132 133 #define PCIE_EXT_CFG_DATA 0x8000 134 #define PCIE_EXT_CFG_INDEX 0x9000 135 136 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 137 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 138 139 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2 140 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1 141 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1 142 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0 143 144 /* PCIe parameters */ 145 #define BRCM_NUM_PCIE_OUT_WINS 0x4 146 #define BRCM_INT_PCI_MSI_NR 32 147 #define BRCM_INT_PCI_MSI_LEGACY_NR 8 148 #define BRCM_INT_PCI_MSI_SHIFT 0 149 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0) 150 #define BRCM_INT_PCI_MSI_LEGACY_MASK GENMASK(31, \ 151 32 - BRCM_INT_PCI_MSI_LEGACY_NR) 152 153 /* MSI target addresses */ 154 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL 155 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL 156 157 /* MDIO registers */ 158 #define MDIO_PORT0 0x0 159 #define MDIO_DATA_MASK 0x7fffffff 160 #define MDIO_PORT_MASK 0xf0000 161 #define MDIO_REGAD_MASK 0xffff 162 #define MDIO_CMD_MASK 0xfff00000 163 #define MDIO_CMD_READ 0x1 164 #define MDIO_CMD_WRITE 0x0 165 #define MDIO_DATA_DONE_MASK 0x80000000 166 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) 167 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) 168 #define SSC_REGS_ADDR 0x1100 169 #define SET_ADDR_OFFSET 0x1f 170 #define SSC_CNTL_OFFSET 0x2 171 #define SSC_CNTL_OVRD_EN_MASK 0x8000 172 #define SSC_CNTL_OVRD_VAL_MASK 0x4000 173 #define SSC_STATUS_OFFSET 0x1 174 #define SSC_STATUS_SSC_MASK 0x400 175 #define SSC_STATUS_PLL_LOCK_MASK 0x800 176 #define PCIE_BRCM_MAX_MEMC 3 177 178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) 179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) 180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) 181 182 /* Rescal registers */ 183 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 184 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3 185 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4 186 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2 187 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2 188 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1 189 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1 190 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0 191 192 /* Forward declarations */ 193 struct brcm_pcie; 194 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val); 195 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val); 196 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val); 197 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val); 198 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val); 199 static int brcm_pcie_linkup(struct brcm_pcie *pcie); 200 static int brcm_pcie_add_bus(struct pci_bus *bus); 201 202 enum { 203 RGR1_SW_INIT_1, 204 EXT_CFG_INDEX, 205 EXT_CFG_DATA, 206 }; 207 208 enum { 209 RGR1_SW_INIT_1_INIT_MASK, 210 RGR1_SW_INIT_1_INIT_SHIFT, 211 }; 212 213 enum pcie_type { 214 GENERIC, 215 BCM7425, 216 BCM7435, 217 BCM4908, 218 BCM7278, 219 BCM2711, 220 }; 221 222 struct pcie_cfg_data { 223 const int *offsets; 224 const enum pcie_type type; 225 void (*perst_set)(struct brcm_pcie *pcie, u32 val); 226 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 227 }; 228 229 static const int pcie_offsets[] = { 230 [RGR1_SW_INIT_1] = 0x9210, 231 [EXT_CFG_INDEX] = 0x9000, 232 [EXT_CFG_DATA] = 0x9004, 233 }; 234 235 static const int pcie_offsets_bmips_7425[] = { 236 [RGR1_SW_INIT_1] = 0x8010, 237 [EXT_CFG_INDEX] = 0x8300, 238 [EXT_CFG_DATA] = 0x8304, 239 }; 240 241 static const struct pcie_cfg_data generic_cfg = { 242 .offsets = pcie_offsets, 243 .type = GENERIC, 244 .perst_set = brcm_pcie_perst_set_generic, 245 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 246 }; 247 248 static const struct pcie_cfg_data bcm7425_cfg = { 249 .offsets = pcie_offsets_bmips_7425, 250 .type = BCM7425, 251 .perst_set = brcm_pcie_perst_set_generic, 252 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 253 }; 254 255 static const struct pcie_cfg_data bcm7435_cfg = { 256 .offsets = pcie_offsets, 257 .type = BCM7435, 258 .perst_set = brcm_pcie_perst_set_generic, 259 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 260 }; 261 262 static const struct pcie_cfg_data bcm4908_cfg = { 263 .offsets = pcie_offsets, 264 .type = BCM4908, 265 .perst_set = brcm_pcie_perst_set_4908, 266 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 267 }; 268 269 static const int pcie_offset_bcm7278[] = { 270 [RGR1_SW_INIT_1] = 0xc010, 271 [EXT_CFG_INDEX] = 0x9000, 272 [EXT_CFG_DATA] = 0x9004, 273 }; 274 275 static const struct pcie_cfg_data bcm7278_cfg = { 276 .offsets = pcie_offset_bcm7278, 277 .type = BCM7278, 278 .perst_set = brcm_pcie_perst_set_7278, 279 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, 280 }; 281 282 static const struct pcie_cfg_data bcm2711_cfg = { 283 .offsets = pcie_offsets, 284 .type = BCM2711, 285 .perst_set = brcm_pcie_perst_set_generic, 286 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 287 }; 288 289 struct subdev_regulators { 290 unsigned int num_supplies; 291 struct regulator_bulk_data supplies[]; 292 }; 293 294 static int pci_subdev_regulators_add_bus(struct pci_bus *bus); 295 static void pci_subdev_regulators_remove_bus(struct pci_bus *bus); 296 297 struct brcm_msi { 298 struct device *dev; 299 void __iomem *base; 300 struct device_node *np; 301 struct irq_domain *msi_domain; 302 struct irq_domain *inner_domain; 303 struct mutex lock; /* guards the alloc/free operations */ 304 u64 target_addr; 305 int irq; 306 DECLARE_BITMAP(used, BRCM_INT_PCI_MSI_NR); 307 bool legacy; 308 /* Some chips have MSIs in bits [31..24] of a shared register. */ 309 int legacy_shift; 310 int nr; /* No. of MSI available, depends on chip */ 311 /* This is the base pointer for interrupt status/set/clr regs */ 312 void __iomem *intr_base; 313 }; 314 315 /* Internal PCIe Host Controller Information.*/ 316 struct brcm_pcie { 317 struct device *dev; 318 void __iomem *base; 319 struct clk *clk; 320 struct device_node *np; 321 bool ssc; 322 int gen; 323 u64 msi_target_addr; 324 struct brcm_msi *msi; 325 const int *reg_offsets; 326 enum pcie_type type; 327 struct reset_control *rescal; 328 struct reset_control *perst_reset; 329 int num_memc; 330 u64 memc_size[PCIE_BRCM_MAX_MEMC]; 331 u32 hw_rev; 332 void (*perst_set)(struct brcm_pcie *pcie, u32 val); 333 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 334 bool refusal_mode; 335 struct subdev_regulators *sr; 336 bool ep_wakeup_capable; 337 }; 338 339 static inline bool is_bmips(const struct brcm_pcie *pcie) 340 { 341 return pcie->type == BCM7435 || pcie->type == BCM7425; 342 } 343 344 /* 345 * This is to convert the size of the inbound "BAR" region to the 346 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE 347 */ 348 static int brcm_pcie_encode_ibar_size(u64 size) 349 { 350 int log2_in = ilog2(size); 351 352 if (log2_in >= 12 && log2_in <= 15) 353 /* Covers 4KB to 32KB (inclusive) */ 354 return (log2_in - 12) + 0x1c; 355 else if (log2_in >= 16 && log2_in <= 35) 356 /* Covers 64KB to 32GB, (inclusive) */ 357 return log2_in - 15; 358 /* Something is awry so disable */ 359 return 0; 360 } 361 362 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) 363 { 364 u32 pkt = 0; 365 366 pkt |= FIELD_PREP(MDIO_PORT_MASK, port); 367 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); 368 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); 369 370 return pkt; 371 } 372 373 /* negative return value indicates error */ 374 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) 375 { 376 int tries; 377 u32 data; 378 379 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), 380 base + PCIE_RC_DL_MDIO_ADDR); 381 readl(base + PCIE_RC_DL_MDIO_ADDR); 382 383 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 384 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { 385 udelay(10); 386 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 387 } 388 389 *val = FIELD_GET(MDIO_DATA_MASK, data); 390 return MDIO_RD_DONE(data) ? 0 : -EIO; 391 } 392 393 /* negative return value indicates error */ 394 static int brcm_pcie_mdio_write(void __iomem *base, u8 port, 395 u8 regad, u16 wrdata) 396 { 397 int tries; 398 u32 data; 399 400 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), 401 base + PCIE_RC_DL_MDIO_ADDR); 402 readl(base + PCIE_RC_DL_MDIO_ADDR); 403 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); 404 405 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 406 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { 407 udelay(10); 408 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 409 } 410 411 return MDIO_WT_DONE(data) ? 0 : -EIO; 412 } 413 414 /* 415 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative 416 * return value indicates error. 417 */ 418 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) 419 { 420 int pll, ssc; 421 int ret; 422 u32 tmp; 423 424 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 425 SSC_REGS_ADDR); 426 if (ret < 0) 427 return ret; 428 429 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 430 SSC_CNTL_OFFSET, &tmp); 431 if (ret < 0) 432 return ret; 433 434 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); 435 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); 436 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, 437 SSC_CNTL_OFFSET, tmp); 438 if (ret < 0) 439 return ret; 440 441 usleep_range(1000, 2000); 442 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 443 SSC_STATUS_OFFSET, &tmp); 444 if (ret < 0) 445 return ret; 446 447 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); 448 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); 449 450 return ssc && pll ? 0 : -EIO; 451 } 452 453 static void *alloc_subdev_regulators(struct device *dev) 454 { 455 static const char * const supplies[] = { 456 "vpcie3v3", 457 "vpcie3v3aux", 458 "vpcie12v", 459 }; 460 const size_t size = sizeof(struct subdev_regulators) 461 + sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies); 462 struct subdev_regulators *sr; 463 int i; 464 465 sr = devm_kzalloc(dev, size, GFP_KERNEL); 466 if (sr) { 467 sr->num_supplies = ARRAY_SIZE(supplies); 468 for (i = 0; i < ARRAY_SIZE(supplies); i++) 469 sr->supplies[i].supply = supplies[i]; 470 } 471 472 return sr; 473 } 474 475 static int pci_subdev_regulators_add_bus(struct pci_bus *bus) 476 { 477 struct device *dev = &bus->dev; 478 struct subdev_regulators *sr; 479 int ret; 480 481 if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent)) 482 return 0; 483 484 if (dev->driver_data) 485 dev_err(dev, "dev.driver_data unexpectedly non-NULL\n"); 486 487 sr = alloc_subdev_regulators(dev); 488 if (!sr) 489 return -ENOMEM; 490 491 dev->driver_data = sr; 492 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); 493 if (ret) 494 return ret; 495 496 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); 497 if (ret) { 498 dev_err(dev, "failed to enable regulators for downstream device\n"); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 static int brcm_pcie_add_bus(struct pci_bus *bus) 506 { 507 struct device *dev = &bus->dev; 508 struct brcm_pcie *pcie = (struct brcm_pcie *) bus->sysdata; 509 int ret; 510 511 if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent)) 512 return 0; 513 514 ret = pci_subdev_regulators_add_bus(bus); 515 if (ret) 516 return ret; 517 518 /* Grab the regulators for suspend/resume */ 519 pcie->sr = bus->dev.driver_data; 520 521 /* 522 * If we have failed linkup there is no point to return an error as 523 * currently it will cause a WARNING() from pci_alloc_child_bus(). 524 * We return 0 and turn on the "refusal_mode" so that any further 525 * accesses to the pci_dev just get 0xffffffff 526 */ 527 if (brcm_pcie_linkup(pcie) != 0) 528 pcie->refusal_mode = true; 529 530 return 0; 531 } 532 533 static void pci_subdev_regulators_remove_bus(struct pci_bus *bus) 534 { 535 struct device *dev = &bus->dev; 536 struct subdev_regulators *sr = dev->driver_data; 537 538 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) 539 return; 540 541 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) 542 dev_err(dev, "failed to disable regulators for downstream device\n"); 543 dev->driver_data = NULL; 544 } 545 546 /* Limits operation to a specific generation (1, 2, or 3) */ 547 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) 548 { 549 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 550 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 551 552 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; 553 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 554 555 lnkctl2 = (lnkctl2 & ~0xf) | gen; 556 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 557 } 558 559 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, 560 unsigned int win, u64 cpu_addr, 561 u64 pcie_addr, u64 size) 562 { 563 u32 cpu_addr_mb_high, limit_addr_mb_high; 564 phys_addr_t cpu_addr_mb, limit_addr_mb; 565 int high_addr_shift; 566 u32 tmp; 567 568 /* Set the base of the pcie_addr window */ 569 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); 570 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); 571 572 /* Write the addr base & limit lower bits (in MBs) */ 573 cpu_addr_mb = cpu_addr / SZ_1M; 574 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; 575 576 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 577 u32p_replace_bits(&tmp, cpu_addr_mb, 578 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 579 u32p_replace_bits(&tmp, limit_addr_mb, 580 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); 581 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 582 583 if (is_bmips(pcie)) 584 return; 585 586 /* Write the cpu & limit addr upper bits */ 587 high_addr_shift = 588 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 589 590 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift; 591 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 592 u32p_replace_bits(&tmp, cpu_addr_mb_high, 593 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); 594 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 595 596 limit_addr_mb_high = limit_addr_mb >> high_addr_shift; 597 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 598 u32p_replace_bits(&tmp, limit_addr_mb_high, 599 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); 600 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 601 } 602 603 static struct irq_chip brcm_msi_irq_chip = { 604 .name = "BRCM STB PCIe MSI", 605 .irq_ack = irq_chip_ack_parent, 606 .irq_mask = pci_msi_mask_irq, 607 .irq_unmask = pci_msi_unmask_irq, 608 }; 609 610 static struct msi_domain_info brcm_msi_domain_info = { 611 /* Multi MSI is supported by the controller, but not by this driver */ 612 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 613 .chip = &brcm_msi_irq_chip, 614 }; 615 616 static void brcm_pcie_msi_isr(struct irq_desc *desc) 617 { 618 struct irq_chip *chip = irq_desc_get_chip(desc); 619 unsigned long status; 620 struct brcm_msi *msi; 621 struct device *dev; 622 u32 bit; 623 624 chained_irq_enter(chip, desc); 625 msi = irq_desc_get_handler_data(desc); 626 dev = msi->dev; 627 628 status = readl(msi->intr_base + MSI_INT_STATUS); 629 status >>= msi->legacy_shift; 630 631 for_each_set_bit(bit, &status, msi->nr) { 632 int ret; 633 ret = generic_handle_domain_irq(msi->inner_domain, bit); 634 if (ret) 635 dev_dbg(dev, "unexpected MSI\n"); 636 } 637 638 chained_irq_exit(chip, desc); 639 } 640 641 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 642 { 643 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 644 645 msg->address_lo = lower_32_bits(msi->target_addr); 646 msg->address_hi = upper_32_bits(msi->target_addr); 647 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; 648 } 649 650 static int brcm_msi_set_affinity(struct irq_data *irq_data, 651 const struct cpumask *mask, bool force) 652 { 653 return -EINVAL; 654 } 655 656 static void brcm_msi_ack_irq(struct irq_data *data) 657 { 658 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 659 const int shift_amt = data->hwirq + msi->legacy_shift; 660 661 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); 662 } 663 664 665 static struct irq_chip brcm_msi_bottom_irq_chip = { 666 .name = "BRCM STB MSI", 667 .irq_compose_msi_msg = brcm_msi_compose_msi_msg, 668 .irq_set_affinity = brcm_msi_set_affinity, 669 .irq_ack = brcm_msi_ack_irq, 670 }; 671 672 static int brcm_msi_alloc(struct brcm_msi *msi) 673 { 674 int hwirq; 675 676 mutex_lock(&msi->lock); 677 hwirq = bitmap_find_free_region(msi->used, msi->nr, 0); 678 mutex_unlock(&msi->lock); 679 680 return hwirq; 681 } 682 683 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) 684 { 685 mutex_lock(&msi->lock); 686 bitmap_release_region(msi->used, hwirq, 0); 687 mutex_unlock(&msi->lock); 688 } 689 690 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 691 unsigned int nr_irqs, void *args) 692 { 693 struct brcm_msi *msi = domain->host_data; 694 int hwirq; 695 696 hwirq = brcm_msi_alloc(msi); 697 698 if (hwirq < 0) 699 return hwirq; 700 701 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, 702 &brcm_msi_bottom_irq_chip, domain->host_data, 703 handle_edge_irq, NULL, NULL); 704 return 0; 705 } 706 707 static void brcm_irq_domain_free(struct irq_domain *domain, 708 unsigned int virq, unsigned int nr_irqs) 709 { 710 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 711 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); 712 713 brcm_msi_free(msi, d->hwirq); 714 } 715 716 static const struct irq_domain_ops msi_domain_ops = { 717 .alloc = brcm_irq_domain_alloc, 718 .free = brcm_irq_domain_free, 719 }; 720 721 static int brcm_allocate_domains(struct brcm_msi *msi) 722 { 723 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); 724 struct device *dev = msi->dev; 725 726 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); 727 if (!msi->inner_domain) { 728 dev_err(dev, "failed to create IRQ domain\n"); 729 return -ENOMEM; 730 } 731 732 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 733 &brcm_msi_domain_info, 734 msi->inner_domain); 735 if (!msi->msi_domain) { 736 dev_err(dev, "failed to create MSI domain\n"); 737 irq_domain_remove(msi->inner_domain); 738 return -ENOMEM; 739 } 740 741 return 0; 742 } 743 744 static void brcm_free_domains(struct brcm_msi *msi) 745 { 746 irq_domain_remove(msi->msi_domain); 747 irq_domain_remove(msi->inner_domain); 748 } 749 750 static void brcm_msi_remove(struct brcm_pcie *pcie) 751 { 752 struct brcm_msi *msi = pcie->msi; 753 754 if (!msi) 755 return; 756 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); 757 brcm_free_domains(msi); 758 } 759 760 static void brcm_msi_set_regs(struct brcm_msi *msi) 761 { 762 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : 763 BRCM_INT_PCI_MSI_MASK; 764 765 writel(val, msi->intr_base + MSI_INT_MASK_CLR); 766 writel(val, msi->intr_base + MSI_INT_CLR); 767 768 /* 769 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI 770 * enable, which we set to 1. 771 */ 772 writel(lower_32_bits(msi->target_addr) | 0x1, 773 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); 774 writel(upper_32_bits(msi->target_addr), 775 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); 776 777 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; 778 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); 779 } 780 781 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) 782 { 783 struct brcm_msi *msi; 784 int irq, ret; 785 struct device *dev = pcie->dev; 786 787 irq = irq_of_parse_and_map(dev->of_node, 1); 788 if (irq <= 0) { 789 dev_err(dev, "cannot map MSI interrupt\n"); 790 return -ENODEV; 791 } 792 793 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); 794 if (!msi) 795 return -ENOMEM; 796 797 mutex_init(&msi->lock); 798 msi->dev = dev; 799 msi->base = pcie->base; 800 msi->np = pcie->np; 801 msi->target_addr = pcie->msi_target_addr; 802 msi->irq = irq; 803 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; 804 805 /* 806 * Sanity check to make sure that the 'used' bitmap in struct brcm_msi 807 * is large enough. 808 */ 809 BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR); 810 811 if (msi->legacy) { 812 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; 813 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; 814 msi->legacy_shift = 24; 815 } else { 816 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; 817 msi->nr = BRCM_INT_PCI_MSI_NR; 818 msi->legacy_shift = 0; 819 } 820 821 ret = brcm_allocate_domains(msi); 822 if (ret) 823 return ret; 824 825 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); 826 827 brcm_msi_set_regs(msi); 828 pcie->msi = msi; 829 830 return 0; 831 } 832 833 /* The controller is capable of serving in both RC and EP roles */ 834 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) 835 { 836 void __iomem *base = pcie->base; 837 u32 val = readl(base + PCIE_MISC_PCIE_STATUS); 838 839 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); 840 } 841 842 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) 843 { 844 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); 845 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); 846 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); 847 848 return dla && plu; 849 } 850 851 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, 852 int where) 853 { 854 struct brcm_pcie *pcie = bus->sysdata; 855 void __iomem *base = pcie->base; 856 int idx; 857 858 /* Accesses to the RC go right to the RC registers if slot==0 */ 859 if (pci_is_root_bus(bus)) 860 return PCI_SLOT(devfn) ? NULL : base + where; 861 if (pcie->refusal_mode) { 862 /* 863 * At this point we do not have link. There will be a CPU 864 * abort -- a quirk with this controller --if Linux tries 865 * to read any config-space registers besides those 866 * targeting the host bridge. To prevent this we hijack 867 * the address to point to a safe access that will return 868 * 0xffffffff. 869 */ 870 writel(0xffffffff, base + PCIE_MISC_RC_BAR2_CONFIG_HI); 871 return base + PCIE_MISC_RC_BAR2_CONFIG_HI + (where & 0x3); 872 } 873 874 /* For devices, write to the config space index register */ 875 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); 876 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); 877 return base + PCIE_EXT_CFG_DATA + where; 878 } 879 880 static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devfn, 881 int where) 882 { 883 struct brcm_pcie *pcie = bus->sysdata; 884 void __iomem *base = pcie->base; 885 int idx; 886 887 /* Accesses to the RC go right to the RC registers if slot==0 */ 888 if (pci_is_root_bus(bus)) 889 return PCI_SLOT(devfn) ? NULL : base + (where & ~0x3); 890 891 /* For devices, write to the config space index register */ 892 idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & ~3)); 893 writel(idx, base + IDX_ADDR(pcie)); 894 return base + DATA_ADDR(pcie); 895 } 896 897 static struct pci_ops brcm_pcie_ops = { 898 .map_bus = brcm_pcie_map_conf, 899 .read = pci_generic_config_read, 900 .write = pci_generic_config_write, 901 .add_bus = brcm_pcie_add_bus, 902 .remove_bus = pci_subdev_regulators_remove_bus, 903 }; 904 905 static struct pci_ops brcm_pcie_ops32 = { 906 .map_bus = brcm_pcie_map_conf32, 907 .read = pci_generic_config_read32, 908 .write = pci_generic_config_write32, 909 }; 910 911 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) 912 { 913 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; 914 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; 915 916 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 917 tmp = (tmp & ~mask) | ((val << shift) & mask); 918 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 919 } 920 921 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) 922 { 923 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK; 924 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT; 925 926 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 927 tmp = (tmp & ~mask) | ((val << shift) & mask); 928 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 929 } 930 931 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) 932 { 933 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) 934 return; 935 936 if (val) 937 reset_control_assert(pcie->perst_reset); 938 else 939 reset_control_deassert(pcie->perst_reset); 940 } 941 942 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) 943 { 944 u32 tmp; 945 946 /* Perst bit has moved and assert value is 0 */ 947 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); 948 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); 949 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); 950 } 951 952 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) 953 { 954 u32 tmp; 955 956 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 957 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); 958 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 959 } 960 961 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, 962 u64 *rc_bar2_size, 963 u64 *rc_bar2_offset) 964 { 965 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 966 struct resource_entry *entry; 967 struct device *dev = pcie->dev; 968 u64 lowest_pcie_addr = ~(u64)0; 969 int ret, i = 0; 970 u64 size = 0; 971 972 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 973 u64 pcie_beg = entry->res->start - entry->offset; 974 975 size += entry->res->end - entry->res->start + 1; 976 if (pcie_beg < lowest_pcie_addr) 977 lowest_pcie_addr = pcie_beg; 978 } 979 980 if (lowest_pcie_addr == ~(u64)0) { 981 dev_err(dev, "DT node has no dma-ranges\n"); 982 return -EINVAL; 983 } 984 985 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, 986 PCIE_BRCM_MAX_MEMC); 987 988 if (ret <= 0) { 989 /* Make an educated guess */ 990 pcie->num_memc = 1; 991 pcie->memc_size[0] = 1ULL << fls64(size - 1); 992 } else { 993 pcie->num_memc = ret; 994 } 995 996 /* Each memc is viewed through a "port" that is a power of 2 */ 997 for (i = 0, size = 0; i < pcie->num_memc; i++) 998 size += pcie->memc_size[i]; 999 1000 /* System memory starts at this address in PCIe-space */ 1001 *rc_bar2_offset = lowest_pcie_addr; 1002 /* The sum of all memc views must also be a power of 2 */ 1003 *rc_bar2_size = 1ULL << fls64(size - 1); 1004 1005 /* 1006 * We validate the inbound memory view even though we should trust 1007 * whatever the device-tree provides. This is because of an HW issue on 1008 * early Raspberry Pi 4's revisions (bcm2711). It turns out its 1009 * firmware has to dynamically edit dma-ranges due to a bug on the 1010 * PCIe controller integration, which prohibits any access above the 1011 * lower 3GB of memory. Given this, we decided to keep the dma-ranges 1012 * in check, avoiding hard to debug device-tree related issues in the 1013 * future: 1014 * 1015 * The PCIe host controller by design must set the inbound viewport to 1016 * be a contiguous arrangement of all of the system's memory. In 1017 * addition, its size mut be a power of two. To further complicate 1018 * matters, the viewport must start on a pcie-address that is aligned 1019 * on a multiple of its size. If a portion of the viewport does not 1020 * represent system memory -- e.g. 3GB of memory requires a 4GB 1021 * viewport -- we can map the outbound memory in or after 3GB and even 1022 * though the viewport will overlap the outbound memory the controller 1023 * will know to send outbound memory downstream and everything else 1024 * upstream. 1025 * 1026 * For example: 1027 * 1028 * - The best-case scenario, memory up to 3GB, is to place the inbound 1029 * region in the first 4GB of pcie-space, as some legacy devices can 1030 * only address 32bits. We would also like to put the MSI under 4GB 1031 * as well, since some devices require a 32bit MSI target address. 1032 * 1033 * - If the system memory is 4GB or larger we cannot start the inbound 1034 * region at location 0 (since we have to allow some space for 1035 * outbound memory @ 3GB). So instead it will start at the 1x 1036 * multiple of its size 1037 */ 1038 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || 1039 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { 1040 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", 1041 *rc_bar2_size, *rc_bar2_offset); 1042 return -EINVAL; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static int brcm_pcie_setup(struct brcm_pcie *pcie) 1049 { 1050 u64 rc_bar2_offset, rc_bar2_size; 1051 void __iomem *base = pcie->base; 1052 int ret, memc; 1053 u32 tmp, burst, aspm_support; 1054 1055 /* Reset the bridge */ 1056 pcie->bridge_sw_init_set(pcie, 1); 1057 usleep_range(100, 200); 1058 1059 /* Take the bridge out of reset */ 1060 pcie->bridge_sw_init_set(pcie, 0); 1061 1062 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1063 if (is_bmips(pcie)) 1064 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 1065 else 1066 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 1067 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1068 /* Wait for SerDes to be stable */ 1069 usleep_range(100, 200); 1070 1071 /* 1072 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it 1073 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it 1074 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. 1075 */ 1076 if (is_bmips(pcie)) 1077 burst = 0x1; /* 256 bytes */ 1078 else if (pcie->type == BCM2711) 1079 burst = 0x0; /* 128 bytes */ 1080 else if (pcie->type == BCM7278) 1081 burst = 0x3; /* 512 bytes */ 1082 else 1083 burst = 0x2; /* 512 bytes */ 1084 1085 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ 1086 tmp = readl(base + PCIE_MISC_MISC_CTRL); 1087 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); 1088 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); 1089 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); 1090 writel(tmp, base + PCIE_MISC_MISC_CTRL); 1091 1092 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, 1093 &rc_bar2_offset); 1094 if (ret) 1095 return ret; 1096 1097 tmp = lower_32_bits(rc_bar2_offset); 1098 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), 1099 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); 1100 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); 1101 writel(upper_32_bits(rc_bar2_offset), 1102 base + PCIE_MISC_RC_BAR2_CONFIG_HI); 1103 1104 tmp = readl(base + PCIE_MISC_MISC_CTRL); 1105 for (memc = 0; memc < pcie->num_memc; memc++) { 1106 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; 1107 1108 if (memc == 0) 1109 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); 1110 else if (memc == 1) 1111 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); 1112 else if (memc == 2) 1113 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2)); 1114 } 1115 writel(tmp, base + PCIE_MISC_MISC_CTRL); 1116 1117 /* 1118 * We ideally want the MSI target address to be located in the 32bit 1119 * addressable memory area. Some devices might depend on it. This is 1120 * possible either when the inbound window is located above the lower 1121 * 4GB or when the inbound area is smaller than 4GB (taking into 1122 * account the rounding-up we're forced to perform). 1123 */ 1124 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) 1125 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; 1126 else 1127 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; 1128 1129 /* disable the PCIe->GISB memory window (RC_BAR1) */ 1130 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); 1131 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; 1132 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); 1133 1134 /* disable the PCIe->SCB memory window (RC_BAR3) */ 1135 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); 1136 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; 1137 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); 1138 1139 if (pcie->gen) 1140 brcm_pcie_set_gen(pcie, pcie->gen); 1141 1142 /* Don't advertise L0s capability if 'aspm-no-l0s' */ 1143 aspm_support = PCIE_LINK_STATE_L1; 1144 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) 1145 aspm_support |= PCIE_LINK_STATE_L0S; 1146 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 1147 u32p_replace_bits(&tmp, aspm_support, 1148 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); 1149 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 1150 1151 /* 1152 * For config space accesses on the RC, show the right class for 1153 * a PCIe-PCIe bridge (the default setting is to be EP mode). 1154 */ 1155 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); 1156 u32p_replace_bits(&tmp, 0x060400, 1157 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); 1158 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); 1159 1160 return 0; 1161 } 1162 1163 static int brcm_pcie_linkup(struct brcm_pcie *pcie) 1164 { 1165 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1166 struct device *dev = pcie->dev; 1167 void __iomem *base = pcie->base; 1168 struct resource_entry *entry; 1169 struct resource *res; 1170 int num_out_wins = 0; 1171 u16 nlw, cls, lnksta; 1172 bool ssc_good = false; 1173 u32 tmp; 1174 int ret, i; 1175 1176 /* Unassert the fundamental reset */ 1177 pcie->perst_set(pcie, 0); 1178 1179 /* 1180 * Give the RC/EP time to wake up, before trying to configure RC. 1181 * Intermittently check status for link-up, up to a total of 100ms. 1182 */ 1183 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) 1184 msleep(5); 1185 1186 if (!brcm_pcie_link_up(pcie)) { 1187 dev_err(dev, "link down\n"); 1188 return -ENODEV; 1189 } 1190 1191 if (!brcm_pcie_rc_mode(pcie)) { 1192 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); 1193 return -EINVAL; 1194 } 1195 1196 resource_list_for_each_entry(entry, &bridge->windows) { 1197 res = entry->res; 1198 1199 if (resource_type(res) != IORESOURCE_MEM) 1200 continue; 1201 1202 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) { 1203 dev_err(pcie->dev, "too many outbound wins\n"); 1204 return -EINVAL; 1205 } 1206 1207 if (is_bmips(pcie)) { 1208 u64 start = res->start; 1209 unsigned int j, nwins = resource_size(res) / SZ_128M; 1210 1211 /* bmips PCIe outbound windows have a 128MB max size */ 1212 if (nwins > BRCM_NUM_PCIE_OUT_WINS) 1213 nwins = BRCM_NUM_PCIE_OUT_WINS; 1214 for (j = 0; j < nwins; j++, start += SZ_128M) 1215 brcm_pcie_set_outbound_win(pcie, j, start, 1216 start - entry->offset, 1217 SZ_128M); 1218 break; 1219 } 1220 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, 1221 res->start - entry->offset, 1222 resource_size(res)); 1223 num_out_wins++; 1224 } 1225 1226 if (pcie->ssc) { 1227 ret = brcm_pcie_set_ssc(pcie); 1228 if (ret == 0) 1229 ssc_good = true; 1230 else 1231 dev_err(dev, "failed attempt to enter ssc mode\n"); 1232 } 1233 1234 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); 1235 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); 1236 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); 1237 dev_info(dev, "link up, %s x%u %s\n", 1238 pci_speed_string(pcie_link_speed[cls]), nlw, 1239 ssc_good ? "(SSC)" : "(!SSC)"); 1240 1241 /* PCIe->SCB endian mode for BAR */ 1242 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 1243 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, 1244 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); 1245 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 1246 1247 /* 1248 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 1249 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. 1250 */ 1251 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1252 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; 1253 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1254 1255 return 0; 1256 } 1257 1258 /* L23 is a low-power PCIe link state */ 1259 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) 1260 { 1261 void __iomem *base = pcie->base; 1262 int l23, i; 1263 u32 tmp; 1264 1265 /* Assert request for L23 */ 1266 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 1267 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 1268 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 1269 1270 /* Wait up to 36 msec for L23 */ 1271 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 1272 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp); 1273 for (i = 0; i < 15 && !l23; i++) { 1274 usleep_range(2000, 2400); 1275 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 1276 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, 1277 tmp); 1278 } 1279 1280 if (!l23) 1281 dev_err(pcie->dev, "failed to enter low-power link state\n"); 1282 } 1283 1284 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) 1285 { 1286 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { 1287 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT, 1288 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT, 1289 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,}; 1290 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { 1291 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK, 1292 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK, 1293 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,}; 1294 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; 1295 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; 1296 u32 tmp, combined_mask = 0; 1297 u32 val; 1298 void __iomem *base = pcie->base; 1299 int i, ret; 1300 1301 for (i = beg; i != end; start ? i++ : i--) { 1302 val = start ? BIT_MASK(shifts[i]) : 0; 1303 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); 1304 tmp = (tmp & ~masks[i]) | (val & masks[i]); 1305 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL); 1306 usleep_range(50, 200); 1307 combined_mask |= masks[i]; 1308 } 1309 1310 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); 1311 val = start ? combined_mask : 0; 1312 1313 ret = (tmp & combined_mask) == val ? 0 : -EIO; 1314 if (ret) 1315 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); 1316 1317 return ret; 1318 } 1319 1320 static inline int brcm_phy_start(struct brcm_pcie *pcie) 1321 { 1322 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; 1323 } 1324 1325 static inline int brcm_phy_stop(struct brcm_pcie *pcie) 1326 { 1327 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; 1328 } 1329 1330 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) 1331 { 1332 void __iomem *base = pcie->base; 1333 int tmp; 1334 1335 if (brcm_pcie_link_up(pcie)) 1336 brcm_pcie_enter_l23(pcie); 1337 /* Assert fundamental reset */ 1338 pcie->perst_set(pcie, 1); 1339 1340 /* Deassert request for L23 in case it was asserted */ 1341 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 1342 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 1343 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 1344 1345 /* Turn off SerDes */ 1346 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1347 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 1348 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1349 1350 /* Shutdown PCIe bridge */ 1351 pcie->bridge_sw_init_set(pcie, 1); 1352 } 1353 1354 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) 1355 { 1356 bool *ret = data; 1357 1358 if (device_may_wakeup(&dev->dev)) { 1359 *ret = true; 1360 dev_info(&dev->dev, "disable cancelled for wake-up device\n"); 1361 } 1362 return (int) *ret; 1363 } 1364 1365 static int brcm_pcie_suspend(struct device *dev) 1366 { 1367 struct brcm_pcie *pcie = dev_get_drvdata(dev); 1368 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1369 int ret; 1370 1371 brcm_pcie_turn_off(pcie); 1372 /* 1373 * If brcm_phy_stop() returns an error, just dev_err(). If we 1374 * return the error it will cause the suspend to fail and this is a 1375 * forgivable offense that will probably be erased on resume. 1376 */ 1377 if (brcm_phy_stop(pcie)) 1378 dev_err(dev, "Could not stop phy for suspend\n"); 1379 1380 ret = reset_control_rearm(pcie->rescal); 1381 if (ret) { 1382 dev_err(dev, "Could not rearm rescal reset\n"); 1383 return ret; 1384 } 1385 1386 if (pcie->sr) { 1387 /* 1388 * Now turn off the regulators, but if at least one 1389 * downstream device is enabled as a wake-up source, do not 1390 * turn off regulators. 1391 */ 1392 pcie->ep_wakeup_capable = false; 1393 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, 1394 &pcie->ep_wakeup_capable); 1395 if (!pcie->ep_wakeup_capable) { 1396 ret = regulator_bulk_disable(pcie->sr->num_supplies, 1397 pcie->sr->supplies); 1398 if (ret) { 1399 dev_err(dev, "Could not turn off regulators\n"); 1400 reset_control_reset(pcie->rescal); 1401 return ret; 1402 } 1403 } 1404 } 1405 clk_disable_unprepare(pcie->clk); 1406 1407 return 0; 1408 } 1409 1410 static int brcm_pcie_resume(struct device *dev) 1411 { 1412 struct brcm_pcie *pcie = dev_get_drvdata(dev); 1413 void __iomem *base; 1414 u32 tmp; 1415 int ret; 1416 1417 base = pcie->base; 1418 ret = clk_prepare_enable(pcie->clk); 1419 if (ret) 1420 return ret; 1421 1422 if (pcie->sr) { 1423 if (pcie->ep_wakeup_capable) { 1424 /* 1425 * We are resuming from a suspend. In the suspend we 1426 * did not disable the power supplies, so there is 1427 * no need to enable them (and falsely increase their 1428 * usage count). 1429 */ 1430 pcie->ep_wakeup_capable = false; 1431 } else { 1432 ret = regulator_bulk_enable(pcie->sr->num_supplies, 1433 pcie->sr->supplies); 1434 if (ret) { 1435 dev_err(dev, "Could not turn on regulators\n"); 1436 goto err_disable_clk; 1437 } 1438 } 1439 } 1440 1441 ret = reset_control_reset(pcie->rescal); 1442 if (ret) 1443 goto err_regulator; 1444 1445 ret = brcm_phy_start(pcie); 1446 if (ret) 1447 goto err_reset; 1448 1449 /* Take bridge out of reset so we can access the SERDES reg */ 1450 pcie->bridge_sw_init_set(pcie, 0); 1451 1452 /* SERDES_IDDQ = 0 */ 1453 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1454 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 1455 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1456 1457 /* wait for serdes to be stable */ 1458 udelay(100); 1459 1460 ret = brcm_pcie_setup(pcie); 1461 if (ret) 1462 goto err_reset; 1463 1464 ret = brcm_pcie_linkup(pcie); 1465 if (ret) 1466 goto err_reset; 1467 1468 if (pcie->msi) 1469 brcm_msi_set_regs(pcie->msi); 1470 1471 return 0; 1472 1473 err_reset: 1474 reset_control_rearm(pcie->rescal); 1475 err_regulator: 1476 if (pcie->sr) 1477 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); 1478 err_disable_clk: 1479 clk_disable_unprepare(pcie->clk); 1480 return ret; 1481 } 1482 1483 static void __brcm_pcie_remove(struct brcm_pcie *pcie) 1484 { 1485 brcm_msi_remove(pcie); 1486 brcm_pcie_turn_off(pcie); 1487 if (brcm_phy_stop(pcie)) 1488 dev_err(pcie->dev, "Could not stop phy\n"); 1489 if (reset_control_rearm(pcie->rescal)) 1490 dev_err(pcie->dev, "Could not rearm rescal reset\n"); 1491 clk_disable_unprepare(pcie->clk); 1492 } 1493 1494 static int brcm_pcie_remove(struct platform_device *pdev) 1495 { 1496 struct brcm_pcie *pcie = platform_get_drvdata(pdev); 1497 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1498 1499 pci_stop_root_bus(bridge->bus); 1500 pci_remove_root_bus(bridge->bus); 1501 __brcm_pcie_remove(pcie); 1502 1503 return 0; 1504 } 1505 1506 static const struct of_device_id brcm_pcie_match[] = { 1507 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, 1508 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, 1509 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, 1510 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, 1511 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, 1512 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, 1513 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, 1514 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, 1515 {}, 1516 }; 1517 1518 static int brcm_pcie_probe(struct platform_device *pdev) 1519 { 1520 struct device_node *np = pdev->dev.of_node, *msi_np; 1521 struct pci_host_bridge *bridge; 1522 const struct pcie_cfg_data *data; 1523 struct brcm_pcie *pcie; 1524 int ret; 1525 1526 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); 1527 if (!bridge) 1528 return -ENOMEM; 1529 1530 data = of_device_get_match_data(&pdev->dev); 1531 if (!data) { 1532 pr_err("failed to look up compatible string\n"); 1533 return -EINVAL; 1534 } 1535 1536 pcie = pci_host_bridge_priv(bridge); 1537 pcie->dev = &pdev->dev; 1538 pcie->np = np; 1539 pcie->reg_offsets = data->offsets; 1540 pcie->type = data->type; 1541 pcie->perst_set = data->perst_set; 1542 pcie->bridge_sw_init_set = data->bridge_sw_init_set; 1543 1544 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1545 if (IS_ERR(pcie->base)) 1546 return PTR_ERR(pcie->base); 1547 1548 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); 1549 if (IS_ERR(pcie->clk)) 1550 return PTR_ERR(pcie->clk); 1551 1552 ret = of_pci_get_max_link_speed(np); 1553 pcie->gen = (ret < 0) ? 0 : ret; 1554 1555 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); 1556 1557 ret = clk_prepare_enable(pcie->clk); 1558 if (ret) { 1559 dev_err(&pdev->dev, "could not enable clock\n"); 1560 return ret; 1561 } 1562 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); 1563 if (IS_ERR(pcie->rescal)) { 1564 clk_disable_unprepare(pcie->clk); 1565 return PTR_ERR(pcie->rescal); 1566 } 1567 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); 1568 if (IS_ERR(pcie->perst_reset)) { 1569 clk_disable_unprepare(pcie->clk); 1570 return PTR_ERR(pcie->perst_reset); 1571 } 1572 1573 ret = reset_control_reset(pcie->rescal); 1574 if (ret) 1575 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); 1576 1577 ret = brcm_phy_start(pcie); 1578 if (ret) { 1579 reset_control_rearm(pcie->rescal); 1580 clk_disable_unprepare(pcie->clk); 1581 return ret; 1582 } 1583 1584 ret = brcm_pcie_setup(pcie); 1585 if (ret) 1586 goto fail; 1587 1588 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); 1589 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { 1590 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); 1591 ret = -ENODEV; 1592 goto fail; 1593 } 1594 1595 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); 1596 if (pci_msi_enabled() && msi_np == pcie->np) { 1597 ret = brcm_pcie_enable_msi(pcie); 1598 if (ret) { 1599 dev_err(pcie->dev, "probe of internal MSI failed"); 1600 goto fail; 1601 } 1602 } 1603 1604 bridge->ops = pcie->type == BCM7425 ? &brcm_pcie_ops32 : &brcm_pcie_ops; 1605 bridge->sysdata = pcie; 1606 1607 platform_set_drvdata(pdev, pcie); 1608 1609 ret = pci_host_probe(bridge); 1610 if (!ret && !brcm_pcie_link_up(pcie)) 1611 ret = -ENODEV; 1612 1613 if (ret) { 1614 brcm_pcie_remove(pdev); 1615 return ret; 1616 } 1617 1618 return 0; 1619 1620 fail: 1621 __brcm_pcie_remove(pcie); 1622 return ret; 1623 } 1624 1625 MODULE_DEVICE_TABLE(of, brcm_pcie_match); 1626 1627 static const struct dev_pm_ops brcm_pcie_pm_ops = { 1628 .suspend_noirq = brcm_pcie_suspend, 1629 .resume_noirq = brcm_pcie_resume, 1630 }; 1631 1632 static struct platform_driver brcm_pcie_driver = { 1633 .probe = brcm_pcie_probe, 1634 .remove = brcm_pcie_remove, 1635 .driver = { 1636 .name = "brcm-pcie", 1637 .of_match_table = brcm_pcie_match, 1638 .pm = &brcm_pcie_pm_ops, 1639 }, 1640 }; 1641 module_platform_driver(brcm_pcie_driver); 1642 1643 MODULE_LICENSE("GPL"); 1644 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver"); 1645 MODULE_AUTHOR("Broadcom"); 1646