1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2009 - 2019 Broadcom */ 3 4 #include <linux/bitfield.h> 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/compiler.h> 8 #include <linux/delay.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/log2.h> 18 #include <linux/module.h> 19 #include <linux/msi.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_pci.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/printk.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/string.h> 29 #include <linux/types.h> 30 31 #include <soc/bcm2835/raspberrypi-firmware.h> 32 33 #include "../pci.h" 34 35 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ 36 #define BRCM_PCIE_CAP_REGS 0x00ac 37 38 /* Broadcom STB PCIe Register Offsets */ 39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc 41 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 42 43 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c 44 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff 45 46 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc 47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 48 49 #define PCIE_RC_DL_MDIO_ADDR 0x1100 50 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 51 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 52 53 #define PCIE_MISC_MISC_CTRL 0x4008 54 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 55 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 56 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 57 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 58 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 59 60 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c 61 #define PCIE_MEM_WIN0_LO(win) \ 62 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8) 63 64 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 65 #define PCIE_MEM_WIN0_HI(win) \ 66 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) 67 68 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c 69 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f 70 71 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 72 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f 73 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 74 75 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c 76 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f 77 78 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 79 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 80 81 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c 82 #define PCIE_MISC_MSI_DATA_CONFIG_VAL 0xffe06540 83 84 #define PCIE_MISC_PCIE_CTRL 0x4064 85 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 86 87 #define PCIE_MISC_PCIE_STATUS 0x4068 88 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 89 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 90 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 91 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 92 93 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 94 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 95 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 96 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \ 97 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) 98 99 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 100 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff 101 #define PCIE_MEM_WIN0_BASE_HI(win) \ 102 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) 103 104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 105 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff 106 #define PCIE_MEM_WIN0_LIMIT_HI(win) \ 107 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) 108 109 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 110 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 111 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 112 113 #define PCIE_MSI_INTR2_STATUS 0x4500 114 #define PCIE_MSI_INTR2_CLR 0x4508 115 #define PCIE_MSI_INTR2_MASK_SET 0x4510 116 #define PCIE_MSI_INTR2_MASK_CLR 0x4514 117 118 #define PCIE_EXT_CFG_DATA 0x8000 119 120 #define PCIE_EXT_CFG_INDEX 0x9000 121 #define PCIE_EXT_BUSNUM_SHIFT 20 122 #define PCIE_EXT_SLOT_SHIFT 15 123 #define PCIE_EXT_FUNC_SHIFT 12 124 125 #define PCIE_RGR1_SW_INIT_1 0x9210 126 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 127 #define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 128 129 /* PCIe parameters */ 130 #define BRCM_NUM_PCIE_OUT_WINS 0x4 131 #define BRCM_INT_PCI_MSI_NR 32 132 133 /* MSI target adresses */ 134 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL 135 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL 136 137 /* MDIO registers */ 138 #define MDIO_PORT0 0x0 139 #define MDIO_DATA_MASK 0x7fffffff 140 #define MDIO_PORT_MASK 0xf0000 141 #define MDIO_REGAD_MASK 0xffff 142 #define MDIO_CMD_MASK 0xfff00000 143 #define MDIO_CMD_READ 0x1 144 #define MDIO_CMD_WRITE 0x0 145 #define MDIO_DATA_DONE_MASK 0x80000000 146 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) 147 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) 148 #define SSC_REGS_ADDR 0x1100 149 #define SET_ADDR_OFFSET 0x1f 150 #define SSC_CNTL_OFFSET 0x2 151 #define SSC_CNTL_OVRD_EN_MASK 0x8000 152 #define SSC_CNTL_OVRD_VAL_MASK 0x4000 153 #define SSC_STATUS_OFFSET 0x1 154 #define SSC_STATUS_SSC_MASK 0x400 155 #define SSC_STATUS_PLL_LOCK_MASK 0x800 156 157 struct brcm_msi { 158 struct device *dev; 159 void __iomem *base; 160 struct device_node *np; 161 struct irq_domain *msi_domain; 162 struct irq_domain *inner_domain; 163 struct mutex lock; /* guards the alloc/free operations */ 164 u64 target_addr; 165 int irq; 166 /* used indicates which MSI interrupts have been alloc'd */ 167 unsigned long used; 168 }; 169 170 /* Internal PCIe Host Controller Information.*/ 171 struct brcm_pcie { 172 struct device *dev; 173 void __iomem *base; 174 struct clk *clk; 175 struct pci_bus *root_bus; 176 struct device_node *np; 177 bool ssc; 178 int gen; 179 u64 msi_target_addr; 180 struct brcm_msi *msi; 181 }; 182 183 /* 184 * This is to convert the size of the inbound "BAR" region to the 185 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE 186 */ 187 static int brcm_pcie_encode_ibar_size(u64 size) 188 { 189 int log2_in = ilog2(size); 190 191 if (log2_in >= 12 && log2_in <= 15) 192 /* Covers 4KB to 32KB (inclusive) */ 193 return (log2_in - 12) + 0x1c; 194 else if (log2_in >= 16 && log2_in <= 35) 195 /* Covers 64KB to 32GB, (inclusive) */ 196 return log2_in - 15; 197 /* Something is awry so disable */ 198 return 0; 199 } 200 201 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) 202 { 203 u32 pkt = 0; 204 205 pkt |= FIELD_PREP(MDIO_PORT_MASK, port); 206 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); 207 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); 208 209 return pkt; 210 } 211 212 /* negative return value indicates error */ 213 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) 214 { 215 int tries; 216 u32 data; 217 218 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), 219 base + PCIE_RC_DL_MDIO_ADDR); 220 readl(base + PCIE_RC_DL_MDIO_ADDR); 221 222 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 223 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { 224 udelay(10); 225 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 226 } 227 228 *val = FIELD_GET(MDIO_DATA_MASK, data); 229 return MDIO_RD_DONE(data) ? 0 : -EIO; 230 } 231 232 /* negative return value indicates error */ 233 static int brcm_pcie_mdio_write(void __iomem *base, u8 port, 234 u8 regad, u16 wrdata) 235 { 236 int tries; 237 u32 data; 238 239 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), 240 base + PCIE_RC_DL_MDIO_ADDR); 241 readl(base + PCIE_RC_DL_MDIO_ADDR); 242 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); 243 244 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 245 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { 246 udelay(10); 247 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 248 } 249 250 return MDIO_WT_DONE(data) ? 0 : -EIO; 251 } 252 253 /* 254 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative 255 * return value indicates error. 256 */ 257 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) 258 { 259 int pll, ssc; 260 int ret; 261 u32 tmp; 262 263 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 264 SSC_REGS_ADDR); 265 if (ret < 0) 266 return ret; 267 268 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 269 SSC_CNTL_OFFSET, &tmp); 270 if (ret < 0) 271 return ret; 272 273 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); 274 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); 275 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, 276 SSC_CNTL_OFFSET, tmp); 277 if (ret < 0) 278 return ret; 279 280 usleep_range(1000, 2000); 281 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 282 SSC_STATUS_OFFSET, &tmp); 283 if (ret < 0) 284 return ret; 285 286 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); 287 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); 288 289 return ssc && pll ? 0 : -EIO; 290 } 291 292 /* Limits operation to a specific generation (1, 2, or 3) */ 293 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) 294 { 295 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 296 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 297 298 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; 299 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 300 301 lnkctl2 = (lnkctl2 & ~0xf) | gen; 302 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 303 } 304 305 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, 306 unsigned int win, u64 cpu_addr, 307 u64 pcie_addr, u64 size) 308 { 309 u32 cpu_addr_mb_high, limit_addr_mb_high; 310 phys_addr_t cpu_addr_mb, limit_addr_mb; 311 int high_addr_shift; 312 u32 tmp; 313 314 /* Set the base of the pcie_addr window */ 315 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); 316 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); 317 318 /* Write the addr base & limit lower bits (in MBs) */ 319 cpu_addr_mb = cpu_addr / SZ_1M; 320 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; 321 322 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 323 u32p_replace_bits(&tmp, cpu_addr_mb, 324 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 325 u32p_replace_bits(&tmp, limit_addr_mb, 326 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); 327 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 328 329 /* Write the cpu & limit addr upper bits */ 330 high_addr_shift = 331 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 332 333 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift; 334 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 335 u32p_replace_bits(&tmp, cpu_addr_mb_high, 336 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); 337 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 338 339 limit_addr_mb_high = limit_addr_mb >> high_addr_shift; 340 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 341 u32p_replace_bits(&tmp, limit_addr_mb_high, 342 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); 343 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 344 } 345 346 static struct irq_chip brcm_msi_irq_chip = { 347 .name = "BRCM STB PCIe MSI", 348 .irq_ack = irq_chip_ack_parent, 349 .irq_mask = pci_msi_mask_irq, 350 .irq_unmask = pci_msi_unmask_irq, 351 }; 352 353 static struct msi_domain_info brcm_msi_domain_info = { 354 /* Multi MSI is supported by the controller, but not by this driver */ 355 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 356 .chip = &brcm_msi_irq_chip, 357 }; 358 359 static void brcm_pcie_msi_isr(struct irq_desc *desc) 360 { 361 struct irq_chip *chip = irq_desc_get_chip(desc); 362 unsigned long status, virq; 363 struct brcm_msi *msi; 364 struct device *dev; 365 u32 bit; 366 367 chained_irq_enter(chip, desc); 368 msi = irq_desc_get_handler_data(desc); 369 dev = msi->dev; 370 371 status = readl(msi->base + PCIE_MSI_INTR2_STATUS); 372 for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) { 373 virq = irq_find_mapping(msi->inner_domain, bit); 374 if (virq) 375 generic_handle_irq(virq); 376 else 377 dev_dbg(dev, "unexpected MSI\n"); 378 } 379 380 chained_irq_exit(chip, desc); 381 } 382 383 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 384 { 385 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 386 387 msg->address_lo = lower_32_bits(msi->target_addr); 388 msg->address_hi = upper_32_bits(msi->target_addr); 389 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL) | data->hwirq; 390 } 391 392 static int brcm_msi_set_affinity(struct irq_data *irq_data, 393 const struct cpumask *mask, bool force) 394 { 395 return -EINVAL; 396 } 397 398 static void brcm_msi_ack_irq(struct irq_data *data) 399 { 400 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 401 402 writel(1 << data->hwirq, msi->base + PCIE_MSI_INTR2_CLR); 403 } 404 405 406 static struct irq_chip brcm_msi_bottom_irq_chip = { 407 .name = "BRCM STB MSI", 408 .irq_compose_msi_msg = brcm_msi_compose_msi_msg, 409 .irq_set_affinity = brcm_msi_set_affinity, 410 .irq_ack = brcm_msi_ack_irq, 411 }; 412 413 static int brcm_msi_alloc(struct brcm_msi *msi) 414 { 415 int hwirq; 416 417 mutex_lock(&msi->lock); 418 hwirq = bitmap_find_free_region(&msi->used, BRCM_INT_PCI_MSI_NR, 0); 419 mutex_unlock(&msi->lock); 420 421 return hwirq; 422 } 423 424 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) 425 { 426 mutex_lock(&msi->lock); 427 bitmap_release_region(&msi->used, hwirq, 0); 428 mutex_unlock(&msi->lock); 429 } 430 431 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 432 unsigned int nr_irqs, void *args) 433 { 434 struct brcm_msi *msi = domain->host_data; 435 int hwirq; 436 437 hwirq = brcm_msi_alloc(msi); 438 439 if (hwirq < 0) 440 return hwirq; 441 442 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, 443 &brcm_msi_bottom_irq_chip, domain->host_data, 444 handle_edge_irq, NULL, NULL); 445 return 0; 446 } 447 448 static void brcm_irq_domain_free(struct irq_domain *domain, 449 unsigned int virq, unsigned int nr_irqs) 450 { 451 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 452 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); 453 454 brcm_msi_free(msi, d->hwirq); 455 } 456 457 static const struct irq_domain_ops msi_domain_ops = { 458 .alloc = brcm_irq_domain_alloc, 459 .free = brcm_irq_domain_free, 460 }; 461 462 static int brcm_allocate_domains(struct brcm_msi *msi) 463 { 464 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); 465 struct device *dev = msi->dev; 466 467 msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR, 468 &msi_domain_ops, msi); 469 if (!msi->inner_domain) { 470 dev_err(dev, "failed to create IRQ domain\n"); 471 return -ENOMEM; 472 } 473 474 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 475 &brcm_msi_domain_info, 476 msi->inner_domain); 477 if (!msi->msi_domain) { 478 dev_err(dev, "failed to create MSI domain\n"); 479 irq_domain_remove(msi->inner_domain); 480 return -ENOMEM; 481 } 482 483 return 0; 484 } 485 486 static void brcm_free_domains(struct brcm_msi *msi) 487 { 488 irq_domain_remove(msi->msi_domain); 489 irq_domain_remove(msi->inner_domain); 490 } 491 492 static void brcm_msi_remove(struct brcm_pcie *pcie) 493 { 494 struct brcm_msi *msi = pcie->msi; 495 496 if (!msi) 497 return; 498 irq_set_chained_handler(msi->irq, NULL); 499 irq_set_handler_data(msi->irq, NULL); 500 brcm_free_domains(msi); 501 } 502 503 static void brcm_msi_set_regs(struct brcm_msi *msi) 504 { 505 writel(0xffffffff, msi->base + PCIE_MSI_INTR2_MASK_CLR); 506 507 /* 508 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI 509 * enable, which we set to 1. 510 */ 511 writel(lower_32_bits(msi->target_addr) | 0x1, 512 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); 513 writel(upper_32_bits(msi->target_addr), 514 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); 515 516 writel(PCIE_MISC_MSI_DATA_CONFIG_VAL, 517 msi->base + PCIE_MISC_MSI_DATA_CONFIG); 518 } 519 520 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) 521 { 522 struct brcm_msi *msi; 523 int irq, ret; 524 struct device *dev = pcie->dev; 525 526 irq = irq_of_parse_and_map(dev->of_node, 1); 527 if (irq <= 0) { 528 dev_err(dev, "cannot map MSI interrupt\n"); 529 return -ENODEV; 530 } 531 532 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); 533 if (!msi) 534 return -ENOMEM; 535 536 mutex_init(&msi->lock); 537 msi->dev = dev; 538 msi->base = pcie->base; 539 msi->np = pcie->np; 540 msi->target_addr = pcie->msi_target_addr; 541 msi->irq = irq; 542 543 ret = brcm_allocate_domains(msi); 544 if (ret) 545 return ret; 546 547 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); 548 549 brcm_msi_set_regs(msi); 550 pcie->msi = msi; 551 552 return 0; 553 } 554 555 /* The controller is capable of serving in both RC and EP roles */ 556 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) 557 { 558 void __iomem *base = pcie->base; 559 u32 val = readl(base + PCIE_MISC_PCIE_STATUS); 560 561 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); 562 } 563 564 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) 565 { 566 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); 567 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); 568 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); 569 570 return dla && plu; 571 } 572 573 /* Configuration space read/write support */ 574 static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) 575 { 576 return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) 577 | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) 578 | (busnr << PCIE_EXT_BUSNUM_SHIFT) 579 | (reg & ~3); 580 } 581 582 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, 583 int where) 584 { 585 struct brcm_pcie *pcie = bus->sysdata; 586 void __iomem *base = pcie->base; 587 int idx; 588 589 /* Accesses to the RC go right to the RC registers if slot==0 */ 590 if (pci_is_root_bus(bus)) 591 return PCI_SLOT(devfn) ? NULL : base + where; 592 593 /* For devices, write to the config space index register */ 594 idx = brcm_pcie_cfg_index(bus->number, devfn, 0); 595 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); 596 return base + PCIE_EXT_CFG_DATA + where; 597 } 598 599 static struct pci_ops brcm_pcie_ops = { 600 .map_bus = brcm_pcie_map_conf, 601 .read = pci_generic_config_read, 602 .write = pci_generic_config_write, 603 }; 604 605 static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) 606 { 607 u32 tmp; 608 609 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); 610 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); 611 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); 612 } 613 614 static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) 615 { 616 u32 tmp; 617 618 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); 619 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); 620 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); 621 } 622 623 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, 624 u64 *rc_bar2_size, 625 u64 *rc_bar2_offset) 626 { 627 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 628 struct device *dev = pcie->dev; 629 struct resource_entry *entry; 630 631 entry = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); 632 if (!entry) 633 return -ENODEV; 634 635 636 /* 637 * The controller expects the inbound window offset to be calculated as 638 * the difference between PCIe's address space and CPU's. The offset 639 * provided by the firmware is calculated the opposite way, so we 640 * negate it. 641 */ 642 *rc_bar2_offset = -entry->offset; 643 *rc_bar2_size = 1ULL << fls64(entry->res->end - entry->res->start); 644 645 /* 646 * We validate the inbound memory view even though we should trust 647 * whatever the device-tree provides. This is because of an HW issue on 648 * early Raspberry Pi 4's revisions (bcm2711). It turns out its 649 * firmware has to dynamically edit dma-ranges due to a bug on the 650 * PCIe controller integration, which prohibits any access above the 651 * lower 3GB of memory. Given this, we decided to keep the dma-ranges 652 * in check, avoiding hard to debug device-tree related issues in the 653 * future: 654 * 655 * The PCIe host controller by design must set the inbound viewport to 656 * be a contiguous arrangement of all of the system's memory. In 657 * addition, its size mut be a power of two. To further complicate 658 * matters, the viewport must start on a pcie-address that is aligned 659 * on a multiple of its size. If a portion of the viewport does not 660 * represent system memory -- e.g. 3GB of memory requires a 4GB 661 * viewport -- we can map the outbound memory in or after 3GB and even 662 * though the viewport will overlap the outbound memory the controller 663 * will know to send outbound memory downstream and everything else 664 * upstream. 665 * 666 * For example: 667 * 668 * - The best-case scenario, memory up to 3GB, is to place the inbound 669 * region in the first 4GB of pcie-space, as some legacy devices can 670 * only address 32bits. We would also like to put the MSI under 4GB 671 * as well, since some devices require a 32bit MSI target address. 672 * 673 * - If the system memory is 4GB or larger we cannot start the inbound 674 * region at location 0 (since we have to allow some space for 675 * outbound memory @ 3GB). So instead it will start at the 1x 676 * multiple of its size 677 */ 678 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || 679 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { 680 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", 681 *rc_bar2_size, *rc_bar2_offset); 682 return -EINVAL; 683 } 684 685 return 0; 686 } 687 688 static int brcm_pcie_setup(struct brcm_pcie *pcie) 689 { 690 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 691 u64 rc_bar2_offset, rc_bar2_size; 692 void __iomem *base = pcie->base; 693 struct device *dev = pcie->dev; 694 struct resource_entry *entry; 695 unsigned int scb_size_val; 696 bool ssc_good = false; 697 struct resource *res; 698 int num_out_wins = 0; 699 u16 nlw, cls, lnksta; 700 int i, ret; 701 u32 tmp, aspm_support; 702 703 /* Reset the bridge */ 704 brcm_pcie_bridge_sw_init_set(pcie, 1); 705 brcm_pcie_perst_set(pcie, 1); 706 707 usleep_range(100, 200); 708 709 /* Take the bridge out of reset */ 710 brcm_pcie_bridge_sw_init_set(pcie, 0); 711 712 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 713 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 714 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 715 /* Wait for SerDes to be stable */ 716 usleep_range(100, 200); 717 718 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ 719 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); 720 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); 721 u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, 722 PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); 723 writel(tmp, base + PCIE_MISC_MISC_CTRL); 724 725 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, 726 &rc_bar2_offset); 727 if (ret) 728 return ret; 729 730 tmp = lower_32_bits(rc_bar2_offset); 731 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), 732 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); 733 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); 734 writel(upper_32_bits(rc_bar2_offset), 735 base + PCIE_MISC_RC_BAR2_CONFIG_HI); 736 737 scb_size_val = rc_bar2_size ? 738 ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ 739 tmp = readl(base + PCIE_MISC_MISC_CTRL); 740 u32p_replace_bits(&tmp, scb_size_val, 741 PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); 742 writel(tmp, base + PCIE_MISC_MISC_CTRL); 743 744 /* 745 * We ideally want the MSI target address to be located in the 32bit 746 * addressable memory area. Some devices might depend on it. This is 747 * possible either when the inbound window is located above the lower 748 * 4GB or when the inbound area is smaller than 4GB (taking into 749 * account the rounding-up we're forced to perform). 750 */ 751 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) 752 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; 753 else 754 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; 755 756 /* disable the PCIe->GISB memory window (RC_BAR1) */ 757 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); 758 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; 759 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); 760 761 /* disable the PCIe->SCB memory window (RC_BAR3) */ 762 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); 763 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; 764 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); 765 766 /* Mask all interrupts since we are not handling any yet */ 767 writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_MASK_SET); 768 769 /* clear any interrupts we find on boot */ 770 writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_CLR); 771 772 if (pcie->gen) 773 brcm_pcie_set_gen(pcie, pcie->gen); 774 775 /* Unassert the fundamental reset */ 776 brcm_pcie_perst_set(pcie, 0); 777 778 /* 779 * Give the RC/EP time to wake up, before trying to configure RC. 780 * Intermittently check status for link-up, up to a total of 100ms. 781 */ 782 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) 783 msleep(5); 784 785 if (!brcm_pcie_link_up(pcie)) { 786 dev_err(dev, "link down\n"); 787 return -ENODEV; 788 } 789 790 if (!brcm_pcie_rc_mode(pcie)) { 791 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); 792 return -EINVAL; 793 } 794 795 resource_list_for_each_entry(entry, &bridge->windows) { 796 res = entry->res; 797 798 if (resource_type(res) != IORESOURCE_MEM) 799 continue; 800 801 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) { 802 dev_err(pcie->dev, "too many outbound wins\n"); 803 return -EINVAL; 804 } 805 806 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, 807 res->start - entry->offset, 808 resource_size(res)); 809 num_out_wins++; 810 } 811 812 /* Don't advertise L0s capability if 'aspm-no-l0s' */ 813 aspm_support = PCIE_LINK_STATE_L1; 814 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) 815 aspm_support |= PCIE_LINK_STATE_L0S; 816 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 817 u32p_replace_bits(&tmp, aspm_support, 818 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); 819 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 820 821 /* 822 * For config space accesses on the RC, show the right class for 823 * a PCIe-PCIe bridge (the default setting is to be EP mode). 824 */ 825 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); 826 u32p_replace_bits(&tmp, 0x060400, 827 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); 828 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); 829 830 if (pcie->ssc) { 831 ret = brcm_pcie_set_ssc(pcie); 832 if (ret == 0) 833 ssc_good = true; 834 else 835 dev_err(dev, "failed attempt to enter ssc mode\n"); 836 } 837 838 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); 839 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); 840 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); 841 dev_info(dev, "link up, %s x%u %s\n", 842 pci_speed_string(pcie_link_speed[cls]), nlw, 843 ssc_good ? "(SSC)" : "(!SSC)"); 844 845 /* PCIe->SCB endian mode for BAR */ 846 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 847 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, 848 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); 849 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 850 851 /* 852 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 853 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. 854 */ 855 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 856 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; 857 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 858 859 return 0; 860 } 861 862 /* L23 is a low-power PCIe link state */ 863 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) 864 { 865 void __iomem *base = pcie->base; 866 int l23, i; 867 u32 tmp; 868 869 /* Assert request for L23 */ 870 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 871 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 872 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 873 874 /* Wait up to 36 msec for L23 */ 875 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 876 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp); 877 for (i = 0; i < 15 && !l23; i++) { 878 usleep_range(2000, 2400); 879 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 880 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, 881 tmp); 882 } 883 884 if (!l23) 885 dev_err(pcie->dev, "failed to enter low-power link state\n"); 886 } 887 888 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) 889 { 890 void __iomem *base = pcie->base; 891 int tmp; 892 893 if (brcm_pcie_link_up(pcie)) 894 brcm_pcie_enter_l23(pcie); 895 /* Assert fundamental reset */ 896 brcm_pcie_perst_set(pcie, 1); 897 898 /* Deassert request for L23 in case it was asserted */ 899 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 900 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 901 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 902 903 /* Turn off SerDes */ 904 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 905 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 906 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 907 908 /* Shutdown PCIe bridge */ 909 brcm_pcie_bridge_sw_init_set(pcie, 1); 910 } 911 912 static void __brcm_pcie_remove(struct brcm_pcie *pcie) 913 { 914 brcm_msi_remove(pcie); 915 brcm_pcie_turn_off(pcie); 916 clk_disable_unprepare(pcie->clk); 917 } 918 919 static int brcm_pcie_remove(struct platform_device *pdev) 920 { 921 struct brcm_pcie *pcie = platform_get_drvdata(pdev); 922 923 pci_stop_root_bus(pcie->root_bus); 924 pci_remove_root_bus(pcie->root_bus); 925 __brcm_pcie_remove(pcie); 926 927 return 0; 928 } 929 930 static int brcm_pcie_probe(struct platform_device *pdev) 931 { 932 struct device_node *np = pdev->dev.of_node, *msi_np; 933 struct pci_host_bridge *bridge; 934 struct device_node *fw_np; 935 struct brcm_pcie *pcie; 936 struct pci_bus *child; 937 struct resource *res; 938 int ret; 939 940 /* 941 * We have to wait for Raspberry Pi's firmware interface to be up as a 942 * PCI fixup, rpi_firmware_init_vl805(), depends on it. This driver's 943 * probe can race with the firmware interface's (see 944 * drivers/firmware/raspberrypi.c) and potentially break the PCI fixup. 945 */ 946 fw_np = of_find_compatible_node(NULL, NULL, 947 "raspberrypi,bcm2835-firmware"); 948 if (fw_np && !rpi_firmware_get(fw_np)) { 949 of_node_put(fw_np); 950 return -EPROBE_DEFER; 951 } 952 of_node_put(fw_np); 953 954 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); 955 if (!bridge) 956 return -ENOMEM; 957 958 pcie = pci_host_bridge_priv(bridge); 959 pcie->dev = &pdev->dev; 960 pcie->np = np; 961 962 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 963 pcie->base = devm_ioremap_resource(&pdev->dev, res); 964 if (IS_ERR(pcie->base)) 965 return PTR_ERR(pcie->base); 966 967 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); 968 if (IS_ERR(pcie->clk)) 969 return PTR_ERR(pcie->clk); 970 971 ret = of_pci_get_max_link_speed(np); 972 pcie->gen = (ret < 0) ? 0 : ret; 973 974 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); 975 976 ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows, 977 &bridge->dma_ranges, NULL); 978 if (ret) 979 return ret; 980 981 ret = clk_prepare_enable(pcie->clk); 982 if (ret) { 983 dev_err(&pdev->dev, "could not enable clock\n"); 984 return ret; 985 } 986 987 ret = brcm_pcie_setup(pcie); 988 if (ret) 989 goto fail; 990 991 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); 992 if (pci_msi_enabled() && msi_np == pcie->np) { 993 ret = brcm_pcie_enable_msi(pcie); 994 if (ret) { 995 dev_err(pcie->dev, "probe of internal MSI failed"); 996 goto fail; 997 } 998 } 999 1000 bridge->dev.parent = &pdev->dev; 1001 bridge->busnr = 0; 1002 bridge->ops = &brcm_pcie_ops; 1003 bridge->sysdata = pcie; 1004 bridge->map_irq = of_irq_parse_and_map_pci; 1005 bridge->swizzle_irq = pci_common_swizzle; 1006 1007 ret = pci_scan_root_bus_bridge(bridge); 1008 if (ret < 0) { 1009 dev_err(pcie->dev, "Scanning root bridge failed\n"); 1010 goto fail; 1011 } 1012 1013 pci_assign_unassigned_bus_resources(bridge->bus); 1014 list_for_each_entry(child, &bridge->bus->children, node) 1015 pcie_bus_configure_settings(child); 1016 pci_bus_add_devices(bridge->bus); 1017 platform_set_drvdata(pdev, pcie); 1018 pcie->root_bus = bridge->bus; 1019 1020 return 0; 1021 fail: 1022 __brcm_pcie_remove(pcie); 1023 return ret; 1024 } 1025 1026 static const struct of_device_id brcm_pcie_match[] = { 1027 { .compatible = "brcm,bcm2711-pcie" }, 1028 {}, 1029 }; 1030 MODULE_DEVICE_TABLE(of, brcm_pcie_match); 1031 1032 static struct platform_driver brcm_pcie_driver = { 1033 .probe = brcm_pcie_probe, 1034 .remove = brcm_pcie_remove, 1035 .driver = { 1036 .name = "brcm-pcie", 1037 .of_match_table = brcm_pcie_match, 1038 }, 1039 }; 1040 module_platform_driver(brcm_pcie_driver); 1041 1042 MODULE_LICENSE("GPL"); 1043 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver"); 1044 MODULE_AUTHOR("Broadcom"); 1045