1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * APM X-Gene PCIe Driver 4 * 5 * Copyright (c) 2014 Applied Micro Circuits Corporation. 6 * 7 * Author: Tanmay Inamdar <tinamdar@apm.com>. 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/memblock.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_pci.h> 19 #include <linux/pci.h> 20 #include <linux/pci-acpi.h> 21 #include <linux/pci-ecam.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 25 #include "../pci.h" 26 27 #define PCIECORE_CTLANDSTATUS 0x50 28 #define PIM1_1L 0x80 29 #define IBAR2 0x98 30 #define IR2MSK 0x9c 31 #define PIM2_1L 0xa0 32 #define IBAR3L 0xb4 33 #define IR3MSKL 0xbc 34 #define PIM3_1L 0xc4 35 #define OMR1BARL 0x100 36 #define OMR2BARL 0x118 37 #define OMR3BARL 0x130 38 #define CFGBARL 0x154 39 #define CFGBARH 0x158 40 #define CFGCTL 0x15c 41 #define RTDID 0x160 42 #define BRIDGE_CFG_0 0x2000 43 #define BRIDGE_CFG_4 0x2010 44 #define BRIDGE_STATUS_0 0x2600 45 46 #define LINK_UP_MASK 0x00000100 47 #define AXI_EP_CFG_ACCESS 0x10000 48 #define EN_COHERENCY 0xF0000000 49 #define EN_REG 0x00000001 50 #define OB_LO_IO 0x00000002 51 #define XGENE_PCIE_VENDORID 0x10E8 52 #define XGENE_PCIE_DEVICEID 0xE004 53 #define SZ_1T (SZ_1G*1024ULL) 54 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) 55 56 #define XGENE_V1_PCI_EXP_CAP 0x40 57 58 /* PCIe IP version */ 59 #define XGENE_PCIE_IP_VER_UNKN 0 60 #define XGENE_PCIE_IP_VER_1 1 61 #define XGENE_PCIE_IP_VER_2 2 62 63 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) 64 struct xgene_pcie_port { 65 struct device_node *node; 66 struct device *dev; 67 struct clk *clk; 68 void __iomem *csr_base; 69 void __iomem *cfg_base; 70 unsigned long cfg_addr; 71 bool link_up; 72 u32 version; 73 }; 74 75 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) 76 { 77 return readl(port->csr_base + reg); 78 } 79 80 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) 81 { 82 writel(val, port->csr_base + reg); 83 } 84 85 static inline u32 pcie_bar_low_val(u32 addr, u32 flags) 86 { 87 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; 88 } 89 90 static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus) 91 { 92 struct pci_config_window *cfg; 93 94 if (acpi_disabled) 95 return (struct xgene_pcie_port *)(bus->sysdata); 96 97 cfg = bus->sysdata; 98 return (struct xgene_pcie_port *)(cfg->priv); 99 } 100 101 /* 102 * When the address bit [17:16] is 2'b01, the Configuration access will be 103 * treated as Type 1 and it will be forwarded to external PCIe device. 104 */ 105 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) 106 { 107 struct xgene_pcie_port *port = pcie_bus_to_port(bus); 108 109 if (bus->number >= (bus->primary + 1)) 110 return port->cfg_base + AXI_EP_CFG_ACCESS; 111 112 return port->cfg_base; 113 } 114 115 /* 116 * For Configuration request, RTDID register is used as Bus Number, 117 * Device Number and Function number of the header fields. 118 */ 119 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) 120 { 121 struct xgene_pcie_port *port = pcie_bus_to_port(bus); 122 unsigned int b, d, f; 123 u32 rtdid_val = 0; 124 125 b = bus->number; 126 d = PCI_SLOT(devfn); 127 f = PCI_FUNC(devfn); 128 129 if (!pci_is_root_bus(bus)) 130 rtdid_val = (b << 8) | (d << 3) | f; 131 132 xgene_pcie_writel(port, RTDID, rtdid_val); 133 /* read the register back to ensure flush */ 134 xgene_pcie_readl(port, RTDID); 135 } 136 137 /* 138 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as 139 * the translation from PCI bus to native BUS. Entire DDR region 140 * is mapped into PCIe space using these registers, so it can be 141 * reached by DMA from EP devices. The BAR0/1 of bridge should be 142 * hidden during enumeration to avoid the sizing and resource allocation 143 * by PCIe core. 144 */ 145 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) 146 { 147 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || 148 (offset == PCI_BASE_ADDRESS_1))) 149 return true; 150 151 return false; 152 } 153 154 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 155 int offset) 156 { 157 if ((pci_is_root_bus(bus) && devfn != 0) || 158 xgene_pcie_hide_rc_bars(bus, offset)) 159 return NULL; 160 161 xgene_pcie_set_rtdid_reg(bus, devfn); 162 return xgene_pcie_get_cfg_base(bus) + offset; 163 } 164 165 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, 166 int where, int size, u32 *val) 167 { 168 struct xgene_pcie_port *port = pcie_bus_to_port(bus); 169 170 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != 171 PCIBIOS_SUCCESSFUL) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 174 /* 175 * The v1 controller has a bug in its Configuration Request 176 * Retry Status (CRS) logic: when CRS Software Visibility is 177 * enabled and we read the Vendor and Device ID of a non-existent 178 * device, the controller fabricates return data of 0xFFFF0001 179 * ("device exists but is not ready") instead of 0xFFFFFFFF 180 * ("device does not exist"). This causes the PCI core to retry 181 * the read until it times out. Avoid this by not claiming to 182 * support CRS SV. 183 */ 184 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && 185 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) 186 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); 187 188 if (size <= 2) 189 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 190 191 return PCIBIOS_SUCCESSFUL; 192 } 193 #endif 194 195 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) 196 static int xgene_get_csr_resource(struct acpi_device *adev, 197 struct resource *res) 198 { 199 struct device *dev = &adev->dev; 200 struct resource_entry *entry; 201 struct list_head list; 202 unsigned long flags; 203 int ret; 204 205 INIT_LIST_HEAD(&list); 206 flags = IORESOURCE_MEM; 207 ret = acpi_dev_get_resources(adev, &list, 208 acpi_dev_filter_resource_type_cb, 209 (void *) flags); 210 if (ret < 0) { 211 dev_err(dev, "failed to parse _CRS method, error code %d\n", 212 ret); 213 return ret; 214 } 215 216 if (ret == 0) { 217 dev_err(dev, "no IO and memory resources present in _CRS\n"); 218 return -EINVAL; 219 } 220 221 entry = list_first_entry(&list, struct resource_entry, node); 222 *res = *entry->res; 223 acpi_dev_free_resource_list(&list); 224 return 0; 225 } 226 227 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) 228 { 229 struct device *dev = cfg->parent; 230 struct acpi_device *adev = to_acpi_device(dev); 231 struct xgene_pcie_port *port; 232 struct resource csr; 233 int ret; 234 235 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 236 if (!port) 237 return -ENOMEM; 238 239 ret = xgene_get_csr_resource(adev, &csr); 240 if (ret) { 241 dev_err(dev, "can't get CSR resource\n"); 242 return ret; 243 } 244 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); 245 if (IS_ERR(port->csr_base)) 246 return PTR_ERR(port->csr_base); 247 248 port->cfg_base = cfg->win; 249 port->version = ipversion; 250 251 cfg->priv = port; 252 return 0; 253 } 254 255 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) 256 { 257 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); 258 } 259 260 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { 261 .init = xgene_v1_pcie_ecam_init, 262 .pci_ops = { 263 .map_bus = xgene_pcie_map_bus, 264 .read = xgene_pcie_config_read32, 265 .write = pci_generic_config_write, 266 } 267 }; 268 269 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) 270 { 271 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); 272 } 273 274 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { 275 .init = xgene_v2_pcie_ecam_init, 276 .pci_ops = { 277 .map_bus = xgene_pcie_map_bus, 278 .read = xgene_pcie_config_read32, 279 .write = pci_generic_config_write, 280 } 281 }; 282 #endif 283 284 #if defined(CONFIG_PCI_XGENE) 285 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, 286 u32 flags, u64 size) 287 { 288 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; 289 u32 val32 = 0; 290 u32 val; 291 292 val32 = xgene_pcie_readl(port, addr); 293 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); 294 xgene_pcie_writel(port, addr, val); 295 296 val32 = xgene_pcie_readl(port, addr + 0x04); 297 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); 298 xgene_pcie_writel(port, addr + 0x04, val); 299 300 val32 = xgene_pcie_readl(port, addr + 0x04); 301 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); 302 xgene_pcie_writel(port, addr + 0x04, val); 303 304 val32 = xgene_pcie_readl(port, addr + 0x08); 305 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); 306 xgene_pcie_writel(port, addr + 0x08, val); 307 308 return mask; 309 } 310 311 static void xgene_pcie_linkup(struct xgene_pcie_port *port, 312 u32 *lanes, u32 *speed) 313 { 314 u32 val32; 315 316 port->link_up = false; 317 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS); 318 if (val32 & LINK_UP_MASK) { 319 port->link_up = true; 320 *speed = PIPE_PHY_RATE_RD(val32); 321 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0); 322 *lanes = val32 >> 26; 323 } 324 } 325 326 static int xgene_pcie_init_port(struct xgene_pcie_port *port) 327 { 328 struct device *dev = port->dev; 329 int rc; 330 331 port->clk = clk_get(dev, NULL); 332 if (IS_ERR(port->clk)) { 333 dev_err(dev, "clock not available\n"); 334 return -ENODEV; 335 } 336 337 rc = clk_prepare_enable(port->clk); 338 if (rc) { 339 dev_err(dev, "clock enable failed\n"); 340 return rc; 341 } 342 343 return 0; 344 } 345 346 static int xgene_pcie_map_reg(struct xgene_pcie_port *port, 347 struct platform_device *pdev) 348 { 349 struct device *dev = port->dev; 350 struct resource *res; 351 352 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); 353 port->csr_base = devm_pci_remap_cfg_resource(dev, res); 354 if (IS_ERR(port->csr_base)) 355 return PTR_ERR(port->csr_base); 356 357 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 358 port->cfg_base = devm_ioremap_resource(dev, res); 359 if (IS_ERR(port->cfg_base)) 360 return PTR_ERR(port->cfg_base); 361 port->cfg_addr = res->start; 362 363 return 0; 364 } 365 366 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, 367 struct resource *res, u32 offset, 368 u64 cpu_addr, u64 pci_addr) 369 { 370 struct device *dev = port->dev; 371 resource_size_t size = resource_size(res); 372 u64 restype = resource_type(res); 373 u64 mask = 0; 374 u32 min_size; 375 u32 flag = EN_REG; 376 377 if (restype == IORESOURCE_MEM) { 378 min_size = SZ_128M; 379 } else { 380 min_size = 128; 381 flag |= OB_LO_IO; 382 } 383 384 if (size >= min_size) 385 mask = ~(size - 1) | flag; 386 else 387 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", 388 (u64)size, min_size); 389 390 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); 391 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); 392 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); 393 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); 394 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); 395 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); 396 } 397 398 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) 399 { 400 u64 addr = port->cfg_addr; 401 402 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); 403 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); 404 xgene_pcie_writel(port, CFGCTL, EN_REG); 405 } 406 407 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port) 408 { 409 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); 410 struct resource_entry *window; 411 struct device *dev = port->dev; 412 413 resource_list_for_each_entry(window, &bridge->windows) { 414 struct resource *res = window->res; 415 u64 restype = resource_type(res); 416 417 dev_dbg(dev, "%pR\n", res); 418 419 switch (restype) { 420 case IORESOURCE_IO: 421 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, 422 pci_pio_to_address(res->start), 423 res->start - window->offset); 424 break; 425 case IORESOURCE_MEM: 426 if (res->flags & IORESOURCE_PREFETCH) 427 xgene_pcie_setup_ob_reg(port, res, OMR2BARL, 428 res->start, 429 res->start - 430 window->offset); 431 else 432 xgene_pcie_setup_ob_reg(port, res, OMR1BARL, 433 res->start, 434 res->start - 435 window->offset); 436 break; 437 case IORESOURCE_BUS: 438 break; 439 default: 440 dev_err(dev, "invalid resource %pR\n", res); 441 return -EINVAL; 442 } 443 } 444 xgene_pcie_setup_cfg_reg(port); 445 return 0; 446 } 447 448 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg, 449 u64 pim, u64 size) 450 { 451 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); 452 xgene_pcie_writel(port, pim_reg + 0x04, 453 upper_32_bits(pim) | EN_COHERENCY); 454 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); 455 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); 456 } 457 458 /* 459 * X-Gene PCIe support maximum 3 inbound memory regions 460 * This function helps to select a region based on size of region 461 */ 462 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) 463 { 464 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { 465 *ib_reg_mask |= (1 << 1); 466 return 1; 467 } 468 469 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { 470 *ib_reg_mask |= (1 << 0); 471 return 0; 472 } 473 474 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { 475 *ib_reg_mask |= (1 << 2); 476 return 2; 477 } 478 479 return -EINVAL; 480 } 481 482 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, 483 struct resource_entry *entry, 484 u8 *ib_reg_mask) 485 { 486 void __iomem *cfg_base = port->cfg_base; 487 struct device *dev = port->dev; 488 void __iomem *bar_addr; 489 u32 pim_reg; 490 u64 cpu_addr = entry->res->start; 491 u64 pci_addr = cpu_addr - entry->offset; 492 u64 size = resource_size(entry->res); 493 u64 mask = ~(size - 1) | EN_REG; 494 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; 495 u32 bar_low; 496 int region; 497 498 region = xgene_pcie_select_ib_reg(ib_reg_mask, size); 499 if (region < 0) { 500 dev_warn(dev, "invalid pcie dma-range config\n"); 501 return; 502 } 503 504 if (entry->res->flags & IORESOURCE_PREFETCH) 505 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; 506 507 bar_low = pcie_bar_low_val((u32)cpu_addr, flags); 508 switch (region) { 509 case 0: 510 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); 511 bar_addr = cfg_base + PCI_BASE_ADDRESS_0; 512 writel(bar_low, bar_addr); 513 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); 514 pim_reg = PIM1_1L; 515 break; 516 case 1: 517 xgene_pcie_writel(port, IBAR2, bar_low); 518 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); 519 pim_reg = PIM2_1L; 520 break; 521 case 2: 522 xgene_pcie_writel(port, IBAR3L, bar_low); 523 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); 524 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); 525 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); 526 pim_reg = PIM3_1L; 527 break; 528 } 529 530 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); 531 } 532 533 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) 534 { 535 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); 536 struct resource_entry *entry; 537 u8 ib_reg_mask = 0; 538 539 resource_list_for_each_entry(entry, &bridge->dma_ranges) 540 xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask); 541 542 return 0; 543 } 544 545 /* clear BAR configuration which was done by firmware */ 546 static void xgene_pcie_clear_config(struct xgene_pcie_port *port) 547 { 548 int i; 549 550 for (i = PIM1_1L; i <= CFGCTL; i += 4) 551 xgene_pcie_writel(port, i, 0); 552 } 553 554 static int xgene_pcie_setup(struct xgene_pcie_port *port) 555 { 556 struct device *dev = port->dev; 557 u32 val, lanes = 0, speed = 0; 558 int ret; 559 560 xgene_pcie_clear_config(port); 561 562 /* setup the vendor and device IDs correctly */ 563 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; 564 xgene_pcie_writel(port, BRIDGE_CFG_0, val); 565 566 ret = xgene_pcie_map_ranges(port); 567 if (ret) 568 return ret; 569 570 ret = xgene_pcie_parse_map_dma_ranges(port); 571 if (ret) 572 return ret; 573 574 xgene_pcie_linkup(port, &lanes, &speed); 575 if (!port->link_up) 576 dev_info(dev, "(rc) link down\n"); 577 else 578 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); 579 return 0; 580 } 581 582 static struct pci_ops xgene_pcie_ops = { 583 .map_bus = xgene_pcie_map_bus, 584 .read = xgene_pcie_config_read32, 585 .write = pci_generic_config_write32, 586 }; 587 588 static int xgene_pcie_probe(struct platform_device *pdev) 589 { 590 struct device *dev = &pdev->dev; 591 struct device_node *dn = dev->of_node; 592 struct xgene_pcie_port *port; 593 struct pci_host_bridge *bridge; 594 int ret; 595 596 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); 597 if (!bridge) 598 return -ENOMEM; 599 600 port = pci_host_bridge_priv(bridge); 601 602 port->node = of_node_get(dn); 603 port->dev = dev; 604 605 port->version = XGENE_PCIE_IP_VER_UNKN; 606 if (of_device_is_compatible(port->node, "apm,xgene-pcie")) 607 port->version = XGENE_PCIE_IP_VER_1; 608 609 ret = xgene_pcie_map_reg(port, pdev); 610 if (ret) 611 return ret; 612 613 ret = xgene_pcie_init_port(port); 614 if (ret) 615 return ret; 616 617 ret = xgene_pcie_setup(port); 618 if (ret) 619 return ret; 620 621 bridge->sysdata = port; 622 bridge->ops = &xgene_pcie_ops; 623 624 return pci_host_probe(bridge); 625 } 626 627 static const struct of_device_id xgene_pcie_match_table[] = { 628 {.compatible = "apm,xgene-pcie",}, 629 {}, 630 }; 631 632 static struct platform_driver xgene_pcie_driver = { 633 .driver = { 634 .name = "xgene-pcie", 635 .of_match_table = of_match_ptr(xgene_pcie_match_table), 636 .suppress_bind_attrs = true, 637 }, 638 .probe = xgene_pcie_probe, 639 }; 640 builtin_platform_driver(xgene_pcie_driver); 641 #endif 642