16e0832faSShawn Lin // SPDX-License-Identifier: GPL-2.0+ 26e0832faSShawn Lin /* 36e0832faSShawn Lin * APM X-Gene MSI Driver 46e0832faSShawn Lin * 56e0832faSShawn Lin * Copyright (c) 2014, Applied Micro Circuits Corporation 66e0832faSShawn Lin * Author: Tanmay Inamdar <tinamdar@apm.com> 76e0832faSShawn Lin * Duc Dang <dhdang@apm.com> 86e0832faSShawn Lin */ 96e0832faSShawn Lin #include <linux/cpu.h> 106e0832faSShawn Lin #include <linux/interrupt.h> 11753596dcSBjorn Helgaas #include <linux/irqdomain.h> 126e0832faSShawn Lin #include <linux/module.h> 136e0832faSShawn Lin #include <linux/msi.h> 146e0832faSShawn Lin #include <linux/irqchip/chained_irq.h> 156e0832faSShawn Lin #include <linux/pci.h> 166e0832faSShawn Lin #include <linux/platform_device.h> 176e0832faSShawn Lin #include <linux/of_pci.h> 186e0832faSShawn Lin 196e0832faSShawn Lin #define MSI_IR0 0x000000 206e0832faSShawn Lin #define MSI_INT0 0x800000 216e0832faSShawn Lin #define IDX_PER_GROUP 8 226e0832faSShawn Lin #define IRQS_PER_IDX 16 236e0832faSShawn Lin #define NR_HW_IRQS 16 246e0832faSShawn Lin #define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) 256e0832faSShawn Lin 266e0832faSShawn Lin struct xgene_msi_group { 276e0832faSShawn Lin struct xgene_msi *msi; 286e0832faSShawn Lin int gic_irq; 296e0832faSShawn Lin u32 msi_grp; 306e0832faSShawn Lin }; 316e0832faSShawn Lin 326e0832faSShawn Lin struct xgene_msi { 336e0832faSShawn Lin struct device_node *node; 346e0832faSShawn Lin struct irq_domain *inner_domain; 356e0832faSShawn Lin struct irq_domain *msi_domain; 366e0832faSShawn Lin u64 msi_addr; 376e0832faSShawn Lin void __iomem *msi_regs; 386e0832faSShawn Lin unsigned long *bitmap; 396e0832faSShawn Lin struct mutex bitmap_lock; 406e0832faSShawn Lin struct xgene_msi_group *msi_groups; 416e0832faSShawn Lin int num_cpus; 426e0832faSShawn Lin }; 436e0832faSShawn Lin 446e0832faSShawn Lin /* Global data */ 456e0832faSShawn Lin static struct xgene_msi xgene_msi_ctrl; 466e0832faSShawn Lin 476e0832faSShawn Lin static struct irq_chip xgene_msi_top_irq_chip = { 486e0832faSShawn Lin .name = "X-Gene1 MSI", 496e0832faSShawn Lin .irq_enable = pci_msi_unmask_irq, 506e0832faSShawn Lin .irq_disable = pci_msi_mask_irq, 516e0832faSShawn Lin .irq_mask = pci_msi_mask_irq, 526e0832faSShawn Lin .irq_unmask = pci_msi_unmask_irq, 536e0832faSShawn Lin }; 546e0832faSShawn Lin 556e0832faSShawn Lin static struct msi_domain_info xgene_msi_domain_info = { 566e0832faSShawn Lin .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 576e0832faSShawn Lin MSI_FLAG_PCI_MSIX), 586e0832faSShawn Lin .chip = &xgene_msi_top_irq_chip, 596e0832faSShawn Lin }; 606e0832faSShawn Lin 616e0832faSShawn Lin /* 626e0832faSShawn Lin * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where 636e0832faSShawn Lin * n is group number (0..F), x is index of registers in each group (0..7) 646e0832faSShawn Lin * The register layout is as follows: 656e0832faSShawn Lin * MSI0IR0 base_addr 666e0832faSShawn Lin * MSI0IR1 base_addr + 0x10000 676e0832faSShawn Lin * ... ... 686e0832faSShawn Lin * MSI0IR6 base_addr + 0x60000 696e0832faSShawn Lin * MSI0IR7 base_addr + 0x70000 706e0832faSShawn Lin * MSI1IR0 base_addr + 0x80000 716e0832faSShawn Lin * MSI1IR1 base_addr + 0x90000 726e0832faSShawn Lin * ... ... 736e0832faSShawn Lin * MSI1IR7 base_addr + 0xF0000 746e0832faSShawn Lin * MSI2IR0 base_addr + 0x100000 756e0832faSShawn Lin * ... ... 766e0832faSShawn Lin * MSIFIR0 base_addr + 0x780000 776e0832faSShawn Lin * MSIFIR1 base_addr + 0x790000 786e0832faSShawn Lin * ... ... 796e0832faSShawn Lin * MSIFIR7 base_addr + 0x7F0000 806e0832faSShawn Lin * MSIINT0 base_addr + 0x800000 816e0832faSShawn Lin * MSIINT1 base_addr + 0x810000 826e0832faSShawn Lin * ... ... 836e0832faSShawn Lin * MSIINTF base_addr + 0x8F0000 846e0832faSShawn Lin * 856e0832faSShawn Lin * Each index register supports 16 MSI vectors (0..15) to generate interrupt. 866e0832faSShawn Lin * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination 876e0832faSShawn Lin * registers. 886e0832faSShawn Lin * 896e0832faSShawn Lin * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate 906e0832faSShawn Lin * the MSI pending status caused by 1 of its 8 index registers. 916e0832faSShawn Lin */ 926e0832faSShawn Lin 936e0832faSShawn Lin /* MSInIRx read helper */ 946e0832faSShawn Lin static u32 xgene_msi_ir_read(struct xgene_msi *msi, 956e0832faSShawn Lin u32 msi_grp, u32 msir_idx) 966e0832faSShawn Lin { 976e0832faSShawn Lin return readl_relaxed(msi->msi_regs + MSI_IR0 + 986e0832faSShawn Lin (msi_grp << 19) + (msir_idx << 16)); 996e0832faSShawn Lin } 1006e0832faSShawn Lin 1016e0832faSShawn Lin /* MSIINTn read helper */ 1026e0832faSShawn Lin static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) 1036e0832faSShawn Lin { 1046e0832faSShawn Lin return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16)); 1056e0832faSShawn Lin } 1066e0832faSShawn Lin 1076e0832faSShawn Lin /* 1086e0832faSShawn Lin * With 2048 MSI vectors supported, the MSI message can be constructed using 1096e0832faSShawn Lin * following scheme: 1106e0832faSShawn Lin * - Divide into 8 256-vector groups 1116e0832faSShawn Lin * Group 0: 0-255 1126e0832faSShawn Lin * Group 1: 256-511 1136e0832faSShawn Lin * Group 2: 512-767 1146e0832faSShawn Lin * ... 1156e0832faSShawn Lin * Group 7: 1792-2047 1166e0832faSShawn Lin * - Each 256-vector group is divided into 16 16-vector groups 1176e0832faSShawn Lin * As an example: 16 16-vector groups for 256-vector group 0-255 is 1186e0832faSShawn Lin * Group 0: 0-15 1196e0832faSShawn Lin * Group 1: 16-32 1206e0832faSShawn Lin * ... 1216e0832faSShawn Lin * Group 15: 240-255 1226e0832faSShawn Lin * - The termination address of MSI vector in 256-vector group n and 16-vector 1236e0832faSShawn Lin * group x is the address of MSIxIRn 1246e0832faSShawn Lin * - The data for MSI vector in 16-vector group x is x 1256e0832faSShawn Lin */ 1266e0832faSShawn Lin static u32 hwirq_to_reg_set(unsigned long hwirq) 1276e0832faSShawn Lin { 1286e0832faSShawn Lin return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); 1296e0832faSShawn Lin } 1306e0832faSShawn Lin 1316e0832faSShawn Lin static u32 hwirq_to_group(unsigned long hwirq) 1326e0832faSShawn Lin { 1336e0832faSShawn Lin return (hwirq % NR_HW_IRQS); 1346e0832faSShawn Lin } 1356e0832faSShawn Lin 1366e0832faSShawn Lin static u32 hwirq_to_msi_data(unsigned long hwirq) 1376e0832faSShawn Lin { 1386e0832faSShawn Lin return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); 1396e0832faSShawn Lin } 1406e0832faSShawn Lin 1416e0832faSShawn Lin static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 1426e0832faSShawn Lin { 1436e0832faSShawn Lin struct xgene_msi *msi = irq_data_get_irq_chip_data(data); 1446e0832faSShawn Lin u32 reg_set = hwirq_to_reg_set(data->hwirq); 1456e0832faSShawn Lin u32 group = hwirq_to_group(data->hwirq); 1466e0832faSShawn Lin u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16); 1476e0832faSShawn Lin 1486e0832faSShawn Lin msg->address_hi = upper_32_bits(target_addr); 1496e0832faSShawn Lin msg->address_lo = lower_32_bits(target_addr); 1506e0832faSShawn Lin msg->data = hwirq_to_msi_data(data->hwirq); 1516e0832faSShawn Lin } 1526e0832faSShawn Lin 1536e0832faSShawn Lin /* 1546e0832faSShawn Lin * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain 1556e0832faSShawn Lin * the expected behaviour of .set_affinity for each MSI interrupt, the 16 1566e0832faSShawn Lin * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs 1576e0832faSShawn Lin * for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another 1586e0832faSShawn Lin * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a 1596e0832faSShawn Lin * consequence, the total MSI vectors that X-Gene v1 supports will be 1606e0832faSShawn Lin * reduced to 256 (2048/8) vectors. 1616e0832faSShawn Lin */ 1626e0832faSShawn Lin static int hwirq_to_cpu(unsigned long hwirq) 1636e0832faSShawn Lin { 1646e0832faSShawn Lin return (hwirq % xgene_msi_ctrl.num_cpus); 1656e0832faSShawn Lin } 1666e0832faSShawn Lin 1676e0832faSShawn Lin static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) 1686e0832faSShawn Lin { 1696e0832faSShawn Lin return (hwirq - hwirq_to_cpu(hwirq)); 1706e0832faSShawn Lin } 1716e0832faSShawn Lin 1726e0832faSShawn Lin static int xgene_msi_set_affinity(struct irq_data *irqdata, 1736e0832faSShawn Lin const struct cpumask *mask, bool force) 1746e0832faSShawn Lin { 1756e0832faSShawn Lin int target_cpu = cpumask_first(mask); 1766e0832faSShawn Lin int curr_cpu; 1776e0832faSShawn Lin 1786e0832faSShawn Lin curr_cpu = hwirq_to_cpu(irqdata->hwirq); 1796e0832faSShawn Lin if (curr_cpu == target_cpu) 1806e0832faSShawn Lin return IRQ_SET_MASK_OK_DONE; 1816e0832faSShawn Lin 1826e0832faSShawn Lin /* Update MSI number to target the new CPU */ 1836e0832faSShawn Lin irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu; 1846e0832faSShawn Lin 1856e0832faSShawn Lin return IRQ_SET_MASK_OK; 1866e0832faSShawn Lin } 1876e0832faSShawn Lin 1886e0832faSShawn Lin static struct irq_chip xgene_msi_bottom_irq_chip = { 1896e0832faSShawn Lin .name = "MSI", 1906e0832faSShawn Lin .irq_set_affinity = xgene_msi_set_affinity, 1916e0832faSShawn Lin .irq_compose_msi_msg = xgene_compose_msi_msg, 1926e0832faSShawn Lin }; 1936e0832faSShawn Lin 1946e0832faSShawn Lin static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1956e0832faSShawn Lin unsigned int nr_irqs, void *args) 1966e0832faSShawn Lin { 1976e0832faSShawn Lin struct xgene_msi *msi = domain->host_data; 1986e0832faSShawn Lin int msi_irq; 1996e0832faSShawn Lin 2006e0832faSShawn Lin mutex_lock(&msi->bitmap_lock); 2016e0832faSShawn Lin 2026e0832faSShawn Lin msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, 2036e0832faSShawn Lin msi->num_cpus, 0); 2046e0832faSShawn Lin if (msi_irq < NR_MSI_VEC) 2056e0832faSShawn Lin bitmap_set(msi->bitmap, msi_irq, msi->num_cpus); 2066e0832faSShawn Lin else 2076e0832faSShawn Lin msi_irq = -ENOSPC; 2086e0832faSShawn Lin 2096e0832faSShawn Lin mutex_unlock(&msi->bitmap_lock); 2106e0832faSShawn Lin 2116e0832faSShawn Lin if (msi_irq < 0) 2126e0832faSShawn Lin return msi_irq; 2136e0832faSShawn Lin 2146e0832faSShawn Lin irq_domain_set_info(domain, virq, msi_irq, 2156e0832faSShawn Lin &xgene_msi_bottom_irq_chip, domain->host_data, 2166e0832faSShawn Lin handle_simple_irq, NULL, NULL); 2176e0832faSShawn Lin 2186e0832faSShawn Lin return 0; 2196e0832faSShawn Lin } 2206e0832faSShawn Lin 2216e0832faSShawn Lin static void xgene_irq_domain_free(struct irq_domain *domain, 2226e0832faSShawn Lin unsigned int virq, unsigned int nr_irqs) 2236e0832faSShawn Lin { 2246e0832faSShawn Lin struct irq_data *d = irq_domain_get_irq_data(domain, virq); 2256e0832faSShawn Lin struct xgene_msi *msi = irq_data_get_irq_chip_data(d); 2266e0832faSShawn Lin u32 hwirq; 2276e0832faSShawn Lin 2286e0832faSShawn Lin mutex_lock(&msi->bitmap_lock); 2296e0832faSShawn Lin 2306e0832faSShawn Lin hwirq = hwirq_to_canonical_hwirq(d->hwirq); 2316e0832faSShawn Lin bitmap_clear(msi->bitmap, hwirq, msi->num_cpus); 2326e0832faSShawn Lin 2336e0832faSShawn Lin mutex_unlock(&msi->bitmap_lock); 2346e0832faSShawn Lin 2356e0832faSShawn Lin irq_domain_free_irqs_parent(domain, virq, nr_irqs); 2366e0832faSShawn Lin } 2376e0832faSShawn Lin 2386e0832faSShawn Lin static const struct irq_domain_ops msi_domain_ops = { 2396e0832faSShawn Lin .alloc = xgene_irq_domain_alloc, 2406e0832faSShawn Lin .free = xgene_irq_domain_free, 2416e0832faSShawn Lin }; 2426e0832faSShawn Lin 2436e0832faSShawn Lin static int xgene_allocate_domains(struct xgene_msi *msi) 2446e0832faSShawn Lin { 2456e0832faSShawn Lin msi->inner_domain = irq_domain_add_linear(NULL, NR_MSI_VEC, 2466e0832faSShawn Lin &msi_domain_ops, msi); 2476e0832faSShawn Lin if (!msi->inner_domain) 2486e0832faSShawn Lin return -ENOMEM; 2496e0832faSShawn Lin 2506e0832faSShawn Lin msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(msi->node), 2516e0832faSShawn Lin &xgene_msi_domain_info, 2526e0832faSShawn Lin msi->inner_domain); 2536e0832faSShawn Lin 2546e0832faSShawn Lin if (!msi->msi_domain) { 2556e0832faSShawn Lin irq_domain_remove(msi->inner_domain); 2566e0832faSShawn Lin return -ENOMEM; 2576e0832faSShawn Lin } 2586e0832faSShawn Lin 2596e0832faSShawn Lin return 0; 2606e0832faSShawn Lin } 2616e0832faSShawn Lin 2626e0832faSShawn Lin static void xgene_free_domains(struct xgene_msi *msi) 2636e0832faSShawn Lin { 2646e0832faSShawn Lin if (msi->msi_domain) 2656e0832faSShawn Lin irq_domain_remove(msi->msi_domain); 2666e0832faSShawn Lin if (msi->inner_domain) 2676e0832faSShawn Lin irq_domain_remove(msi->inner_domain); 2686e0832faSShawn Lin } 2696e0832faSShawn Lin 2706e0832faSShawn Lin static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) 2716e0832faSShawn Lin { 2721ed9b961SChristophe JAILLET xgene_msi->bitmap = bitmap_zalloc(NR_MSI_VEC, GFP_KERNEL); 2736e0832faSShawn Lin if (!xgene_msi->bitmap) 2746e0832faSShawn Lin return -ENOMEM; 2756e0832faSShawn Lin 2766e0832faSShawn Lin mutex_init(&xgene_msi->bitmap_lock); 2776e0832faSShawn Lin 2786e0832faSShawn Lin xgene_msi->msi_groups = kcalloc(NR_HW_IRQS, 2796e0832faSShawn Lin sizeof(struct xgene_msi_group), 2806e0832faSShawn Lin GFP_KERNEL); 2816e0832faSShawn Lin if (!xgene_msi->msi_groups) 2826e0832faSShawn Lin return -ENOMEM; 2836e0832faSShawn Lin 2846e0832faSShawn Lin return 0; 2856e0832faSShawn Lin } 2866e0832faSShawn Lin 2876e0832faSShawn Lin static void xgene_msi_isr(struct irq_desc *desc) 2886e0832faSShawn Lin { 2896e0832faSShawn Lin struct irq_chip *chip = irq_desc_get_chip(desc); 2906e0832faSShawn Lin struct xgene_msi_group *msi_groups; 2916e0832faSShawn Lin struct xgene_msi *xgene_msi; 292d21faba1SMarc Zyngier int msir_index, msir_val, hw_irq, ret; 2936e0832faSShawn Lin u32 intr_index, grp_select, msi_grp; 2946e0832faSShawn Lin 2956e0832faSShawn Lin chained_irq_enter(chip, desc); 2966e0832faSShawn Lin 2976e0832faSShawn Lin msi_groups = irq_desc_get_handler_data(desc); 2986e0832faSShawn Lin xgene_msi = msi_groups->msi; 2996e0832faSShawn Lin msi_grp = msi_groups->msi_grp; 3006e0832faSShawn Lin 3016e0832faSShawn Lin /* 3026e0832faSShawn Lin * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt 303b2105b9fSKrzysztof Wilczyński * If bit x of this register is set (x is 0..7), one or more interrupts 3046e0832faSShawn Lin * corresponding to MSInIRx is set. 3056e0832faSShawn Lin */ 3066e0832faSShawn Lin grp_select = xgene_msi_int_read(xgene_msi, msi_grp); 3076e0832faSShawn Lin while (grp_select) { 3086e0832faSShawn Lin msir_index = ffs(grp_select) - 1; 3096e0832faSShawn Lin /* 3106e0832faSShawn Lin * Calculate MSInIRx address to read to check for interrupts 3116e0832faSShawn Lin * (refer to termination address and data assignment 3126e0832faSShawn Lin * described in xgene_compose_msi_msg() ) 3136e0832faSShawn Lin */ 3146e0832faSShawn Lin msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index); 3156e0832faSShawn Lin while (msir_val) { 3166e0832faSShawn Lin intr_index = ffs(msir_val) - 1; 3176e0832faSShawn Lin /* 3186e0832faSShawn Lin * Calculate MSI vector number (refer to the termination 3196e0832faSShawn Lin * address and data assignment described in 3206e0832faSShawn Lin * xgene_compose_msi_msg function) 3216e0832faSShawn Lin */ 3226e0832faSShawn Lin hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) * 3236e0832faSShawn Lin NR_HW_IRQS) + msi_grp; 3246e0832faSShawn Lin /* 3256e0832faSShawn Lin * As we have multiple hw_irq that maps to single MSI, 3266e0832faSShawn Lin * always look up the virq using the hw_irq as seen from 3276e0832faSShawn Lin * CPU0 3286e0832faSShawn Lin */ 3296e0832faSShawn Lin hw_irq = hwirq_to_canonical_hwirq(hw_irq); 330d21faba1SMarc Zyngier ret = generic_handle_domain_irq(xgene_msi->inner_domain, hw_irq); 331d21faba1SMarc Zyngier WARN_ON_ONCE(ret); 3326e0832faSShawn Lin msir_val &= ~(1 << intr_index); 3336e0832faSShawn Lin } 3346e0832faSShawn Lin grp_select &= ~(1 << msir_index); 3356e0832faSShawn Lin 3366e0832faSShawn Lin if (!grp_select) { 3376e0832faSShawn Lin /* 3386e0832faSShawn Lin * We handled all interrupts happened in this group, 3396e0832faSShawn Lin * resample this group MSI_INTx register in case 3406e0832faSShawn Lin * something else has been made pending in the meantime 3416e0832faSShawn Lin */ 3426e0832faSShawn Lin grp_select = xgene_msi_int_read(xgene_msi, msi_grp); 3436e0832faSShawn Lin } 3446e0832faSShawn Lin } 3456e0832faSShawn Lin 3466e0832faSShawn Lin chained_irq_exit(chip, desc); 3476e0832faSShawn Lin } 3486e0832faSShawn Lin 3496e0832faSShawn Lin static enum cpuhp_state pci_xgene_online; 3506e0832faSShawn Lin 351*afbb9130SUwe Kleine-König static void xgene_msi_remove(struct platform_device *pdev) 3526e0832faSShawn Lin { 3536e0832faSShawn Lin struct xgene_msi *msi = platform_get_drvdata(pdev); 3546e0832faSShawn Lin 3556e0832faSShawn Lin if (pci_xgene_online) 3566e0832faSShawn Lin cpuhp_remove_state(pci_xgene_online); 3576e0832faSShawn Lin cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD); 3586e0832faSShawn Lin 3596e0832faSShawn Lin kfree(msi->msi_groups); 3606e0832faSShawn Lin 3611ed9b961SChristophe JAILLET bitmap_free(msi->bitmap); 3626e0832faSShawn Lin msi->bitmap = NULL; 3636e0832faSShawn Lin 3646e0832faSShawn Lin xgene_free_domains(msi); 3656e0832faSShawn Lin } 3666e0832faSShawn Lin 3676e0832faSShawn Lin static int xgene_msi_hwirq_alloc(unsigned int cpu) 3686e0832faSShawn Lin { 3696e0832faSShawn Lin struct xgene_msi *msi = &xgene_msi_ctrl; 3706e0832faSShawn Lin struct xgene_msi_group *msi_group; 3716e0832faSShawn Lin cpumask_var_t mask; 3726e0832faSShawn Lin int i; 3736e0832faSShawn Lin int err; 3746e0832faSShawn Lin 3756e0832faSShawn Lin for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { 3766e0832faSShawn Lin msi_group = &msi->msi_groups[i]; 3776e0832faSShawn Lin if (!msi_group->gic_irq) 3786e0832faSShawn Lin continue; 3796e0832faSShawn Lin 380a93c00e5SMartin Kaiser irq_set_chained_handler_and_data(msi_group->gic_irq, 381a93c00e5SMartin Kaiser xgene_msi_isr, msi_group); 382a93c00e5SMartin Kaiser 3836e0832faSShawn Lin /* 3846e0832faSShawn Lin * Statically allocate MSI GIC IRQs to each CPU core. 3856e0832faSShawn Lin * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated 3866e0832faSShawn Lin * to each core. 3876e0832faSShawn Lin */ 3886e0832faSShawn Lin if (alloc_cpumask_var(&mask, GFP_KERNEL)) { 3896e0832faSShawn Lin cpumask_clear(mask); 3906e0832faSShawn Lin cpumask_set_cpu(cpu, mask); 3916e0832faSShawn Lin err = irq_set_affinity(msi_group->gic_irq, mask); 3926e0832faSShawn Lin if (err) 3936e0832faSShawn Lin pr_err("failed to set affinity for GIC IRQ"); 3946e0832faSShawn Lin free_cpumask_var(mask); 3956e0832faSShawn Lin } else { 3966e0832faSShawn Lin pr_err("failed to alloc CPU mask for affinity\n"); 3976e0832faSShawn Lin err = -EINVAL; 3986e0832faSShawn Lin } 3996e0832faSShawn Lin 4006e0832faSShawn Lin if (err) { 4016e0832faSShawn Lin irq_set_chained_handler_and_data(msi_group->gic_irq, 4026e0832faSShawn Lin NULL, NULL); 4036e0832faSShawn Lin return err; 4046e0832faSShawn Lin } 4056e0832faSShawn Lin } 4066e0832faSShawn Lin 4076e0832faSShawn Lin return 0; 4086e0832faSShawn Lin } 4096e0832faSShawn Lin 4106e0832faSShawn Lin static int xgene_msi_hwirq_free(unsigned int cpu) 4116e0832faSShawn Lin { 4126e0832faSShawn Lin struct xgene_msi *msi = &xgene_msi_ctrl; 4136e0832faSShawn Lin struct xgene_msi_group *msi_group; 4146e0832faSShawn Lin int i; 4156e0832faSShawn Lin 4166e0832faSShawn Lin for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { 4176e0832faSShawn Lin msi_group = &msi->msi_groups[i]; 4186e0832faSShawn Lin if (!msi_group->gic_irq) 4196e0832faSShawn Lin continue; 4206e0832faSShawn Lin 4216e0832faSShawn Lin irq_set_chained_handler_and_data(msi_group->gic_irq, NULL, 4226e0832faSShawn Lin NULL); 4236e0832faSShawn Lin } 4246e0832faSShawn Lin return 0; 4256e0832faSShawn Lin } 4266e0832faSShawn Lin 4276e0832faSShawn Lin static const struct of_device_id xgene_msi_match_table[] = { 4286e0832faSShawn Lin {.compatible = "apm,xgene1-msi"}, 4296e0832faSShawn Lin {}, 4306e0832faSShawn Lin }; 4316e0832faSShawn Lin 4326e0832faSShawn Lin static int xgene_msi_probe(struct platform_device *pdev) 4336e0832faSShawn Lin { 4346e0832faSShawn Lin struct resource *res; 4356e0832faSShawn Lin int rc, irq_index; 4366e0832faSShawn Lin struct xgene_msi *xgene_msi; 4376e0832faSShawn Lin int virt_msir; 4386e0832faSShawn Lin u32 msi_val, msi_idx; 4396e0832faSShawn Lin 4406e0832faSShawn Lin xgene_msi = &xgene_msi_ctrl; 4416e0832faSShawn Lin 4426e0832faSShawn Lin platform_set_drvdata(pdev, xgene_msi); 4436e0832faSShawn Lin 4446e0832faSShawn Lin res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4456e0832faSShawn Lin xgene_msi->msi_regs = devm_ioremap_resource(&pdev->dev, res); 4466e0832faSShawn Lin if (IS_ERR(xgene_msi->msi_regs)) { 4476e0832faSShawn Lin rc = PTR_ERR(xgene_msi->msi_regs); 4486e0832faSShawn Lin goto error; 4496e0832faSShawn Lin } 4506e0832faSShawn Lin xgene_msi->msi_addr = res->start; 4516e0832faSShawn Lin xgene_msi->node = pdev->dev.of_node; 4526e0832faSShawn Lin xgene_msi->num_cpus = num_possible_cpus(); 4536e0832faSShawn Lin 4546e0832faSShawn Lin rc = xgene_msi_init_allocator(xgene_msi); 4556e0832faSShawn Lin if (rc) { 4566e0832faSShawn Lin dev_err(&pdev->dev, "Error allocating MSI bitmap\n"); 4576e0832faSShawn Lin goto error; 4586e0832faSShawn Lin } 4596e0832faSShawn Lin 4606e0832faSShawn Lin rc = xgene_allocate_domains(xgene_msi); 4616e0832faSShawn Lin if (rc) { 4626e0832faSShawn Lin dev_err(&pdev->dev, "Failed to allocate MSI domain\n"); 4636e0832faSShawn Lin goto error; 4646e0832faSShawn Lin } 4656e0832faSShawn Lin 4666e0832faSShawn Lin for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { 4676e0832faSShawn Lin virt_msir = platform_get_irq(pdev, irq_index); 4686e0832faSShawn Lin if (virt_msir < 0) { 4696e0832faSShawn Lin rc = virt_msir; 4706e0832faSShawn Lin goto error; 4716e0832faSShawn Lin } 4726e0832faSShawn Lin xgene_msi->msi_groups[irq_index].gic_irq = virt_msir; 4736e0832faSShawn Lin xgene_msi->msi_groups[irq_index].msi_grp = irq_index; 4746e0832faSShawn Lin xgene_msi->msi_groups[irq_index].msi = xgene_msi; 4756e0832faSShawn Lin } 4766e0832faSShawn Lin 4776e0832faSShawn Lin /* 4786e0832faSShawn Lin * MSInIRx registers are read-to-clear; before registering 4796e0832faSShawn Lin * interrupt handlers, read all of them to clear spurious 4806e0832faSShawn Lin * interrupts that may occur before the driver is probed. 4816e0832faSShawn Lin */ 4826e0832faSShawn Lin for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { 4836e0832faSShawn Lin for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++) 484026b940fSKrzysztof Wilczyński xgene_msi_ir_read(xgene_msi, irq_index, msi_idx); 485026b940fSKrzysztof Wilczyński 4866e0832faSShawn Lin /* Read MSIINTn to confirm */ 4876e0832faSShawn Lin msi_val = xgene_msi_int_read(xgene_msi, irq_index); 4886e0832faSShawn Lin if (msi_val) { 4896e0832faSShawn Lin dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); 4906e0832faSShawn Lin rc = -EINVAL; 4916e0832faSShawn Lin goto error; 4926e0832faSShawn Lin } 4936e0832faSShawn Lin } 4946e0832faSShawn Lin 4956e0832faSShawn Lin rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online", 4966e0832faSShawn Lin xgene_msi_hwirq_alloc, NULL); 4976e0832faSShawn Lin if (rc < 0) 4986e0832faSShawn Lin goto err_cpuhp; 4996e0832faSShawn Lin pci_xgene_online = rc; 5006e0832faSShawn Lin rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL, 5016e0832faSShawn Lin xgene_msi_hwirq_free); 5026e0832faSShawn Lin if (rc) 5036e0832faSShawn Lin goto err_cpuhp; 5046e0832faSShawn Lin 5056e0832faSShawn Lin dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n"); 5066e0832faSShawn Lin 5076e0832faSShawn Lin return 0; 5086e0832faSShawn Lin 5096e0832faSShawn Lin err_cpuhp: 5106e0832faSShawn Lin dev_err(&pdev->dev, "failed to add CPU MSI notifier\n"); 5116e0832faSShawn Lin error: 5126e0832faSShawn Lin xgene_msi_remove(pdev); 5136e0832faSShawn Lin return rc; 5146e0832faSShawn Lin } 5156e0832faSShawn Lin 5166e0832faSShawn Lin static struct platform_driver xgene_msi_driver = { 5176e0832faSShawn Lin .driver = { 5186e0832faSShawn Lin .name = "xgene-msi", 5196e0832faSShawn Lin .of_match_table = xgene_msi_match_table, 5206e0832faSShawn Lin }, 5216e0832faSShawn Lin .probe = xgene_msi_probe, 522*afbb9130SUwe Kleine-König .remove_new = xgene_msi_remove, 5236e0832faSShawn Lin }; 5246e0832faSShawn Lin 5256e0832faSShawn Lin static int __init xgene_pcie_msi_init(void) 5266e0832faSShawn Lin { 5276e0832faSShawn Lin return platform_driver_register(&xgene_msi_driver); 5286e0832faSShawn Lin } 5296e0832faSShawn Lin subsys_initcall(xgene_pcie_msi_init); 530