1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * Based on the code from arch/arm/mach-integrator/pci_v3.c 7 * Copyright (C) 1999 ARM Limited 8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd 9 * 10 * Contributors to the old driver include: 11 * Russell King <linux@armlinux.org.uk> 12 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite) 13 * Rob Herring <robh@kernel.org> 14 * Liviu Dudau <Liviu.Dudau@arm.com> 15 * Grant Likely <grant.likely@secretlab.ca> 16 * Arnd Bergmann <arnd@arndb.de> 17 * Bjorn Helgaas <bhelgaas@google.com> 18 */ 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_pci.h> 27 #include <linux/pci.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 #include <linux/bitops.h> 31 #include <linux/irq.h> 32 #include <linux/mfd/syscon.h> 33 #include <linux/regmap.h> 34 #include <linux/clk.h> 35 36 #include "../pci.h" 37 38 #define V3_PCI_VENDOR 0x00000000 39 #define V3_PCI_DEVICE 0x00000002 40 #define V3_PCI_CMD 0x00000004 41 #define V3_PCI_STAT 0x00000006 42 #define V3_PCI_CC_REV 0x00000008 43 #define V3_PCI_HDR_CFG 0x0000000C 44 #define V3_PCI_IO_BASE 0x00000010 45 #define V3_PCI_BASE0 0x00000014 46 #define V3_PCI_BASE1 0x00000018 47 #define V3_PCI_SUB_VENDOR 0x0000002C 48 #define V3_PCI_SUB_ID 0x0000002E 49 #define V3_PCI_ROM 0x00000030 50 #define V3_PCI_BPARAM 0x0000003C 51 #define V3_PCI_MAP0 0x00000040 52 #define V3_PCI_MAP1 0x00000044 53 #define V3_PCI_INT_STAT 0x00000048 54 #define V3_PCI_INT_CFG 0x0000004C 55 #define V3_LB_BASE0 0x00000054 56 #define V3_LB_BASE1 0x00000058 57 #define V3_LB_MAP0 0x0000005E 58 #define V3_LB_MAP1 0x00000062 59 #define V3_LB_BASE2 0x00000064 60 #define V3_LB_MAP2 0x00000066 61 #define V3_LB_SIZE 0x00000068 62 #define V3_LB_IO_BASE 0x0000006E 63 #define V3_FIFO_CFG 0x00000070 64 #define V3_FIFO_PRIORITY 0x00000072 65 #define V3_FIFO_STAT 0x00000074 66 #define V3_LB_ISTAT 0x00000076 67 #define V3_LB_IMASK 0x00000077 68 #define V3_SYSTEM 0x00000078 69 #define V3_LB_CFG 0x0000007A 70 #define V3_PCI_CFG 0x0000007C 71 #define V3_DMA_PCI_ADR0 0x00000080 72 #define V3_DMA_PCI_ADR1 0x00000090 73 #define V3_DMA_LOCAL_ADR0 0x00000084 74 #define V3_DMA_LOCAL_ADR1 0x00000094 75 #define V3_DMA_LENGTH0 0x00000088 76 #define V3_DMA_LENGTH1 0x00000098 77 #define V3_DMA_CSR0 0x0000008B 78 #define V3_DMA_CSR1 0x0000009B 79 #define V3_DMA_CTLB_ADR0 0x0000008C 80 #define V3_DMA_CTLB_ADR1 0x0000009C 81 #define V3_DMA_DELAY 0x000000E0 82 #define V3_MAIL_DATA 0x000000C0 83 #define V3_PCI_MAIL_IEWR 0x000000D0 84 #define V3_PCI_MAIL_IERD 0x000000D2 85 #define V3_LB_MAIL_IEWR 0x000000D4 86 #define V3_LB_MAIL_IERD 0x000000D6 87 #define V3_MAIL_WR_STAT 0x000000D8 88 #define V3_MAIL_RD_STAT 0x000000DA 89 #define V3_QBA_MAP 0x000000DC 90 91 /* PCI STATUS bits */ 92 #define V3_PCI_STAT_PAR_ERR BIT(15) 93 #define V3_PCI_STAT_SYS_ERR BIT(14) 94 #define V3_PCI_STAT_M_ABORT_ERR BIT(13) 95 #define V3_PCI_STAT_T_ABORT_ERR BIT(12) 96 97 /* LB ISTAT bits */ 98 #define V3_LB_ISTAT_MAILBOX BIT(7) 99 #define V3_LB_ISTAT_PCI_RD BIT(6) 100 #define V3_LB_ISTAT_PCI_WR BIT(5) 101 #define V3_LB_ISTAT_PCI_INT BIT(4) 102 #define V3_LB_ISTAT_PCI_PERR BIT(3) 103 #define V3_LB_ISTAT_I2O_QWR BIT(2) 104 #define V3_LB_ISTAT_DMA1 BIT(1) 105 #define V3_LB_ISTAT_DMA0 BIT(0) 106 107 /* PCI COMMAND bits */ 108 #define V3_COMMAND_M_FBB_EN BIT(9) 109 #define V3_COMMAND_M_SERR_EN BIT(8) 110 #define V3_COMMAND_M_PAR_EN BIT(6) 111 #define V3_COMMAND_M_MASTER_EN BIT(2) 112 #define V3_COMMAND_M_MEM_EN BIT(1) 113 #define V3_COMMAND_M_IO_EN BIT(0) 114 115 /* SYSTEM bits */ 116 #define V3_SYSTEM_M_RST_OUT BIT(15) 117 #define V3_SYSTEM_M_LOCK BIT(14) 118 #define V3_SYSTEM_UNLOCK 0xa05f 119 120 /* PCI CFG bits */ 121 #define V3_PCI_CFG_M_I2O_EN BIT(15) 122 #define V3_PCI_CFG_M_IO_REG_DIS BIT(14) 123 #define V3_PCI_CFG_M_IO_DIS BIT(13) 124 #define V3_PCI_CFG_M_EN3V BIT(12) 125 #define V3_PCI_CFG_M_RETRY_EN BIT(10) 126 #define V3_PCI_CFG_M_AD_LOW1 BIT(9) 127 #define V3_PCI_CFG_M_AD_LOW0 BIT(8) 128 /* 129 * This is the value applied to C/BE[3:1], with bit 0 always held 0 130 * during DMA access. 131 */ 132 #define V3_PCI_CFG_M_RTYPE_SHIFT 5 133 #define V3_PCI_CFG_M_WTYPE_SHIFT 1 134 #define V3_PCI_CFG_TYPE_DEFAULT 0x3 135 136 /* PCI BASE bits (PCI -> Local Bus) */ 137 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U 138 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U 139 #define V3_PCI_BASE_M_PREFETCH BIT(3) 140 #define V3_PCI_BASE_M_TYPE (3 << 1) 141 #define V3_PCI_BASE_M_IO BIT(0) 142 143 /* PCI MAP bits (PCI -> Local bus) */ 144 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U 145 #define V3_PCI_MAP_M_RD_POST_INH BIT(15) 146 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) 147 #define V3_PCI_MAP_M_SWAP (3 << 8) 148 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U 149 #define V3_PCI_MAP_M_REG_EN BIT(1) 150 #define V3_PCI_MAP_M_ENABLE BIT(0) 151 152 /* LB_BASE0,1 bits (Local bus -> PCI) */ 153 #define V3_LB_BASE_ADR_BASE 0xfff00000U 154 #define V3_LB_BASE_SWAP (3 << 8) 155 #define V3_LB_BASE_ADR_SIZE (15 << 4) 156 #define V3_LB_BASE_PREFETCH BIT(3) 157 #define V3_LB_BASE_ENABLE BIT(0) 158 159 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) 160 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) 161 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) 162 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) 163 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) 164 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) 165 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) 166 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) 167 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) 168 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) 169 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) 170 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) 171 172 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) 173 174 /* LB_MAP0,1 bits (Local bus -> PCI) */ 175 #define V3_LB_MAP_MAP_ADR 0xfff0U 176 #define V3_LB_MAP_TYPE (7 << 1) 177 #define V3_LB_MAP_AD_LOW_EN BIT(0) 178 179 #define V3_LB_MAP_TYPE_IACK (0 << 1) 180 #define V3_LB_MAP_TYPE_IO (1 << 1) 181 #define V3_LB_MAP_TYPE_MEM (3 << 1) 182 #define V3_LB_MAP_TYPE_CONFIG (5 << 1) 183 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) 184 185 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) 186 187 /* LB_BASE2 bits (Local bus -> PCI IO) */ 188 #define V3_LB_BASE2_ADR_BASE 0xff00U 189 #define V3_LB_BASE2_SWAP_AUTO (3 << 6) 190 #define V3_LB_BASE2_ENABLE BIT(0) 191 192 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) 193 194 /* LB_MAP2 bits (Local bus -> PCI IO) */ 195 #define V3_LB_MAP2_MAP_ADR 0xff00U 196 197 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) 198 199 /* FIFO priority bits */ 200 #define V3_FIFO_PRIO_LOCAL BIT(12) 201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10) 202 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11) 203 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11)) 204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8) 205 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9) 206 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9)) 207 #define V3_FIFO_PRIO_PCI BIT(4) 208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2) 209 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3) 210 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3)) 211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0) 212 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1) 213 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1)) 214 215 /* Local bus configuration bits */ 216 #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000 217 #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13) 218 #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14) 219 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14)) 220 #define V3_LB_CFG_LB_RST BIT(12) 221 #define V3_LB_CFG_LB_PPC_RDY BIT(11) 222 #define V3_LB_CFG_LB_LB_INT BIT(10) 223 #define V3_LB_CFG_LB_ERR_EN BIT(9) 224 #define V3_LB_CFG_LB_RDY_EN BIT(8) 225 #define V3_LB_CFG_LB_BE_IMODE BIT(7) 226 #define V3_LB_CFG_LB_BE_OMODE BIT(6) 227 #define V3_LB_CFG_LB_ENDIAN BIT(5) 228 #define V3_LB_CFG_LB_PARK_EN BIT(4) 229 #define V3_LB_CFG_LB_FBB_DIS BIT(2) 230 231 /* ARM Integrator-specific extended control registers */ 232 #define INTEGRATOR_SC_PCI_OFFSET 0x18 233 #define INTEGRATOR_SC_PCI_ENABLE BIT(0) 234 #define INTEGRATOR_SC_PCI_INTCLR BIT(1) 235 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20 236 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24 237 238 struct v3_pci { 239 struct device *dev; 240 void __iomem *base; 241 void __iomem *config_base; 242 u32 config_mem; 243 u32 non_pre_mem; 244 u32 pre_mem; 245 phys_addr_t non_pre_bus_addr; 246 phys_addr_t pre_bus_addr; 247 struct regmap *map; 248 }; 249 250 /* 251 * The V3 PCI interface chip in Integrator provides several windows from 252 * local bus memory into the PCI memory areas. Unfortunately, there 253 * are not really enough windows for our usage, therefore we reuse 254 * one of the windows for access to PCI configuration space. On the 255 * Integrator/AP, the memory map is as follows: 256 * 257 * Local Bus Memory Usage 258 * 259 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable 260 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable 261 * 60000000 - 60FFFFFF PCI IO. 16M 262 * 61000000 - 61FFFFFF PCI Configuration. 16M 263 * 264 * There are three V3 windows, each described by a pair of V3 registers. 265 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. 266 * Base0 and Base1 can be used for any type of PCI memory access. Base2 267 * can be used either for PCI I/O or for I20 accesses. By default, uHAL 268 * uses this only for PCI IO space. 269 * 270 * Normally these spaces are mapped using the following base registers: 271 * 272 * Usage Local Bus Memory Base/Map registers used 273 * 274 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 275 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 276 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 277 * Cfg 61000000 - 61FFFFFF 278 * 279 * This means that I20 and PCI configuration space accesses will fail. 280 * When PCI configuration accesses are needed (via the uHAL PCI 281 * configuration space primitives) we must remap the spaces as follows: 282 * 283 * Usage Local Bus Memory Base/Map registers used 284 * 285 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 286 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 287 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 288 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 289 * 290 * To make this work, the code depends on overlapping windows working. 291 * The V3 chip translates an address by checking its range within 292 * each of the BASE/MAP pairs in turn (in ascending register number 293 * order). It will use the first matching pair. So, for example, 294 * if the same address is mapped by both LB_BASE0/LB_MAP0 and 295 * LB_BASE1/LB_MAP1, the V3 will use the translation from 296 * LB_BASE0/LB_MAP0. 297 * 298 * To allow PCI Configuration space access, the code enlarges the 299 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes 300 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can 301 * be remapped for use by configuration cycles. 302 * 303 * At the end of the PCI Configuration space accesses, 304 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window 305 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to 306 * reveal the now restored LB_BASE1/LB_MAP1 window. 307 * 308 * NOTE: We do not set up I2O mapping. I suspect that this is only 309 * for an intelligent (target) device. Using I2O disables most of 310 * the mappings into PCI memory. 311 */ 312 static void __iomem *v3_map_bus(struct pci_bus *bus, 313 unsigned int devfn, int offset) 314 { 315 struct v3_pci *v3 = bus->sysdata; 316 unsigned int address, mapaddress, busnr; 317 318 busnr = bus->number; 319 if (busnr == 0) { 320 int slot = PCI_SLOT(devfn); 321 322 /* 323 * local bus segment so need a type 0 config cycle 324 * 325 * build the PCI configuration "address" with one-hot in 326 * A31-A11 327 * 328 * mapaddress: 329 * 3:1 = config cycle (101) 330 * 0 = PCI A1 & A0 are 0 (0) 331 */ 332 address = PCI_FUNC(devfn) << 8; 333 mapaddress = V3_LB_MAP_TYPE_CONFIG; 334 335 if (slot > 12) 336 /* 337 * high order bits are handled by the MAP register 338 */ 339 mapaddress |= BIT(slot - 5); 340 else 341 /* 342 * low order bits handled directly in the address 343 */ 344 address |= BIT(slot + 11); 345 } else { 346 /* 347 * not the local bus segment so need a type 1 config cycle 348 * 349 * address: 350 * 23:16 = bus number 351 * 15:11 = slot number (7:3 of devfn) 352 * 10:8 = func number (2:0 of devfn) 353 * 354 * mapaddress: 355 * 3:1 = config cycle (101) 356 * 0 = PCI A1 & A0 from host bus (1) 357 */ 358 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; 359 address = (busnr << 16) | (devfn << 8); 360 } 361 362 /* 363 * Set up base0 to see all 512Mbytes of memory space (not 364 * prefetchable), this frees up base1 for re-use by 365 * configuration memory 366 */ 367 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 368 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE, 369 v3->base + V3_LB_BASE0); 370 371 /* 372 * Set up base1/map1 to point into configuration space. 373 * The config mem is always 16MB. 374 */ 375 writel(v3_addr_to_lb_base(v3->config_mem) | 376 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE, 377 v3->base + V3_LB_BASE1); 378 writew(mapaddress, v3->base + V3_LB_MAP1); 379 380 return v3->config_base + address + offset; 381 } 382 383 static void v3_unmap_bus(struct v3_pci *v3) 384 { 385 /* 386 * Reassign base1 for use by prefetchable PCI memory 387 */ 388 writel(v3_addr_to_lb_base(v3->pre_mem) | 389 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 390 V3_LB_BASE_ENABLE, 391 v3->base + V3_LB_BASE1); 392 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 393 V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 394 v3->base + V3_LB_MAP1); 395 396 /* 397 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 398 */ 399 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 400 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE, 401 v3->base + V3_LB_BASE0); 402 } 403 404 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn, 405 int config, int size, u32 *value) 406 { 407 struct v3_pci *v3 = bus->sysdata; 408 int ret; 409 410 dev_dbg(&bus->dev, 411 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 412 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); 413 ret = pci_generic_config_read(bus, fn, config, size, value); 414 v3_unmap_bus(v3); 415 return ret; 416 } 417 418 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn, 419 int config, int size, u32 value) 420 { 421 struct v3_pci *v3 = bus->sysdata; 422 int ret; 423 424 dev_dbg(&bus->dev, 425 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 426 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); 427 ret = pci_generic_config_write(bus, fn, config, size, value); 428 v3_unmap_bus(v3); 429 return ret; 430 } 431 432 static struct pci_ops v3_pci_ops = { 433 .map_bus = v3_map_bus, 434 .read = v3_pci_read_config, 435 .write = v3_pci_write_config, 436 }; 437 438 static irqreturn_t v3_irq(int irq, void *data) 439 { 440 struct v3_pci *v3 = data; 441 struct device *dev = v3->dev; 442 u32 status; 443 444 status = readw(v3->base + V3_PCI_STAT); 445 if (status & V3_PCI_STAT_PAR_ERR) 446 dev_err(dev, "parity error interrupt\n"); 447 if (status & V3_PCI_STAT_SYS_ERR) 448 dev_err(dev, "system error interrupt\n"); 449 if (status & V3_PCI_STAT_M_ABORT_ERR) 450 dev_err(dev, "master abort error interrupt\n"); 451 if (status & V3_PCI_STAT_T_ABORT_ERR) 452 dev_err(dev, "target abort error interrupt\n"); 453 writew(status, v3->base + V3_PCI_STAT); 454 455 status = readb(v3->base + V3_LB_ISTAT); 456 if (status & V3_LB_ISTAT_MAILBOX) 457 dev_info(dev, "PCI mailbox interrupt\n"); 458 if (status & V3_LB_ISTAT_PCI_RD) 459 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n"); 460 if (status & V3_LB_ISTAT_PCI_WR) 461 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n"); 462 if (status & V3_LB_ISTAT_PCI_INT) 463 dev_info(dev, "PCI pin interrupt\n"); 464 if (status & V3_LB_ISTAT_PCI_PERR) 465 dev_err(dev, "PCI parity error interrupt\n"); 466 if (status & V3_LB_ISTAT_I2O_QWR) 467 dev_info(dev, "I2O inbound post queue interrupt\n"); 468 if (status & V3_LB_ISTAT_DMA1) 469 dev_info(dev, "DMA channel 1 interrupt\n"); 470 if (status & V3_LB_ISTAT_DMA0) 471 dev_info(dev, "DMA channel 0 interrupt\n"); 472 /* Clear all possible interrupts on the local bus */ 473 writeb(0, v3->base + V3_LB_ISTAT); 474 if (v3->map) 475 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 476 INTEGRATOR_SC_PCI_ENABLE | 477 INTEGRATOR_SC_PCI_INTCLR); 478 479 return IRQ_HANDLED; 480 } 481 482 static int v3_integrator_init(struct v3_pci *v3) 483 { 484 unsigned int val; 485 486 v3->map = 487 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon"); 488 if (IS_ERR(v3->map)) { 489 dev_err(v3->dev, "no syscon\n"); 490 return -ENODEV; 491 } 492 493 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); 494 /* Take the PCI bridge out of reset, clear IRQs */ 495 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 496 INTEGRATOR_SC_PCI_ENABLE | 497 INTEGRATOR_SC_PCI_INTCLR); 498 499 if (!(val & INTEGRATOR_SC_PCI_ENABLE)) { 500 /* If we were in reset we need to sleep a bit */ 501 msleep(230); 502 503 /* Set the physical base for the controller itself */ 504 writel(0x6200, v3->base + V3_LB_IO_BASE); 505 506 /* Wait for the mailbox to settle after reset */ 507 do { 508 writeb(0xaa, v3->base + V3_MAIL_DATA); 509 writeb(0x55, v3->base + V3_MAIL_DATA + 4); 510 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && 511 readb(v3->base + V3_MAIL_DATA) != 0x55); 512 } 513 514 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); 515 516 return 0; 517 } 518 519 static int v3_pci_setup_resource(struct v3_pci *v3, 520 struct pci_host_bridge *host, 521 struct resource_entry *win) 522 { 523 struct device *dev = v3->dev; 524 struct resource *mem; 525 struct resource *io; 526 527 switch (resource_type(win->res)) { 528 case IORESOURCE_IO: 529 io = win->res; 530 531 /* Setup window 2 - PCI I/O */ 532 writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) | 533 V3_LB_BASE2_ENABLE, 534 v3->base + V3_LB_BASE2); 535 writew(v3_addr_to_lb_map2(io->start - win->offset), 536 v3->base + V3_LB_MAP2); 537 break; 538 case IORESOURCE_MEM: 539 mem = win->res; 540 if (mem->flags & IORESOURCE_PREFETCH) { 541 mem->name = "V3 PCI PRE-MEM"; 542 v3->pre_mem = mem->start; 543 v3->pre_bus_addr = mem->start - win->offset; 544 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n", 545 mem, &v3->pre_bus_addr); 546 if (resource_size(mem) != SZ_256M) { 547 dev_err(dev, "prefetchable memory range is not 256MB\n"); 548 return -EINVAL; 549 } 550 if (v3->non_pre_mem && 551 (mem->start != v3->non_pre_mem + SZ_256M)) { 552 dev_err(dev, 553 "prefetchable memory is not adjacent to non-prefetchable memory\n"); 554 return -EINVAL; 555 } 556 /* Setup window 1 - PCI prefetchable memory */ 557 writel(v3_addr_to_lb_base(v3->pre_mem) | 558 V3_LB_BASE_ADR_SIZE_256MB | 559 V3_LB_BASE_PREFETCH | 560 V3_LB_BASE_ENABLE, 561 v3->base + V3_LB_BASE1); 562 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 563 V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 564 v3->base + V3_LB_MAP1); 565 } else { 566 mem->name = "V3 PCI NON-PRE-MEM"; 567 v3->non_pre_mem = mem->start; 568 v3->non_pre_bus_addr = mem->start - win->offset; 569 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n", 570 mem, &v3->non_pre_bus_addr); 571 if (resource_size(mem) != SZ_256M) { 572 dev_err(dev, 573 "non-prefetchable memory range is not 256MB\n"); 574 return -EINVAL; 575 } 576 /* Setup window 0 - PCI non-prefetchable memory */ 577 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 578 V3_LB_BASE_ADR_SIZE_256MB | 579 V3_LB_BASE_ENABLE, 580 v3->base + V3_LB_BASE0); 581 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | 582 V3_LB_MAP_TYPE_MEM, 583 v3->base + V3_LB_MAP0); 584 } 585 break; 586 case IORESOURCE_BUS: 587 break; 588 default: 589 dev_info(dev, "Unknown resource type %lu\n", 590 resource_type(win->res)); 591 break; 592 } 593 594 return 0; 595 } 596 597 static int v3_get_dma_range_config(struct v3_pci *v3, 598 struct resource_entry *entry, 599 u32 *pci_base, u32 *pci_map) 600 { 601 struct device *dev = v3->dev; 602 u64 cpu_addr = entry->res->start; 603 u64 cpu_end = entry->res->end; 604 u64 pci_end = cpu_end - entry->offset; 605 u64 pci_addr = entry->res->start - entry->offset; 606 u32 val; 607 608 if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { 609 dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n"); 610 return -EINVAL; 611 } 612 val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE; 613 *pci_base = val; 614 615 if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { 616 dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n"); 617 return -EINVAL; 618 } 619 val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR; 620 621 switch (resource_size(entry->res)) { 622 case SZ_1M: 623 val |= V3_LB_BASE_ADR_SIZE_1MB; 624 break; 625 case SZ_2M: 626 val |= V3_LB_BASE_ADR_SIZE_2MB; 627 break; 628 case SZ_4M: 629 val |= V3_LB_BASE_ADR_SIZE_4MB; 630 break; 631 case SZ_8M: 632 val |= V3_LB_BASE_ADR_SIZE_8MB; 633 break; 634 case SZ_16M: 635 val |= V3_LB_BASE_ADR_SIZE_16MB; 636 break; 637 case SZ_32M: 638 val |= V3_LB_BASE_ADR_SIZE_32MB; 639 break; 640 case SZ_64M: 641 val |= V3_LB_BASE_ADR_SIZE_64MB; 642 break; 643 case SZ_128M: 644 val |= V3_LB_BASE_ADR_SIZE_128MB; 645 break; 646 case SZ_256M: 647 val |= V3_LB_BASE_ADR_SIZE_256MB; 648 break; 649 case SZ_512M: 650 val |= V3_LB_BASE_ADR_SIZE_512MB; 651 break; 652 case SZ_1G: 653 val |= V3_LB_BASE_ADR_SIZE_1GB; 654 break; 655 case SZ_2G: 656 val |= V3_LB_BASE_ADR_SIZE_2GB; 657 break; 658 default: 659 dev_err(v3->dev, "illegal dma memory chunk size\n"); 660 return -EINVAL; 661 } 662 val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE; 663 *pci_map = val; 664 665 dev_dbg(dev, 666 "DMA MEM CPU: 0x%016llx -> 0x%016llx => " 667 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", 668 cpu_addr, cpu_end, 669 pci_addr, pci_end, 670 *pci_base, *pci_map); 671 672 return 0; 673 } 674 675 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, 676 struct device_node *np) 677 { 678 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3); 679 struct device *dev = v3->dev; 680 struct resource_entry *entry; 681 int i = 0; 682 683 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 684 int ret; 685 u32 pci_base, pci_map; 686 687 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map); 688 if (ret) 689 return ret; 690 691 if (i == 0) { 692 writel(pci_base, v3->base + V3_PCI_BASE0); 693 writel(pci_map, v3->base + V3_PCI_MAP0); 694 } else if (i == 1) { 695 writel(pci_base, v3->base + V3_PCI_BASE1); 696 writel(pci_map, v3->base + V3_PCI_MAP1); 697 } else { 698 dev_err(dev, "too many ranges, only two supported\n"); 699 dev_err(dev, "range %d ignored\n", i); 700 } 701 i++; 702 } 703 return 0; 704 } 705 706 static int v3_pci_probe(struct platform_device *pdev) 707 { 708 struct device *dev = &pdev->dev; 709 struct device_node *np = dev->of_node; 710 struct resource *regs; 711 struct resource_entry *win; 712 struct v3_pci *v3; 713 struct pci_host_bridge *host; 714 struct clk *clk; 715 u16 val; 716 int irq; 717 int ret; 718 719 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3)); 720 if (!host) 721 return -ENOMEM; 722 723 host->ops = &v3_pci_ops; 724 v3 = pci_host_bridge_priv(host); 725 host->sysdata = v3; 726 v3->dev = dev; 727 728 /* Get and enable host clock */ 729 clk = devm_clk_get(dev, NULL); 730 if (IS_ERR(clk)) { 731 dev_err(dev, "clock not found\n"); 732 return PTR_ERR(clk); 733 } 734 ret = clk_prepare_enable(clk); 735 if (ret) { 736 dev_err(dev, "unable to enable clock\n"); 737 return ret; 738 } 739 740 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 741 v3->base = devm_ioremap_resource(dev, regs); 742 if (IS_ERR(v3->base)) 743 return PTR_ERR(v3->base); 744 /* 745 * The hardware has a register with the physical base address 746 * of the V3 controller itself, verify that this is the same 747 * as the physical memory we've remapped it from. 748 */ 749 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) 750 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n", 751 readl(v3->base + V3_LB_IO_BASE), regs); 752 753 /* Configuration space is 16MB directly mapped */ 754 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 755 if (resource_size(regs) != SZ_16M) { 756 dev_err(dev, "config mem is not 16MB!\n"); 757 return -EINVAL; 758 } 759 v3->config_mem = regs->start; 760 v3->config_base = devm_ioremap_resource(dev, regs); 761 if (IS_ERR(v3->config_base)) 762 return PTR_ERR(v3->config_base); 763 764 /* Get and request error IRQ resource */ 765 irq = platform_get_irq(pdev, 0); 766 if (irq < 0) 767 return irq; 768 769 ret = devm_request_irq(dev, irq, v3_irq, 0, 770 "PCIv3 error", v3); 771 if (ret < 0) { 772 dev_err(dev, 773 "unable to request PCIv3 error IRQ %d (%d)\n", 774 irq, ret); 775 return ret; 776 } 777 778 /* 779 * Unlock V3 registers, but only if they were previously locked. 780 */ 781 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) 782 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); 783 784 /* Disable all slave access while we set up the windows */ 785 val = readw(v3->base + V3_PCI_CMD); 786 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 787 writew(val, v3->base + V3_PCI_CMD); 788 789 /* Put the PCI bus into reset */ 790 val = readw(v3->base + V3_SYSTEM); 791 val &= ~V3_SYSTEM_M_RST_OUT; 792 writew(val, v3->base + V3_SYSTEM); 793 794 /* Retry until we're ready */ 795 val = readw(v3->base + V3_PCI_CFG); 796 val |= V3_PCI_CFG_M_RETRY_EN; 797 writew(val, v3->base + V3_PCI_CFG); 798 799 /* Set up the local bus protocol */ 800 val = readw(v3->base + V3_LB_CFG); 801 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */ 802 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */ 803 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */ 804 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */ 805 writew(val, v3->base + V3_LB_CFG); 806 807 /* Enable the PCI bus master */ 808 val = readw(v3->base + V3_PCI_CMD); 809 val |= PCI_COMMAND_MASTER; 810 writew(val, v3->base + V3_PCI_CMD); 811 812 /* Get the I/O and memory ranges from DT */ 813 resource_list_for_each_entry(win, &host->windows) { 814 ret = v3_pci_setup_resource(v3, host, win); 815 if (ret) { 816 dev_err(dev, "error setting up resources\n"); 817 return ret; 818 } 819 } 820 ret = v3_pci_parse_map_dma_ranges(v3, np); 821 if (ret) 822 return ret; 823 824 /* 825 * Disable PCI to host IO cycles, enable I/O buffers @3.3V, 826 * set AD_LOW0 to 1 if one of the LB_MAP registers choose 827 * to use this (should be unused). 828 */ 829 writel(0x00000000, v3->base + V3_PCI_IO_BASE); 830 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS | 831 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0; 832 /* 833 * DMA read and write from PCI bus commands types 834 */ 835 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT; 836 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT; 837 writew(val, v3->base + V3_PCI_CFG); 838 839 /* 840 * Set the V3 FIFO such that writes have higher priority than 841 * reads, and local bus write causes local bus read fifo flush 842 * on aperture 1. Same for PCI. 843 */ 844 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 | 845 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 | 846 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 | 847 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1, 848 v3->base + V3_FIFO_PRIORITY); 849 850 851 /* 852 * Clear any error interrupts, and enable parity and write error 853 * interrupts 854 */ 855 writeb(0, v3->base + V3_LB_ISTAT); 856 val = readw(v3->base + V3_LB_CFG); 857 val |= V3_LB_CFG_LB_LB_INT; 858 writew(val, v3->base + V3_LB_CFG); 859 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 860 v3->base + V3_LB_IMASK); 861 862 /* Special Integrator initialization */ 863 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { 864 ret = v3_integrator_init(v3); 865 if (ret) 866 return ret; 867 } 868 869 /* Post-init: enable PCI memory and invalidate (master already on) */ 870 val = readw(v3->base + V3_PCI_CMD); 871 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE; 872 writew(val, v3->base + V3_PCI_CMD); 873 874 /* Clear pending interrupts */ 875 writeb(0, v3->base + V3_LB_ISTAT); 876 /* Read or write errors and parity errors cause interrupts */ 877 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 878 v3->base + V3_LB_IMASK); 879 880 /* Take the PCI bus out of reset so devices can initialize */ 881 val = readw(v3->base + V3_SYSTEM); 882 val |= V3_SYSTEM_M_RST_OUT; 883 writew(val, v3->base + V3_SYSTEM); 884 885 /* 886 * Re-lock the system register. 887 */ 888 val = readw(v3->base + V3_SYSTEM); 889 val |= V3_SYSTEM_M_LOCK; 890 writew(val, v3->base + V3_SYSTEM); 891 892 return pci_host_probe(host); 893 } 894 895 static const struct of_device_id v3_pci_of_match[] = { 896 { 897 .compatible = "v3,v360epc-pci", 898 }, 899 {}, 900 }; 901 902 static struct platform_driver v3_pci_driver = { 903 .driver = { 904 .name = "pci-v3-semi", 905 .of_match_table = of_match_ptr(v3_pci_of_match), 906 .suppress_bind_attrs = true, 907 }, 908 .probe = v3_pci_probe, 909 }; 910 builtin_platform_driver(v3_pci_driver); 911