1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
4  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5  *
6  * Based on the code from arch/arm/mach-integrator/pci_v3.c
7  * Copyright (C) 1999 ARM Limited
8  * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
9  *
10  * Contributors to the old driver include:
11  * Russell King <linux@armlinux.org.uk>
12  * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
13  * Rob Herring <robh@kernel.org>
14  * Liviu Dudau <Liviu.Dudau@arm.com>
15  * Grant Likely <grant.likely@secretlab.ca>
16  * Arnd Bergmann <arnd@arndb.de>
17  * Bjorn Helgaas <bhelgaas@google.com>
18  */
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
31 #include <linux/irq.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/regmap.h>
34 #include <linux/clk.h>
35 
36 #include "../pci.h"
37 
38 #define V3_PCI_VENDOR			0x00000000
39 #define V3_PCI_DEVICE			0x00000002
40 #define V3_PCI_CMD			0x00000004
41 #define V3_PCI_STAT			0x00000006
42 #define V3_PCI_CC_REV			0x00000008
43 #define V3_PCI_HDR_CFG			0x0000000C
44 #define V3_PCI_IO_BASE			0x00000010
45 #define V3_PCI_BASE0			0x00000014
46 #define V3_PCI_BASE1			0x00000018
47 #define V3_PCI_SUB_VENDOR		0x0000002C
48 #define V3_PCI_SUB_ID			0x0000002E
49 #define V3_PCI_ROM			0x00000030
50 #define V3_PCI_BPARAM			0x0000003C
51 #define V3_PCI_MAP0			0x00000040
52 #define V3_PCI_MAP1			0x00000044
53 #define V3_PCI_INT_STAT			0x00000048
54 #define V3_PCI_INT_CFG			0x0000004C
55 #define V3_LB_BASE0			0x00000054
56 #define V3_LB_BASE1			0x00000058
57 #define V3_LB_MAP0			0x0000005E
58 #define V3_LB_MAP1			0x00000062
59 #define V3_LB_BASE2			0x00000064
60 #define V3_LB_MAP2			0x00000066
61 #define V3_LB_SIZE			0x00000068
62 #define V3_LB_IO_BASE			0x0000006E
63 #define V3_FIFO_CFG			0x00000070
64 #define V3_FIFO_PRIORITY		0x00000072
65 #define V3_FIFO_STAT			0x00000074
66 #define V3_LB_ISTAT			0x00000076
67 #define V3_LB_IMASK			0x00000077
68 #define V3_SYSTEM			0x00000078
69 #define V3_LB_CFG			0x0000007A
70 #define V3_PCI_CFG			0x0000007C
71 #define V3_DMA_PCI_ADR0			0x00000080
72 #define V3_DMA_PCI_ADR1			0x00000090
73 #define V3_DMA_LOCAL_ADR0		0x00000084
74 #define V3_DMA_LOCAL_ADR1		0x00000094
75 #define V3_DMA_LENGTH0			0x00000088
76 #define V3_DMA_LENGTH1			0x00000098
77 #define V3_DMA_CSR0			0x0000008B
78 #define V3_DMA_CSR1			0x0000009B
79 #define V3_DMA_CTLB_ADR0		0x0000008C
80 #define V3_DMA_CTLB_ADR1		0x0000009C
81 #define V3_DMA_DELAY			0x000000E0
82 #define V3_MAIL_DATA			0x000000C0
83 #define V3_PCI_MAIL_IEWR		0x000000D0
84 #define V3_PCI_MAIL_IERD		0x000000D2
85 #define V3_LB_MAIL_IEWR			0x000000D4
86 #define V3_LB_MAIL_IERD			0x000000D6
87 #define V3_MAIL_WR_STAT			0x000000D8
88 #define V3_MAIL_RD_STAT			0x000000DA
89 #define V3_QBA_MAP			0x000000DC
90 
91 /* PCI STATUS bits */
92 #define V3_PCI_STAT_PAR_ERR		BIT(15)
93 #define V3_PCI_STAT_SYS_ERR		BIT(14)
94 #define V3_PCI_STAT_M_ABORT_ERR		BIT(13)
95 #define V3_PCI_STAT_T_ABORT_ERR		BIT(12)
96 
97 /* LB ISTAT bits */
98 #define V3_LB_ISTAT_MAILBOX		BIT(7)
99 #define V3_LB_ISTAT_PCI_RD		BIT(6)
100 #define V3_LB_ISTAT_PCI_WR		BIT(5)
101 #define V3_LB_ISTAT_PCI_INT		BIT(4)
102 #define V3_LB_ISTAT_PCI_PERR		BIT(3)
103 #define V3_LB_ISTAT_I2O_QWR		BIT(2)
104 #define V3_LB_ISTAT_DMA1		BIT(1)
105 #define V3_LB_ISTAT_DMA0		BIT(0)
106 
107 /* PCI COMMAND bits */
108 #define V3_COMMAND_M_FBB_EN		BIT(9)
109 #define V3_COMMAND_M_SERR_EN		BIT(8)
110 #define V3_COMMAND_M_PAR_EN		BIT(6)
111 #define V3_COMMAND_M_MASTER_EN		BIT(2)
112 #define V3_COMMAND_M_MEM_EN		BIT(1)
113 #define V3_COMMAND_M_IO_EN		BIT(0)
114 
115 /* SYSTEM bits */
116 #define V3_SYSTEM_M_RST_OUT		BIT(15)
117 #define V3_SYSTEM_M_LOCK		BIT(14)
118 #define V3_SYSTEM_UNLOCK		0xa05f
119 
120 /* PCI CFG bits */
121 #define V3_PCI_CFG_M_I2O_EN		BIT(15)
122 #define V3_PCI_CFG_M_IO_REG_DIS		BIT(14)
123 #define V3_PCI_CFG_M_IO_DIS		BIT(13)
124 #define V3_PCI_CFG_M_EN3V		BIT(12)
125 #define V3_PCI_CFG_M_RETRY_EN		BIT(10)
126 #define V3_PCI_CFG_M_AD_LOW1		BIT(9)
127 #define V3_PCI_CFG_M_AD_LOW0		BIT(8)
128 /*
129  * This is the value applied to C/BE[3:1], with bit 0 always held 0
130  * during DMA access.
131  */
132 #define V3_PCI_CFG_M_RTYPE_SHIFT	5
133 #define V3_PCI_CFG_M_WTYPE_SHIFT	1
134 #define V3_PCI_CFG_TYPE_DEFAULT		0x3
135 
136 /* PCI BASE bits (PCI -> Local Bus) */
137 #define V3_PCI_BASE_M_ADR_BASE		0xFFF00000U
138 #define V3_PCI_BASE_M_ADR_BASEL		0x000FFF00U
139 #define V3_PCI_BASE_M_PREFETCH		BIT(3)
140 #define V3_PCI_BASE_M_TYPE		(3 << 1)
141 #define V3_PCI_BASE_M_IO		BIT(0)
142 
143 /* PCI MAP bits (PCI -> Local bus) */
144 #define V3_PCI_MAP_M_MAP_ADR		0xFFF00000U
145 #define V3_PCI_MAP_M_RD_POST_INH	BIT(15)
146 #define V3_PCI_MAP_M_ROM_SIZE		(3 << 10)
147 #define V3_PCI_MAP_M_SWAP		(3 << 8)
148 #define V3_PCI_MAP_M_ADR_SIZE		0x000000F0U
149 #define V3_PCI_MAP_M_REG_EN		BIT(1)
150 #define V3_PCI_MAP_M_ENABLE		BIT(0)
151 
152 /* LB_BASE0,1 bits (Local bus -> PCI) */
153 #define V3_LB_BASE_ADR_BASE		0xfff00000U
154 #define V3_LB_BASE_SWAP			(3 << 8)
155 #define V3_LB_BASE_ADR_SIZE		(15 << 4)
156 #define V3_LB_BASE_PREFETCH		BIT(3)
157 #define V3_LB_BASE_ENABLE		BIT(0)
158 
159 #define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
160 #define V3_LB_BASE_ADR_SIZE_2MB		(1 << 4)
161 #define V3_LB_BASE_ADR_SIZE_4MB		(2 << 4)
162 #define V3_LB_BASE_ADR_SIZE_8MB		(3 << 4)
163 #define V3_LB_BASE_ADR_SIZE_16MB	(4 << 4)
164 #define V3_LB_BASE_ADR_SIZE_32MB	(5 << 4)
165 #define V3_LB_BASE_ADR_SIZE_64MB	(6 << 4)
166 #define V3_LB_BASE_ADR_SIZE_128MB	(7 << 4)
167 #define V3_LB_BASE_ADR_SIZE_256MB	(8 << 4)
168 #define V3_LB_BASE_ADR_SIZE_512MB	(9 << 4)
169 #define V3_LB_BASE_ADR_SIZE_1GB		(10 << 4)
170 #define V3_LB_BASE_ADR_SIZE_2GB		(11 << 4)
171 
172 #define v3_addr_to_lb_base(a)	((a) & V3_LB_BASE_ADR_BASE)
173 
174 /* LB_MAP0,1 bits (Local bus -> PCI) */
175 #define V3_LB_MAP_MAP_ADR		0xfff0U
176 #define V3_LB_MAP_TYPE			(7 << 1)
177 #define V3_LB_MAP_AD_LOW_EN		BIT(0)
178 
179 #define V3_LB_MAP_TYPE_IACK		(0 << 1)
180 #define V3_LB_MAP_TYPE_IO		(1 << 1)
181 #define V3_LB_MAP_TYPE_MEM		(3 << 1)
182 #define V3_LB_MAP_TYPE_CONFIG		(5 << 1)
183 #define V3_LB_MAP_TYPE_MEM_MULTIPLE	(6 << 1)
184 
185 #define v3_addr_to_lb_map(a)	(((a) >> 16) & V3_LB_MAP_MAP_ADR)
186 
187 /* LB_BASE2 bits (Local bus -> PCI IO) */
188 #define V3_LB_BASE2_ADR_BASE		0xff00U
189 #define V3_LB_BASE2_SWAP_AUTO		(3 << 6)
190 #define V3_LB_BASE2_ENABLE		BIT(0)
191 
192 #define v3_addr_to_lb_base2(a)	(((a) >> 16) & V3_LB_BASE2_ADR_BASE)
193 
194 /* LB_MAP2 bits (Local bus -> PCI IO) */
195 #define V3_LB_MAP2_MAP_ADR		0xff00U
196 
197 #define v3_addr_to_lb_map2(a)	(((a) >> 16) & V3_LB_MAP2_MAP_ADR)
198 
199 /* FIFO priority bits */
200 #define V3_FIFO_PRIO_LOCAL		BIT(12)
201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB	BIT(10)
202 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1	BIT(11)
203 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY	(BIT(10)|BIT(11))
204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB	BIT(8)
205 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1	BIT(9)
206 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY	(BIT(8)|BIT(9))
207 #define V3_FIFO_PRIO_PCI		BIT(4)
208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB	BIT(2)
209 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1	BIT(3)
210 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY	(BIT(2)|BIT(3))
211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB	BIT(0)
212 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1	BIT(1)
213 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY	(BIT(0)|BIT(1))
214 
215 /* Local bus configuration bits */
216 #define V3_LB_CFG_LB_TO_64_CYCLES	0x0000
217 #define V3_LB_CFG_LB_TO_256_CYCLES	BIT(13)
218 #define V3_LB_CFG_LB_TO_512_CYCLES	BIT(14)
219 #define V3_LB_CFG_LB_TO_1024_CYCLES	(BIT(13)|BIT(14))
220 #define V3_LB_CFG_LB_RST		BIT(12)
221 #define V3_LB_CFG_LB_PPC_RDY		BIT(11)
222 #define V3_LB_CFG_LB_LB_INT		BIT(10)
223 #define V3_LB_CFG_LB_ERR_EN		BIT(9)
224 #define V3_LB_CFG_LB_RDY_EN		BIT(8)
225 #define V3_LB_CFG_LB_BE_IMODE		BIT(7)
226 #define V3_LB_CFG_LB_BE_OMODE		BIT(6)
227 #define V3_LB_CFG_LB_ENDIAN		BIT(5)
228 #define V3_LB_CFG_LB_PARK_EN		BIT(4)
229 #define V3_LB_CFG_LB_FBB_DIS		BIT(2)
230 
231 /* ARM Integrator-specific extended control registers */
232 #define INTEGRATOR_SC_PCI_OFFSET	0x18
233 #define INTEGRATOR_SC_PCI_ENABLE	BIT(0)
234 #define INTEGRATOR_SC_PCI_INTCLR	BIT(1)
235 #define INTEGRATOR_SC_LBFADDR_OFFSET	0x20
236 #define INTEGRATOR_SC_LBFCODE_OFFSET	0x24
237 
238 struct v3_pci {
239 	struct device *dev;
240 	void __iomem *base;
241 	void __iomem *config_base;
242 	struct pci_bus *bus;
243 	u32 config_mem;
244 	u32 io_mem;
245 	u32 non_pre_mem;
246 	u32 pre_mem;
247 	phys_addr_t io_bus_addr;
248 	phys_addr_t non_pre_bus_addr;
249 	phys_addr_t pre_bus_addr;
250 	struct regmap *map;
251 };
252 
253 /*
254  * The V3 PCI interface chip in Integrator provides several windows from
255  * local bus memory into the PCI memory areas. Unfortunately, there
256  * are not really enough windows for our usage, therefore we reuse
257  * one of the windows for access to PCI configuration space. On the
258  * Integrator/AP, the memory map is as follows:
259  *
260  * Local Bus Memory         Usage
261  *
262  * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
263  * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
264  * 60000000 - 60FFFFFF      PCI IO.  16M
265  * 61000000 - 61FFFFFF      PCI Configuration. 16M
266  *
267  * There are three V3 windows, each described by a pair of V3 registers.
268  * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
269  * Base0 and Base1 can be used for any type of PCI memory access.   Base2
270  * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
271  * uses this only for PCI IO space.
272  *
273  * Normally these spaces are mapped using the following base registers:
274  *
275  * Usage Local Bus Memory         Base/Map registers used
276  *
277  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
278  * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
279  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
280  * Cfg   61000000 - 61FFFFFF
281  *
282  * This means that I20 and PCI configuration space accesses will fail.
283  * When PCI configuration accesses are needed (via the uHAL PCI
284  * configuration space primitives) we must remap the spaces as follows:
285  *
286  * Usage Local Bus Memory         Base/Map registers used
287  *
288  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
289  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
290  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
291  * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
292  *
293  * To make this work, the code depends on overlapping windows working.
294  * The V3 chip translates an address by checking its range within
295  * each of the BASE/MAP pairs in turn (in ascending register number
296  * order).  It will use the first matching pair.   So, for example,
297  * if the same address is mapped by both LB_BASE0/LB_MAP0 and
298  * LB_BASE1/LB_MAP1, the V3 will use the translation from
299  * LB_BASE0/LB_MAP0.
300  *
301  * To allow PCI Configuration space access, the code enlarges the
302  * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
303  * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
304  * be remapped for use by configuration cycles.
305  *
306  * At the end of the PCI Configuration space accesses,
307  * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
308  * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
309  * reveal the now restored LB_BASE1/LB_MAP1 window.
310  *
311  * NOTE: We do not set up I2O mapping.  I suspect that this is only
312  * for an intelligent (target) device.  Using I2O disables most of
313  * the mappings into PCI memory.
314  */
315 static void __iomem *v3_map_bus(struct pci_bus *bus,
316 				unsigned int devfn, int offset)
317 {
318 	struct v3_pci *v3 = bus->sysdata;
319 	unsigned int address, mapaddress, busnr;
320 
321 	busnr = bus->number;
322 	if (busnr == 0) {
323 		int slot = PCI_SLOT(devfn);
324 
325 		/*
326 		 * local bus segment so need a type 0 config cycle
327 		 *
328 		 * build the PCI configuration "address" with one-hot in
329 		 * A31-A11
330 		 *
331 		 * mapaddress:
332 		 *  3:1 = config cycle (101)
333 		 *  0   = PCI A1 & A0 are 0 (0)
334 		 */
335 		address = PCI_FUNC(devfn) << 8;
336 		mapaddress = V3_LB_MAP_TYPE_CONFIG;
337 
338 		if (slot > 12)
339 			/*
340 			 * high order bits are handled by the MAP register
341 			 */
342 			mapaddress |= BIT(slot - 5);
343 		else
344 			/*
345 			 * low order bits handled directly in the address
346 			 */
347 			address |= BIT(slot + 11);
348 	} else {
349 		/*
350 		 * not the local bus segment so need a type 1 config cycle
351 		 *
352 		 * address:
353 		 *  23:16 = bus number
354 		 *  15:11 = slot number (7:3 of devfn)
355 		 *  10:8  = func number (2:0 of devfn)
356 		 *
357 		 * mapaddress:
358 		 *  3:1 = config cycle (101)
359 		 *  0   = PCI A1 & A0 from host bus (1)
360 		 */
361 		mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
362 		address = (busnr << 16) | (devfn << 8);
363 	}
364 
365 	/*
366 	 * Set up base0 to see all 512Mbytes of memory space (not
367 	 * prefetchable), this frees up base1 for re-use by
368 	 * configuration memory
369 	 */
370 	writel(v3_addr_to_lb_base(v3->non_pre_mem) |
371 	       V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
372 	       v3->base + V3_LB_BASE0);
373 
374 	/*
375 	 * Set up base1/map1 to point into configuration space.
376 	 * The config mem is always 16MB.
377 	 */
378 	writel(v3_addr_to_lb_base(v3->config_mem) |
379 	       V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
380 	       v3->base + V3_LB_BASE1);
381 	writew(mapaddress, v3->base + V3_LB_MAP1);
382 
383 	return v3->config_base + address + offset;
384 }
385 
386 static void v3_unmap_bus(struct v3_pci *v3)
387 {
388 	/*
389 	 * Reassign base1 for use by prefetchable PCI memory
390 	 */
391 	writel(v3_addr_to_lb_base(v3->pre_mem) |
392 	       V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
393 	       V3_LB_BASE_ENABLE,
394 	       v3->base + V3_LB_BASE1);
395 	writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
396 	       V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
397 	       v3->base + V3_LB_MAP1);
398 
399 	/*
400 	 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
401 	 */
402 	writel(v3_addr_to_lb_base(v3->non_pre_mem) |
403 	       V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
404 	       v3->base + V3_LB_BASE0);
405 }
406 
407 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
408 			      int config, int size, u32 *value)
409 {
410 	struct v3_pci *v3 = bus->sysdata;
411 	int ret;
412 
413 	dev_dbg(&bus->dev,
414 		"[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
415 		PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
416 	ret = pci_generic_config_read(bus, fn, config, size, value);
417 	v3_unmap_bus(v3);
418 	return ret;
419 }
420 
421 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
422 				    int config, int size, u32 value)
423 {
424 	struct v3_pci *v3 = bus->sysdata;
425 	int ret;
426 
427 	dev_dbg(&bus->dev,
428 		"[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
429 		PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
430 	ret = pci_generic_config_write(bus, fn, config, size, value);
431 	v3_unmap_bus(v3);
432 	return ret;
433 }
434 
435 static struct pci_ops v3_pci_ops = {
436 	.map_bus = v3_map_bus,
437 	.read = v3_pci_read_config,
438 	.write = v3_pci_write_config,
439 };
440 
441 static irqreturn_t v3_irq(int irq, void *data)
442 {
443 	struct v3_pci *v3 = data;
444 	struct device *dev = v3->dev;
445 	u32 status;
446 
447 	status = readw(v3->base + V3_PCI_STAT);
448 	if (status & V3_PCI_STAT_PAR_ERR)
449 		dev_err(dev, "parity error interrupt\n");
450 	if (status & V3_PCI_STAT_SYS_ERR)
451 		dev_err(dev, "system error interrupt\n");
452 	if (status & V3_PCI_STAT_M_ABORT_ERR)
453 		dev_err(dev, "master abort error interrupt\n");
454 	if (status & V3_PCI_STAT_T_ABORT_ERR)
455 		dev_err(dev, "target abort error interrupt\n");
456 	writew(status, v3->base + V3_PCI_STAT);
457 
458 	status = readb(v3->base + V3_LB_ISTAT);
459 	if (status & V3_LB_ISTAT_MAILBOX)
460 		dev_info(dev, "PCI mailbox interrupt\n");
461 	if (status & V3_LB_ISTAT_PCI_RD)
462 		dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
463 	if (status & V3_LB_ISTAT_PCI_WR)
464 		dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
465 	if (status &  V3_LB_ISTAT_PCI_INT)
466 		dev_info(dev, "PCI pin interrupt\n");
467 	if (status & V3_LB_ISTAT_PCI_PERR)
468 		dev_err(dev, "PCI parity error interrupt\n");
469 	if (status & V3_LB_ISTAT_I2O_QWR)
470 		dev_info(dev, "I2O inbound post queue interrupt\n");
471 	if (status & V3_LB_ISTAT_DMA1)
472 		dev_info(dev, "DMA channel 1 interrupt\n");
473 	if (status & V3_LB_ISTAT_DMA0)
474 		dev_info(dev, "DMA channel 0 interrupt\n");
475 	/* Clear all possible interrupts on the local bus */
476 	writeb(0, v3->base + V3_LB_ISTAT);
477 	if (v3->map)
478 		regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
479 			     INTEGRATOR_SC_PCI_ENABLE |
480 			     INTEGRATOR_SC_PCI_INTCLR);
481 
482 	return IRQ_HANDLED;
483 }
484 
485 static int v3_integrator_init(struct v3_pci *v3)
486 {
487 	unsigned int val;
488 
489 	v3->map =
490 		syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
491 	if (IS_ERR(v3->map)) {
492 		dev_err(v3->dev, "no syscon\n");
493 		return -ENODEV;
494 	}
495 
496 	regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
497 	/* Take the PCI bridge out of reset, clear IRQs */
498 	regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
499 		     INTEGRATOR_SC_PCI_ENABLE |
500 		     INTEGRATOR_SC_PCI_INTCLR);
501 
502 	if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
503 		/* If we were in reset we need to sleep a bit */
504 		msleep(230);
505 
506 		/* Set the physical base for the controller itself */
507 		writel(0x6200, v3->base + V3_LB_IO_BASE);
508 
509 		/* Wait for the mailbox to settle after reset */
510 		do {
511 			writeb(0xaa, v3->base + V3_MAIL_DATA);
512 			writeb(0x55, v3->base + V3_MAIL_DATA + 4);
513 		} while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
514 			 readb(v3->base + V3_MAIL_DATA) != 0x55);
515 	}
516 
517 	dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
518 
519 	return 0;
520 }
521 
522 static int v3_pci_setup_resource(struct v3_pci *v3,
523 				 resource_size_t io_base,
524 				 struct pci_host_bridge *host,
525 				 struct resource_entry *win)
526 {
527 	struct device *dev = v3->dev;
528 	struct resource *mem;
529 	struct resource *io;
530 	int ret;
531 
532 	switch (resource_type(win->res)) {
533 	case IORESOURCE_IO:
534 		io = win->res;
535 		io->name = "V3 PCI I/O";
536 		v3->io_mem = io_base;
537 		v3->io_bus_addr = io->start - win->offset;
538 		dev_dbg(dev, "I/O window %pR, bus addr %pap\n",
539 			io, &v3->io_bus_addr);
540 		ret = devm_pci_remap_iospace(dev, io, io_base);
541 		if (ret) {
542 			dev_warn(dev,
543 				 "error %d: failed to map resource %pR\n",
544 				 ret, io);
545 			return ret;
546 		}
547 		/* Setup window 2 - PCI I/O */
548 		writel(v3_addr_to_lb_base2(v3->io_mem) |
549 		       V3_LB_BASE2_ENABLE,
550 		       v3->base + V3_LB_BASE2);
551 		writew(v3_addr_to_lb_map2(v3->io_bus_addr),
552 		       v3->base + V3_LB_MAP2);
553 		break;
554 	case IORESOURCE_MEM:
555 		mem = win->res;
556 		if (mem->flags & IORESOURCE_PREFETCH) {
557 			mem->name = "V3 PCI PRE-MEM";
558 			v3->pre_mem = mem->start;
559 			v3->pre_bus_addr = mem->start - win->offset;
560 			dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
561 				mem, &v3->pre_bus_addr);
562 			if (resource_size(mem) != SZ_256M) {
563 				dev_err(dev, "prefetchable memory range is not 256MB\n");
564 				return -EINVAL;
565 			}
566 			if (v3->non_pre_mem &&
567 			    (mem->start != v3->non_pre_mem + SZ_256M)) {
568 				dev_err(dev,
569 					"prefetchable memory is not adjacent to non-prefetchable memory\n");
570 				return -EINVAL;
571 			}
572 			/* Setup window 1 - PCI prefetchable memory */
573 			writel(v3_addr_to_lb_base(v3->pre_mem) |
574 			       V3_LB_BASE_ADR_SIZE_256MB |
575 			       V3_LB_BASE_PREFETCH |
576 			       V3_LB_BASE_ENABLE,
577 			       v3->base + V3_LB_BASE1);
578 			writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
579 			       V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
580 			       v3->base + V3_LB_MAP1);
581 		} else {
582 			mem->name = "V3 PCI NON-PRE-MEM";
583 			v3->non_pre_mem = mem->start;
584 			v3->non_pre_bus_addr = mem->start - win->offset;
585 			dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
586 				mem, &v3->non_pre_bus_addr);
587 			if (resource_size(mem) != SZ_256M) {
588 				dev_err(dev,
589 					"non-prefetchable memory range is not 256MB\n");
590 				return -EINVAL;
591 			}
592 			/* Setup window 0 - PCI non-prefetchable memory */
593 			writel(v3_addr_to_lb_base(v3->non_pre_mem) |
594 			       V3_LB_BASE_ADR_SIZE_256MB |
595 			       V3_LB_BASE_ENABLE,
596 			       v3->base + V3_LB_BASE0);
597 			writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
598 			       V3_LB_MAP_TYPE_MEM,
599 			       v3->base + V3_LB_MAP0);
600 		}
601 		break;
602 	case IORESOURCE_BUS:
603 		dev_dbg(dev, "BUS %pR\n", win->res);
604 		host->busnr = win->res->start;
605 		break;
606 	default:
607 		dev_info(dev, "Unknown resource type %lu\n",
608 			 resource_type(win->res));
609 		break;
610 	}
611 
612 	return 0;
613 }
614 
615 static int v3_get_dma_range_config(struct v3_pci *v3,
616 				   struct of_pci_range *range,
617 				   u32 *pci_base, u32 *pci_map)
618 {
619 	struct device *dev = v3->dev;
620 	u64 cpu_end = range->cpu_addr + range->size - 1;
621 	u64 pci_end = range->pci_addr + range->size - 1;
622 	u32 val;
623 
624 	if (range->pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
625 		dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
626 		return -EINVAL;
627 	}
628 	val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE;
629 	*pci_base = val;
630 
631 	if (range->cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
632 		dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
633 		return -EINVAL;
634 	}
635 	val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
636 
637 	switch (range->size) {
638 	case SZ_1M:
639 		val |= V3_LB_BASE_ADR_SIZE_1MB;
640 		break;
641 	case SZ_2M:
642 		val |= V3_LB_BASE_ADR_SIZE_2MB;
643 		break;
644 	case SZ_4M:
645 		val |= V3_LB_BASE_ADR_SIZE_4MB;
646 		break;
647 	case SZ_8M:
648 		val |= V3_LB_BASE_ADR_SIZE_8MB;
649 		break;
650 	case SZ_16M:
651 		val |= V3_LB_BASE_ADR_SIZE_16MB;
652 		break;
653 	case SZ_32M:
654 		val |= V3_LB_BASE_ADR_SIZE_32MB;
655 		break;
656 	case SZ_64M:
657 		val |= V3_LB_BASE_ADR_SIZE_64MB;
658 		break;
659 	case SZ_128M:
660 		val |= V3_LB_BASE_ADR_SIZE_128MB;
661 		break;
662 	case SZ_256M:
663 		val |= V3_LB_BASE_ADR_SIZE_256MB;
664 		break;
665 	case SZ_512M:
666 		val |= V3_LB_BASE_ADR_SIZE_512MB;
667 		break;
668 	case SZ_1G:
669 		val |= V3_LB_BASE_ADR_SIZE_1GB;
670 		break;
671 	case SZ_2G:
672 		val |= V3_LB_BASE_ADR_SIZE_2GB;
673 		break;
674 	default:
675 		dev_err(v3->dev, "illegal dma memory chunk size\n");
676 		return -EINVAL;
677 		break;
678 	}
679 	val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
680 	*pci_map = val;
681 
682 	dev_dbg(dev,
683 		"DMA MEM CPU: 0x%016llx -> 0x%016llx => "
684 		"PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
685 		range->cpu_addr, cpu_end,
686 		range->pci_addr, pci_end,
687 		*pci_base, *pci_map);
688 
689 	return 0;
690 }
691 
692 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
693 				       struct device_node *np)
694 {
695 	struct of_pci_range range;
696 	struct of_pci_range_parser parser;
697 	struct device *dev = v3->dev;
698 	int i = 0;
699 
700 	if (of_pci_dma_range_parser_init(&parser, np)) {
701 		dev_err(dev, "missing dma-ranges property\n");
702 		return -EINVAL;
703 	}
704 
705 	/*
706 	 * Get the dma-ranges from the device tree
707 	 */
708 	for_each_of_pci_range(&parser, &range) {
709 		int ret;
710 		u32 pci_base, pci_map;
711 
712 		ret = v3_get_dma_range_config(v3, &range, &pci_base, &pci_map);
713 		if (ret)
714 			return ret;
715 
716 		if (i == 0) {
717 			writel(pci_base, v3->base + V3_PCI_BASE0);
718 			writel(pci_map, v3->base + V3_PCI_MAP0);
719 		} else if (i == 1) {
720 			writel(pci_base, v3->base + V3_PCI_BASE1);
721 			writel(pci_map, v3->base + V3_PCI_MAP1);
722 		} else {
723 			dev_err(dev, "too many ranges, only two supported\n");
724 			dev_err(dev, "range %d ignored\n", i);
725 		}
726 		i++;
727 	}
728 	return 0;
729 }
730 
731 static int v3_pci_probe(struct platform_device *pdev)
732 {
733 	struct device *dev = &pdev->dev;
734 	struct device_node *np = dev->of_node;
735 	resource_size_t io_base;
736 	struct resource *regs;
737 	struct resource_entry *win;
738 	struct v3_pci *v3;
739 	struct pci_host_bridge *host;
740 	struct clk *clk;
741 	u16 val;
742 	int irq;
743 	int ret;
744 	LIST_HEAD(res);
745 
746 	host = pci_alloc_host_bridge(sizeof(*v3));
747 	if (!host)
748 		return -ENOMEM;
749 
750 	host->dev.parent = dev;
751 	host->ops = &v3_pci_ops;
752 	host->busnr = 0;
753 	host->msi = NULL;
754 	host->map_irq = of_irq_parse_and_map_pci;
755 	host->swizzle_irq = pci_common_swizzle;
756 	v3 = pci_host_bridge_priv(host);
757 	host->sysdata = v3;
758 	v3->dev = dev;
759 
760 	/* Get and enable host clock */
761 	clk = devm_clk_get(dev, NULL);
762 	if (IS_ERR(clk)) {
763 		dev_err(dev, "clock not found\n");
764 		return PTR_ERR(clk);
765 	}
766 	ret = clk_prepare_enable(clk);
767 	if (ret) {
768 		dev_err(dev, "unable to enable clock\n");
769 		return ret;
770 	}
771 
772 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
773 	v3->base = devm_ioremap_resource(dev, regs);
774 	if (IS_ERR(v3->base))
775 		return PTR_ERR(v3->base);
776 	/*
777 	 * The hardware has a register with the physical base address
778 	 * of the V3 controller itself, verify that this is the same
779 	 * as the physical memory we've remapped it from.
780 	 */
781 	if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
782 		dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
783 			readl(v3->base + V3_LB_IO_BASE), regs);
784 
785 	/* Configuration space is 16MB directly mapped */
786 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
787 	if (resource_size(regs) != SZ_16M) {
788 		dev_err(dev, "config mem is not 16MB!\n");
789 		return -EINVAL;
790 	}
791 	v3->config_mem = regs->start;
792 	v3->config_base = devm_ioremap_resource(dev, regs);
793 	if (IS_ERR(v3->config_base))
794 		return PTR_ERR(v3->config_base);
795 
796 	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
797 						    &io_base);
798 	if (ret)
799 		return ret;
800 
801 	ret = devm_request_pci_bus_resources(dev, &res);
802 	if (ret)
803 		return ret;
804 
805 	/* Get and request error IRQ resource */
806 	irq = platform_get_irq(pdev, 0);
807 	if (irq <= 0) {
808 		dev_err(dev, "unable to obtain PCIv3 error IRQ\n");
809 		return -ENODEV;
810 	}
811 	ret = devm_request_irq(dev, irq, v3_irq, 0,
812 			"PCIv3 error", v3);
813 	if (ret < 0) {
814 		dev_err(dev,
815 			"unable to request PCIv3 error IRQ %d (%d)\n",
816 			irq, ret);
817 		return ret;
818 	}
819 
820 	/*
821 	 * Unlock V3 registers, but only if they were previously locked.
822 	 */
823 	if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
824 		writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
825 
826 	/* Disable all slave access while we set up the windows */
827 	val = readw(v3->base + V3_PCI_CMD);
828 	val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
829 	writew(val, v3->base + V3_PCI_CMD);
830 
831 	/* Put the PCI bus into reset */
832 	val = readw(v3->base + V3_SYSTEM);
833 	val &= ~V3_SYSTEM_M_RST_OUT;
834 	writew(val, v3->base + V3_SYSTEM);
835 
836 	/* Retry until we're ready */
837 	val = readw(v3->base + V3_PCI_CFG);
838 	val |= V3_PCI_CFG_M_RETRY_EN;
839 	writew(val, v3->base + V3_PCI_CFG);
840 
841 	/* Set up the local bus protocol */
842 	val = readw(v3->base + V3_LB_CFG);
843 	val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
844 	val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
845 	val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
846 	val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
847 	writew(val, v3->base + V3_LB_CFG);
848 
849 	/* Enable the PCI bus master */
850 	val = readw(v3->base + V3_PCI_CMD);
851 	val |= PCI_COMMAND_MASTER;
852 	writew(val, v3->base + V3_PCI_CMD);
853 
854 	/* Get the I/O and memory ranges from DT */
855 	resource_list_for_each_entry(win, &res) {
856 		ret = v3_pci_setup_resource(v3, io_base, host, win);
857 		if (ret) {
858 			dev_err(dev, "error setting up resources\n");
859 			return ret;
860 		}
861 	}
862 	ret = v3_pci_parse_map_dma_ranges(v3, np);
863 	if (ret)
864 		return ret;
865 
866 	/*
867 	 * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
868 	 * set AD_LOW0 to 1 if one of the LB_MAP registers choose
869 	 * to use this (should be unused).
870 	 */
871 	writel(0x00000000, v3->base + V3_PCI_IO_BASE);
872 	val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
873 		V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
874 	/*
875 	 * DMA read and write from PCI bus commands types
876 	 */
877 	val |=  V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
878 	val |=  V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
879 	writew(val, v3->base + V3_PCI_CFG);
880 
881 	/*
882 	 * Set the V3 FIFO such that writes have higher priority than
883 	 * reads, and local bus write causes local bus read fifo flush
884 	 * on aperture 1. Same for PCI.
885 	 */
886 	writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
887 	       V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
888 	       V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
889 	       V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
890 	       v3->base + V3_FIFO_PRIORITY);
891 
892 
893 	/*
894 	 * Clear any error interrupts, and enable parity and write error
895 	 * interrupts
896 	 */
897 	writeb(0, v3->base + V3_LB_ISTAT);
898 	val = readw(v3->base + V3_LB_CFG);
899 	val |= V3_LB_CFG_LB_LB_INT;
900 	writew(val, v3->base + V3_LB_CFG);
901 	writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
902 	       v3->base + V3_LB_IMASK);
903 
904 	/* Special Integrator initialization */
905 	if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
906 		ret = v3_integrator_init(v3);
907 		if (ret)
908 			return ret;
909 	}
910 
911 	/* Post-init: enable PCI memory and invalidate (master already on) */
912 	val = readw(v3->base + V3_PCI_CMD);
913 	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
914 	writew(val, v3->base + V3_PCI_CMD);
915 
916 	/* Clear pending interrupts */
917 	writeb(0, v3->base + V3_LB_ISTAT);
918 	/* Read or write errors and parity errors cause interrupts */
919 	writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
920 	       v3->base + V3_LB_IMASK);
921 
922 	/* Take the PCI bus out of reset so devices can initialize */
923 	val = readw(v3->base + V3_SYSTEM);
924 	val |= V3_SYSTEM_M_RST_OUT;
925 	writew(val, v3->base + V3_SYSTEM);
926 
927 	/*
928 	 * Re-lock the system register.
929 	 */
930 	val = readw(v3->base + V3_SYSTEM);
931 	val |= V3_SYSTEM_M_LOCK;
932 	writew(val, v3->base + V3_SYSTEM);
933 
934 	list_splice_init(&res, &host->windows);
935 	ret = pci_scan_root_bus_bridge(host);
936 	if (ret) {
937 		dev_err(dev, "failed to register host: %d\n", ret);
938 		return ret;
939 	}
940 	v3->bus = host->bus;
941 
942 	pci_bus_assign_resources(v3->bus);
943 	pci_bus_add_devices(v3->bus);
944 
945 	return 0;
946 }
947 
948 static const struct of_device_id v3_pci_of_match[] = {
949 	{
950 		.compatible = "v3,v360epc-pci",
951 	},
952 	{},
953 };
954 
955 static struct platform_driver v3_pci_driver = {
956 	.driver = {
957 		.name = "pci-v3-semi",
958 		.of_match_table = of_match_ptr(v3_pci_of_match),
959 		.suppress_bind_attrs = true,
960 	},
961 	.probe  = v3_pci_probe,
962 };
963 builtin_platform_driver(v3_pci_driver);
964