1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * Based on the code from arch/arm/mach-integrator/pci_v3.c 7 * Copyright (C) 1999 ARM Limited 8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd 9 * 10 * Contributors to the old driver include: 11 * Russell King <linux@armlinux.org.uk> 12 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite) 13 * Rob Herring <robh@kernel.org> 14 * Liviu Dudau <Liviu.Dudau@arm.com> 15 * Grant Likely <grant.likely@secretlab.ca> 16 * Arnd Bergmann <arnd@arndb.de> 17 * Bjorn Helgaas <bhelgaas@google.com> 18 */ 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_pci.h> 27 #include <linux/pci.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 #include <linux/bitops.h> 31 #include <linux/irq.h> 32 #include <linux/mfd/syscon.h> 33 #include <linux/regmap.h> 34 #include <linux/clk.h> 35 36 #include "../pci.h" 37 38 #define V3_PCI_VENDOR 0x00000000 39 #define V3_PCI_DEVICE 0x00000002 40 #define V3_PCI_CMD 0x00000004 41 #define V3_PCI_STAT 0x00000006 42 #define V3_PCI_CC_REV 0x00000008 43 #define V3_PCI_HDR_CFG 0x0000000C 44 #define V3_PCI_IO_BASE 0x00000010 45 #define V3_PCI_BASE0 0x00000014 46 #define V3_PCI_BASE1 0x00000018 47 #define V3_PCI_SUB_VENDOR 0x0000002C 48 #define V3_PCI_SUB_ID 0x0000002E 49 #define V3_PCI_ROM 0x00000030 50 #define V3_PCI_BPARAM 0x0000003C 51 #define V3_PCI_MAP0 0x00000040 52 #define V3_PCI_MAP1 0x00000044 53 #define V3_PCI_INT_STAT 0x00000048 54 #define V3_PCI_INT_CFG 0x0000004C 55 #define V3_LB_BASE0 0x00000054 56 #define V3_LB_BASE1 0x00000058 57 #define V3_LB_MAP0 0x0000005E 58 #define V3_LB_MAP1 0x00000062 59 #define V3_LB_BASE2 0x00000064 60 #define V3_LB_MAP2 0x00000066 61 #define V3_LB_SIZE 0x00000068 62 #define V3_LB_IO_BASE 0x0000006E 63 #define V3_FIFO_CFG 0x00000070 64 #define V3_FIFO_PRIORITY 0x00000072 65 #define V3_FIFO_STAT 0x00000074 66 #define V3_LB_ISTAT 0x00000076 67 #define V3_LB_IMASK 0x00000077 68 #define V3_SYSTEM 0x00000078 69 #define V3_LB_CFG 0x0000007A 70 #define V3_PCI_CFG 0x0000007C 71 #define V3_DMA_PCI_ADR0 0x00000080 72 #define V3_DMA_PCI_ADR1 0x00000090 73 #define V3_DMA_LOCAL_ADR0 0x00000084 74 #define V3_DMA_LOCAL_ADR1 0x00000094 75 #define V3_DMA_LENGTH0 0x00000088 76 #define V3_DMA_LENGTH1 0x00000098 77 #define V3_DMA_CSR0 0x0000008B 78 #define V3_DMA_CSR1 0x0000009B 79 #define V3_DMA_CTLB_ADR0 0x0000008C 80 #define V3_DMA_CTLB_ADR1 0x0000009C 81 #define V3_DMA_DELAY 0x000000E0 82 #define V3_MAIL_DATA 0x000000C0 83 #define V3_PCI_MAIL_IEWR 0x000000D0 84 #define V3_PCI_MAIL_IERD 0x000000D2 85 #define V3_LB_MAIL_IEWR 0x000000D4 86 #define V3_LB_MAIL_IERD 0x000000D6 87 #define V3_MAIL_WR_STAT 0x000000D8 88 #define V3_MAIL_RD_STAT 0x000000DA 89 #define V3_QBA_MAP 0x000000DC 90 91 /* PCI STATUS bits */ 92 #define V3_PCI_STAT_PAR_ERR BIT(15) 93 #define V3_PCI_STAT_SYS_ERR BIT(14) 94 #define V3_PCI_STAT_M_ABORT_ERR BIT(13) 95 #define V3_PCI_STAT_T_ABORT_ERR BIT(12) 96 97 /* LB ISTAT bits */ 98 #define V3_LB_ISTAT_MAILBOX BIT(7) 99 #define V3_LB_ISTAT_PCI_RD BIT(6) 100 #define V3_LB_ISTAT_PCI_WR BIT(5) 101 #define V3_LB_ISTAT_PCI_INT BIT(4) 102 #define V3_LB_ISTAT_PCI_PERR BIT(3) 103 #define V3_LB_ISTAT_I2O_QWR BIT(2) 104 #define V3_LB_ISTAT_DMA1 BIT(1) 105 #define V3_LB_ISTAT_DMA0 BIT(0) 106 107 /* PCI COMMAND bits */ 108 #define V3_COMMAND_M_FBB_EN BIT(9) 109 #define V3_COMMAND_M_SERR_EN BIT(8) 110 #define V3_COMMAND_M_PAR_EN BIT(6) 111 #define V3_COMMAND_M_MASTER_EN BIT(2) 112 #define V3_COMMAND_M_MEM_EN BIT(1) 113 #define V3_COMMAND_M_IO_EN BIT(0) 114 115 /* SYSTEM bits */ 116 #define V3_SYSTEM_M_RST_OUT BIT(15) 117 #define V3_SYSTEM_M_LOCK BIT(14) 118 #define V3_SYSTEM_UNLOCK 0xa05f 119 120 /* PCI CFG bits */ 121 #define V3_PCI_CFG_M_I2O_EN BIT(15) 122 #define V3_PCI_CFG_M_IO_REG_DIS BIT(14) 123 #define V3_PCI_CFG_M_IO_DIS BIT(13) 124 #define V3_PCI_CFG_M_EN3V BIT(12) 125 #define V3_PCI_CFG_M_RETRY_EN BIT(10) 126 #define V3_PCI_CFG_M_AD_LOW1 BIT(9) 127 #define V3_PCI_CFG_M_AD_LOW0 BIT(8) 128 /* 129 * This is the value applied to C/BE[3:1], with bit 0 always held 0 130 * during DMA access. 131 */ 132 #define V3_PCI_CFG_M_RTYPE_SHIFT 5 133 #define V3_PCI_CFG_M_WTYPE_SHIFT 1 134 #define V3_PCI_CFG_TYPE_DEFAULT 0x3 135 136 /* PCI BASE bits (PCI -> Local Bus) */ 137 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U 138 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U 139 #define V3_PCI_BASE_M_PREFETCH BIT(3) 140 #define V3_PCI_BASE_M_TYPE (3 << 1) 141 #define V3_PCI_BASE_M_IO BIT(0) 142 143 /* PCI MAP bits (PCI -> Local bus) */ 144 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U 145 #define V3_PCI_MAP_M_RD_POST_INH BIT(15) 146 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) 147 #define V3_PCI_MAP_M_SWAP (3 << 8) 148 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U 149 #define V3_PCI_MAP_M_REG_EN BIT(1) 150 #define V3_PCI_MAP_M_ENABLE BIT(0) 151 152 /* LB_BASE0,1 bits (Local bus -> PCI) */ 153 #define V3_LB_BASE_ADR_BASE 0xfff00000U 154 #define V3_LB_BASE_SWAP (3 << 8) 155 #define V3_LB_BASE_ADR_SIZE (15 << 4) 156 #define V3_LB_BASE_PREFETCH BIT(3) 157 #define V3_LB_BASE_ENABLE BIT(0) 158 159 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) 160 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) 161 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) 162 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) 163 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) 164 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) 165 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) 166 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) 167 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) 168 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) 169 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) 170 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) 171 172 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) 173 174 /* LB_MAP0,1 bits (Local bus -> PCI) */ 175 #define V3_LB_MAP_MAP_ADR 0xfff0U 176 #define V3_LB_MAP_TYPE (7 << 1) 177 #define V3_LB_MAP_AD_LOW_EN BIT(0) 178 179 #define V3_LB_MAP_TYPE_IACK (0 << 1) 180 #define V3_LB_MAP_TYPE_IO (1 << 1) 181 #define V3_LB_MAP_TYPE_MEM (3 << 1) 182 #define V3_LB_MAP_TYPE_CONFIG (5 << 1) 183 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) 184 185 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) 186 187 /* LB_BASE2 bits (Local bus -> PCI IO) */ 188 #define V3_LB_BASE2_ADR_BASE 0xff00U 189 #define V3_LB_BASE2_SWAP_AUTO (3 << 6) 190 #define V3_LB_BASE2_ENABLE BIT(0) 191 192 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) 193 194 /* LB_MAP2 bits (Local bus -> PCI IO) */ 195 #define V3_LB_MAP2_MAP_ADR 0xff00U 196 197 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) 198 199 /* FIFO priority bits */ 200 #define V3_FIFO_PRIO_LOCAL BIT(12) 201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10) 202 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11) 203 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11)) 204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8) 205 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9) 206 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9)) 207 #define V3_FIFO_PRIO_PCI BIT(4) 208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2) 209 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3) 210 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3)) 211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0) 212 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1) 213 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1)) 214 215 /* Local bus configuration bits */ 216 #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000 217 #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13) 218 #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14) 219 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14)) 220 #define V3_LB_CFG_LB_RST BIT(12) 221 #define V3_LB_CFG_LB_PPC_RDY BIT(11) 222 #define V3_LB_CFG_LB_LB_INT BIT(10) 223 #define V3_LB_CFG_LB_ERR_EN BIT(9) 224 #define V3_LB_CFG_LB_RDY_EN BIT(8) 225 #define V3_LB_CFG_LB_BE_IMODE BIT(7) 226 #define V3_LB_CFG_LB_BE_OMODE BIT(6) 227 #define V3_LB_CFG_LB_ENDIAN BIT(5) 228 #define V3_LB_CFG_LB_PARK_EN BIT(4) 229 #define V3_LB_CFG_LB_FBB_DIS BIT(2) 230 231 /* ARM Integrator-specific extended control registers */ 232 #define INTEGRATOR_SC_PCI_OFFSET 0x18 233 #define INTEGRATOR_SC_PCI_ENABLE BIT(0) 234 #define INTEGRATOR_SC_PCI_INTCLR BIT(1) 235 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20 236 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24 237 238 struct v3_pci { 239 struct device *dev; 240 void __iomem *base; 241 void __iomem *config_base; 242 struct pci_bus *bus; 243 u32 config_mem; 244 u32 non_pre_mem; 245 u32 pre_mem; 246 phys_addr_t non_pre_bus_addr; 247 phys_addr_t pre_bus_addr; 248 struct regmap *map; 249 }; 250 251 /* 252 * The V3 PCI interface chip in Integrator provides several windows from 253 * local bus memory into the PCI memory areas. Unfortunately, there 254 * are not really enough windows for our usage, therefore we reuse 255 * one of the windows for access to PCI configuration space. On the 256 * Integrator/AP, the memory map is as follows: 257 * 258 * Local Bus Memory Usage 259 * 260 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable 261 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable 262 * 60000000 - 60FFFFFF PCI IO. 16M 263 * 61000000 - 61FFFFFF PCI Configuration. 16M 264 * 265 * There are three V3 windows, each described by a pair of V3 registers. 266 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. 267 * Base0 and Base1 can be used for any type of PCI memory access. Base2 268 * can be used either for PCI I/O or for I20 accesses. By default, uHAL 269 * uses this only for PCI IO space. 270 * 271 * Normally these spaces are mapped using the following base registers: 272 * 273 * Usage Local Bus Memory Base/Map registers used 274 * 275 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 276 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 277 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 278 * Cfg 61000000 - 61FFFFFF 279 * 280 * This means that I20 and PCI configuration space accesses will fail. 281 * When PCI configuration accesses are needed (via the uHAL PCI 282 * configuration space primitives) we must remap the spaces as follows: 283 * 284 * Usage Local Bus Memory Base/Map registers used 285 * 286 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 287 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 288 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 289 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 290 * 291 * To make this work, the code depends on overlapping windows working. 292 * The V3 chip translates an address by checking its range within 293 * each of the BASE/MAP pairs in turn (in ascending register number 294 * order). It will use the first matching pair. So, for example, 295 * if the same address is mapped by both LB_BASE0/LB_MAP0 and 296 * LB_BASE1/LB_MAP1, the V3 will use the translation from 297 * LB_BASE0/LB_MAP0. 298 * 299 * To allow PCI Configuration space access, the code enlarges the 300 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes 301 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can 302 * be remapped for use by configuration cycles. 303 * 304 * At the end of the PCI Configuration space accesses, 305 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window 306 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to 307 * reveal the now restored LB_BASE1/LB_MAP1 window. 308 * 309 * NOTE: We do not set up I2O mapping. I suspect that this is only 310 * for an intelligent (target) device. Using I2O disables most of 311 * the mappings into PCI memory. 312 */ 313 static void __iomem *v3_map_bus(struct pci_bus *bus, 314 unsigned int devfn, int offset) 315 { 316 struct v3_pci *v3 = bus->sysdata; 317 unsigned int address, mapaddress, busnr; 318 319 busnr = bus->number; 320 if (busnr == 0) { 321 int slot = PCI_SLOT(devfn); 322 323 /* 324 * local bus segment so need a type 0 config cycle 325 * 326 * build the PCI configuration "address" with one-hot in 327 * A31-A11 328 * 329 * mapaddress: 330 * 3:1 = config cycle (101) 331 * 0 = PCI A1 & A0 are 0 (0) 332 */ 333 address = PCI_FUNC(devfn) << 8; 334 mapaddress = V3_LB_MAP_TYPE_CONFIG; 335 336 if (slot > 12) 337 /* 338 * high order bits are handled by the MAP register 339 */ 340 mapaddress |= BIT(slot - 5); 341 else 342 /* 343 * low order bits handled directly in the address 344 */ 345 address |= BIT(slot + 11); 346 } else { 347 /* 348 * not the local bus segment so need a type 1 config cycle 349 * 350 * address: 351 * 23:16 = bus number 352 * 15:11 = slot number (7:3 of devfn) 353 * 10:8 = func number (2:0 of devfn) 354 * 355 * mapaddress: 356 * 3:1 = config cycle (101) 357 * 0 = PCI A1 & A0 from host bus (1) 358 */ 359 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; 360 address = (busnr << 16) | (devfn << 8); 361 } 362 363 /* 364 * Set up base0 to see all 512Mbytes of memory space (not 365 * prefetchable), this frees up base1 for re-use by 366 * configuration memory 367 */ 368 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 369 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE, 370 v3->base + V3_LB_BASE0); 371 372 /* 373 * Set up base1/map1 to point into configuration space. 374 * The config mem is always 16MB. 375 */ 376 writel(v3_addr_to_lb_base(v3->config_mem) | 377 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE, 378 v3->base + V3_LB_BASE1); 379 writew(mapaddress, v3->base + V3_LB_MAP1); 380 381 return v3->config_base + address + offset; 382 } 383 384 static void v3_unmap_bus(struct v3_pci *v3) 385 { 386 /* 387 * Reassign base1 for use by prefetchable PCI memory 388 */ 389 writel(v3_addr_to_lb_base(v3->pre_mem) | 390 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 391 V3_LB_BASE_ENABLE, 392 v3->base + V3_LB_BASE1); 393 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 394 V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 395 v3->base + V3_LB_MAP1); 396 397 /* 398 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 399 */ 400 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 401 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE, 402 v3->base + V3_LB_BASE0); 403 } 404 405 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn, 406 int config, int size, u32 *value) 407 { 408 struct v3_pci *v3 = bus->sysdata; 409 int ret; 410 411 dev_dbg(&bus->dev, 412 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 413 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); 414 ret = pci_generic_config_read(bus, fn, config, size, value); 415 v3_unmap_bus(v3); 416 return ret; 417 } 418 419 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn, 420 int config, int size, u32 value) 421 { 422 struct v3_pci *v3 = bus->sysdata; 423 int ret; 424 425 dev_dbg(&bus->dev, 426 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 427 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); 428 ret = pci_generic_config_write(bus, fn, config, size, value); 429 v3_unmap_bus(v3); 430 return ret; 431 } 432 433 static struct pci_ops v3_pci_ops = { 434 .map_bus = v3_map_bus, 435 .read = v3_pci_read_config, 436 .write = v3_pci_write_config, 437 }; 438 439 static irqreturn_t v3_irq(int irq, void *data) 440 { 441 struct v3_pci *v3 = data; 442 struct device *dev = v3->dev; 443 u32 status; 444 445 status = readw(v3->base + V3_PCI_STAT); 446 if (status & V3_PCI_STAT_PAR_ERR) 447 dev_err(dev, "parity error interrupt\n"); 448 if (status & V3_PCI_STAT_SYS_ERR) 449 dev_err(dev, "system error interrupt\n"); 450 if (status & V3_PCI_STAT_M_ABORT_ERR) 451 dev_err(dev, "master abort error interrupt\n"); 452 if (status & V3_PCI_STAT_T_ABORT_ERR) 453 dev_err(dev, "target abort error interrupt\n"); 454 writew(status, v3->base + V3_PCI_STAT); 455 456 status = readb(v3->base + V3_LB_ISTAT); 457 if (status & V3_LB_ISTAT_MAILBOX) 458 dev_info(dev, "PCI mailbox interrupt\n"); 459 if (status & V3_LB_ISTAT_PCI_RD) 460 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n"); 461 if (status & V3_LB_ISTAT_PCI_WR) 462 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n"); 463 if (status & V3_LB_ISTAT_PCI_INT) 464 dev_info(dev, "PCI pin interrupt\n"); 465 if (status & V3_LB_ISTAT_PCI_PERR) 466 dev_err(dev, "PCI parity error interrupt\n"); 467 if (status & V3_LB_ISTAT_I2O_QWR) 468 dev_info(dev, "I2O inbound post queue interrupt\n"); 469 if (status & V3_LB_ISTAT_DMA1) 470 dev_info(dev, "DMA channel 1 interrupt\n"); 471 if (status & V3_LB_ISTAT_DMA0) 472 dev_info(dev, "DMA channel 0 interrupt\n"); 473 /* Clear all possible interrupts on the local bus */ 474 writeb(0, v3->base + V3_LB_ISTAT); 475 if (v3->map) 476 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 477 INTEGRATOR_SC_PCI_ENABLE | 478 INTEGRATOR_SC_PCI_INTCLR); 479 480 return IRQ_HANDLED; 481 } 482 483 static int v3_integrator_init(struct v3_pci *v3) 484 { 485 unsigned int val; 486 487 v3->map = 488 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon"); 489 if (IS_ERR(v3->map)) { 490 dev_err(v3->dev, "no syscon\n"); 491 return -ENODEV; 492 } 493 494 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); 495 /* Take the PCI bridge out of reset, clear IRQs */ 496 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 497 INTEGRATOR_SC_PCI_ENABLE | 498 INTEGRATOR_SC_PCI_INTCLR); 499 500 if (!(val & INTEGRATOR_SC_PCI_ENABLE)) { 501 /* If we were in reset we need to sleep a bit */ 502 msleep(230); 503 504 /* Set the physical base for the controller itself */ 505 writel(0x6200, v3->base + V3_LB_IO_BASE); 506 507 /* Wait for the mailbox to settle after reset */ 508 do { 509 writeb(0xaa, v3->base + V3_MAIL_DATA); 510 writeb(0x55, v3->base + V3_MAIL_DATA + 4); 511 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && 512 readb(v3->base + V3_MAIL_DATA) != 0x55); 513 } 514 515 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); 516 517 return 0; 518 } 519 520 static int v3_pci_setup_resource(struct v3_pci *v3, 521 struct pci_host_bridge *host, 522 struct resource_entry *win) 523 { 524 struct device *dev = v3->dev; 525 struct resource *mem; 526 struct resource *io; 527 528 switch (resource_type(win->res)) { 529 case IORESOURCE_IO: 530 io = win->res; 531 532 /* Setup window 2 - PCI I/O */ 533 writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) | 534 V3_LB_BASE2_ENABLE, 535 v3->base + V3_LB_BASE2); 536 writew(v3_addr_to_lb_map2(io->start - win->offset), 537 v3->base + V3_LB_MAP2); 538 break; 539 case IORESOURCE_MEM: 540 mem = win->res; 541 if (mem->flags & IORESOURCE_PREFETCH) { 542 mem->name = "V3 PCI PRE-MEM"; 543 v3->pre_mem = mem->start; 544 v3->pre_bus_addr = mem->start - win->offset; 545 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n", 546 mem, &v3->pre_bus_addr); 547 if (resource_size(mem) != SZ_256M) { 548 dev_err(dev, "prefetchable memory range is not 256MB\n"); 549 return -EINVAL; 550 } 551 if (v3->non_pre_mem && 552 (mem->start != v3->non_pre_mem + SZ_256M)) { 553 dev_err(dev, 554 "prefetchable memory is not adjacent to non-prefetchable memory\n"); 555 return -EINVAL; 556 } 557 /* Setup window 1 - PCI prefetchable memory */ 558 writel(v3_addr_to_lb_base(v3->pre_mem) | 559 V3_LB_BASE_ADR_SIZE_256MB | 560 V3_LB_BASE_PREFETCH | 561 V3_LB_BASE_ENABLE, 562 v3->base + V3_LB_BASE1); 563 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 564 V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 565 v3->base + V3_LB_MAP1); 566 } else { 567 mem->name = "V3 PCI NON-PRE-MEM"; 568 v3->non_pre_mem = mem->start; 569 v3->non_pre_bus_addr = mem->start - win->offset; 570 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n", 571 mem, &v3->non_pre_bus_addr); 572 if (resource_size(mem) != SZ_256M) { 573 dev_err(dev, 574 "non-prefetchable memory range is not 256MB\n"); 575 return -EINVAL; 576 } 577 /* Setup window 0 - PCI non-prefetchable memory */ 578 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 579 V3_LB_BASE_ADR_SIZE_256MB | 580 V3_LB_BASE_ENABLE, 581 v3->base + V3_LB_BASE0); 582 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | 583 V3_LB_MAP_TYPE_MEM, 584 v3->base + V3_LB_MAP0); 585 } 586 break; 587 case IORESOURCE_BUS: 588 dev_dbg(dev, "BUS %pR\n", win->res); 589 host->busnr = win->res->start; 590 break; 591 default: 592 dev_info(dev, "Unknown resource type %lu\n", 593 resource_type(win->res)); 594 break; 595 } 596 597 return 0; 598 } 599 600 static int v3_get_dma_range_config(struct v3_pci *v3, 601 struct resource_entry *entry, 602 u32 *pci_base, u32 *pci_map) 603 { 604 struct device *dev = v3->dev; 605 u64 cpu_addr = entry->res->start; 606 u64 cpu_end = entry->res->end; 607 u64 pci_end = cpu_end - entry->offset; 608 u64 pci_addr = entry->res->start - entry->offset; 609 u32 val; 610 611 if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { 612 dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n"); 613 return -EINVAL; 614 } 615 val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE; 616 *pci_base = val; 617 618 if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { 619 dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n"); 620 return -EINVAL; 621 } 622 val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR; 623 624 switch (resource_size(entry->res)) { 625 case SZ_1M: 626 val |= V3_LB_BASE_ADR_SIZE_1MB; 627 break; 628 case SZ_2M: 629 val |= V3_LB_BASE_ADR_SIZE_2MB; 630 break; 631 case SZ_4M: 632 val |= V3_LB_BASE_ADR_SIZE_4MB; 633 break; 634 case SZ_8M: 635 val |= V3_LB_BASE_ADR_SIZE_8MB; 636 break; 637 case SZ_16M: 638 val |= V3_LB_BASE_ADR_SIZE_16MB; 639 break; 640 case SZ_32M: 641 val |= V3_LB_BASE_ADR_SIZE_32MB; 642 break; 643 case SZ_64M: 644 val |= V3_LB_BASE_ADR_SIZE_64MB; 645 break; 646 case SZ_128M: 647 val |= V3_LB_BASE_ADR_SIZE_128MB; 648 break; 649 case SZ_256M: 650 val |= V3_LB_BASE_ADR_SIZE_256MB; 651 break; 652 case SZ_512M: 653 val |= V3_LB_BASE_ADR_SIZE_512MB; 654 break; 655 case SZ_1G: 656 val |= V3_LB_BASE_ADR_SIZE_1GB; 657 break; 658 case SZ_2G: 659 val |= V3_LB_BASE_ADR_SIZE_2GB; 660 break; 661 default: 662 dev_err(v3->dev, "illegal dma memory chunk size\n"); 663 return -EINVAL; 664 break; 665 } 666 val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE; 667 *pci_map = val; 668 669 dev_dbg(dev, 670 "DMA MEM CPU: 0x%016llx -> 0x%016llx => " 671 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", 672 cpu_addr, cpu_end, 673 pci_addr, pci_end, 674 *pci_base, *pci_map); 675 676 return 0; 677 } 678 679 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, 680 struct device_node *np) 681 { 682 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3); 683 struct device *dev = v3->dev; 684 struct resource_entry *entry; 685 int i = 0; 686 687 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 688 int ret; 689 u32 pci_base, pci_map; 690 691 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map); 692 if (ret) 693 return ret; 694 695 if (i == 0) { 696 writel(pci_base, v3->base + V3_PCI_BASE0); 697 writel(pci_map, v3->base + V3_PCI_MAP0); 698 } else if (i == 1) { 699 writel(pci_base, v3->base + V3_PCI_BASE1); 700 writel(pci_map, v3->base + V3_PCI_MAP1); 701 } else { 702 dev_err(dev, "too many ranges, only two supported\n"); 703 dev_err(dev, "range %d ignored\n", i); 704 } 705 i++; 706 } 707 return 0; 708 } 709 710 static int v3_pci_probe(struct platform_device *pdev) 711 { 712 struct device *dev = &pdev->dev; 713 struct device_node *np = dev->of_node; 714 struct resource *regs; 715 struct resource_entry *win; 716 struct v3_pci *v3; 717 struct pci_host_bridge *host; 718 struct clk *clk; 719 u16 val; 720 int irq; 721 int ret; 722 723 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3)); 724 if (!host) 725 return -ENOMEM; 726 727 host->dev.parent = dev; 728 host->ops = &v3_pci_ops; 729 host->busnr = 0; 730 host->msi = NULL; 731 host->map_irq = of_irq_parse_and_map_pci; 732 host->swizzle_irq = pci_common_swizzle; 733 v3 = pci_host_bridge_priv(host); 734 host->sysdata = v3; 735 v3->dev = dev; 736 737 /* Get and enable host clock */ 738 clk = devm_clk_get(dev, NULL); 739 if (IS_ERR(clk)) { 740 dev_err(dev, "clock not found\n"); 741 return PTR_ERR(clk); 742 } 743 ret = clk_prepare_enable(clk); 744 if (ret) { 745 dev_err(dev, "unable to enable clock\n"); 746 return ret; 747 } 748 749 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 750 v3->base = devm_ioremap_resource(dev, regs); 751 if (IS_ERR(v3->base)) 752 return PTR_ERR(v3->base); 753 /* 754 * The hardware has a register with the physical base address 755 * of the V3 controller itself, verify that this is the same 756 * as the physical memory we've remapped it from. 757 */ 758 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) 759 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n", 760 readl(v3->base + V3_LB_IO_BASE), regs); 761 762 /* Configuration space is 16MB directly mapped */ 763 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 764 if (resource_size(regs) != SZ_16M) { 765 dev_err(dev, "config mem is not 16MB!\n"); 766 return -EINVAL; 767 } 768 v3->config_mem = regs->start; 769 v3->config_base = devm_ioremap_resource(dev, regs); 770 if (IS_ERR(v3->config_base)) 771 return PTR_ERR(v3->config_base); 772 773 ret = pci_parse_request_of_pci_ranges(dev, &host->windows, 774 &host->dma_ranges, NULL); 775 if (ret) 776 return ret; 777 778 /* Get and request error IRQ resource */ 779 irq = platform_get_irq(pdev, 0); 780 if (irq < 0) { 781 dev_err(dev, "unable to obtain PCIv3 error IRQ\n"); 782 return irq; 783 } 784 ret = devm_request_irq(dev, irq, v3_irq, 0, 785 "PCIv3 error", v3); 786 if (ret < 0) { 787 dev_err(dev, 788 "unable to request PCIv3 error IRQ %d (%d)\n", 789 irq, ret); 790 return ret; 791 } 792 793 /* 794 * Unlock V3 registers, but only if they were previously locked. 795 */ 796 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) 797 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); 798 799 /* Disable all slave access while we set up the windows */ 800 val = readw(v3->base + V3_PCI_CMD); 801 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 802 writew(val, v3->base + V3_PCI_CMD); 803 804 /* Put the PCI bus into reset */ 805 val = readw(v3->base + V3_SYSTEM); 806 val &= ~V3_SYSTEM_M_RST_OUT; 807 writew(val, v3->base + V3_SYSTEM); 808 809 /* Retry until we're ready */ 810 val = readw(v3->base + V3_PCI_CFG); 811 val |= V3_PCI_CFG_M_RETRY_EN; 812 writew(val, v3->base + V3_PCI_CFG); 813 814 /* Set up the local bus protocol */ 815 val = readw(v3->base + V3_LB_CFG); 816 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */ 817 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */ 818 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */ 819 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */ 820 writew(val, v3->base + V3_LB_CFG); 821 822 /* Enable the PCI bus master */ 823 val = readw(v3->base + V3_PCI_CMD); 824 val |= PCI_COMMAND_MASTER; 825 writew(val, v3->base + V3_PCI_CMD); 826 827 /* Get the I/O and memory ranges from DT */ 828 resource_list_for_each_entry(win, &host->windows) { 829 ret = v3_pci_setup_resource(v3, host, win); 830 if (ret) { 831 dev_err(dev, "error setting up resources\n"); 832 return ret; 833 } 834 } 835 ret = v3_pci_parse_map_dma_ranges(v3, np); 836 if (ret) 837 return ret; 838 839 /* 840 * Disable PCI to host IO cycles, enable I/O buffers @3.3V, 841 * set AD_LOW0 to 1 if one of the LB_MAP registers choose 842 * to use this (should be unused). 843 */ 844 writel(0x00000000, v3->base + V3_PCI_IO_BASE); 845 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS | 846 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0; 847 /* 848 * DMA read and write from PCI bus commands types 849 */ 850 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT; 851 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT; 852 writew(val, v3->base + V3_PCI_CFG); 853 854 /* 855 * Set the V3 FIFO such that writes have higher priority than 856 * reads, and local bus write causes local bus read fifo flush 857 * on aperture 1. Same for PCI. 858 */ 859 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 | 860 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 | 861 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 | 862 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1, 863 v3->base + V3_FIFO_PRIORITY); 864 865 866 /* 867 * Clear any error interrupts, and enable parity and write error 868 * interrupts 869 */ 870 writeb(0, v3->base + V3_LB_ISTAT); 871 val = readw(v3->base + V3_LB_CFG); 872 val |= V3_LB_CFG_LB_LB_INT; 873 writew(val, v3->base + V3_LB_CFG); 874 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 875 v3->base + V3_LB_IMASK); 876 877 /* Special Integrator initialization */ 878 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { 879 ret = v3_integrator_init(v3); 880 if (ret) 881 return ret; 882 } 883 884 /* Post-init: enable PCI memory and invalidate (master already on) */ 885 val = readw(v3->base + V3_PCI_CMD); 886 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE; 887 writew(val, v3->base + V3_PCI_CMD); 888 889 /* Clear pending interrupts */ 890 writeb(0, v3->base + V3_LB_ISTAT); 891 /* Read or write errors and parity errors cause interrupts */ 892 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 893 v3->base + V3_LB_IMASK); 894 895 /* Take the PCI bus out of reset so devices can initialize */ 896 val = readw(v3->base + V3_SYSTEM); 897 val |= V3_SYSTEM_M_RST_OUT; 898 writew(val, v3->base + V3_SYSTEM); 899 900 /* 901 * Re-lock the system register. 902 */ 903 val = readw(v3->base + V3_SYSTEM); 904 val |= V3_SYSTEM_M_LOCK; 905 writew(val, v3->base + V3_SYSTEM); 906 907 ret = pci_scan_root_bus_bridge(host); 908 if (ret) { 909 dev_err(dev, "failed to register host: %d\n", ret); 910 return ret; 911 } 912 v3->bus = host->bus; 913 914 pci_bus_assign_resources(v3->bus); 915 pci_bus_add_devices(v3->bus); 916 917 return 0; 918 } 919 920 static const struct of_device_id v3_pci_of_match[] = { 921 { 922 .compatible = "v3,v360epc-pci", 923 }, 924 {}, 925 }; 926 927 static struct platform_driver v3_pci_driver = { 928 .driver = { 929 .name = "pci-v3-semi", 930 .of_match_table = of_match_ptr(v3_pci_of_match), 931 .suppress_bind_attrs = true, 932 }, 933 .probe = v3_pci_probe, 934 }; 935 builtin_platform_driver(v3_pci_driver); 936