1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-rcar-gen2: internal PCI bus support 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * Author: Valentine Barshak <valentine.barshak@cogentembedded.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/pci.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/sizes.h> 22 #include <linux/slab.h> 23 24 #include "../pci.h" 25 26 /* AHB-PCI Bridge PCI communication registers */ 27 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800 28 29 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00) 30 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04) 31 #define RCAR_PCIAHB_PREFETCH0 0x0 32 #define RCAR_PCIAHB_PREFETCH4 0x1 33 #define RCAR_PCIAHB_PREFETCH8 0x2 34 #define RCAR_PCIAHB_PREFETCH16 0x3 35 36 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10) 37 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14) 38 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1) 39 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1) 40 #define RCAR_AHBPCI_WIN1_HOST (1 << 30) 41 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31) 42 43 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20) 44 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24) 45 #define RCAR_PCI_INT_SIGTABORT (1 << 0) 46 #define RCAR_PCI_INT_SIGRETABORT (1 << 1) 47 #define RCAR_PCI_INT_REMABORT (1 << 2) 48 #define RCAR_PCI_INT_PERR (1 << 3) 49 #define RCAR_PCI_INT_SIGSERR (1 << 4) 50 #define RCAR_PCI_INT_RESERR (1 << 5) 51 #define RCAR_PCI_INT_WIN1ERR (1 << 12) 52 #define RCAR_PCI_INT_WIN2ERR (1 << 13) 53 #define RCAR_PCI_INT_A (1 << 16) 54 #define RCAR_PCI_INT_B (1 << 17) 55 #define RCAR_PCI_INT_PME (1 << 19) 56 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \ 57 RCAR_PCI_INT_SIGRETABORT | \ 58 RCAR_PCI_INT_REMABORT | \ 59 RCAR_PCI_INT_PERR | \ 60 RCAR_PCI_INT_SIGSERR | \ 61 RCAR_PCI_INT_RESERR | \ 62 RCAR_PCI_INT_WIN1ERR | \ 63 RCAR_PCI_INT_WIN2ERR) 64 65 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30) 66 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0) 67 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1) 68 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2) 69 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7) 70 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17) 71 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \ 72 RCAR_AHB_BUS_MMODE_BYTE_BURST | \ 73 RCAR_AHB_BUS_MMODE_WR_INCR | \ 74 RCAR_AHB_BUS_MMODE_HBUS_REQ | \ 75 RCAR_AHB_BUS_SMODE_READYCTR) 76 77 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34) 78 #define RCAR_USBCTR_USBH_RST (1 << 0) 79 #define RCAR_USBCTR_PCICLK_MASK (1 << 1) 80 #define RCAR_USBCTR_PLL_RST (1 << 2) 81 #define RCAR_USBCTR_DIRPD (1 << 8) 82 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9) 83 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10) 84 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10) 85 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10) 86 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10) 87 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10) 88 89 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40) 90 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0) 91 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1) 92 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12) 93 94 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48) 95 96 struct rcar_pci_priv { 97 struct device *dev; 98 void __iomem *reg; 99 struct resource mem_res; 100 struct resource *cfg_res; 101 unsigned busnr; 102 int irq; 103 unsigned long window_size; 104 unsigned long window_addr; 105 unsigned long window_pci; 106 }; 107 108 /* PCI configuration space operations */ 109 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, 110 int where) 111 { 112 struct pci_sys_data *sys = bus->sysdata; 113 struct rcar_pci_priv *priv = sys->private_data; 114 int slot, val; 115 116 if (sys->busnr != bus->number || PCI_FUNC(devfn)) 117 return NULL; 118 119 /* Only one EHCI/OHCI device built-in */ 120 slot = PCI_SLOT(devfn); 121 if (slot > 2) 122 return NULL; 123 124 /* bridge logic only has registers to 0x40 */ 125 if (slot == 0x0 && where >= 0x40) 126 return NULL; 127 128 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG : 129 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG; 130 131 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); 132 return priv->reg + (slot >> 1) * 0x100 + where; 133 } 134 135 /* PCI interrupt mapping */ 136 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 137 { 138 struct pci_sys_data *sys = dev->bus->sysdata; 139 struct rcar_pci_priv *priv = sys->private_data; 140 int irq; 141 142 irq = of_irq_parse_and_map_pci(dev, slot, pin); 143 if (!irq) 144 irq = priv->irq; 145 146 return irq; 147 } 148 149 #ifdef CONFIG_PCI_DEBUG 150 /* if debug enabled, then attach an error handler irq to the bridge */ 151 152 static irqreturn_t rcar_pci_err_irq(int irq, void *pw) 153 { 154 struct rcar_pci_priv *priv = pw; 155 struct device *dev = priv->dev; 156 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); 157 158 if (status & RCAR_PCI_INT_ALLERRORS) { 159 dev_err(dev, "error irq: status %08x\n", status); 160 161 /* clear the error(s) */ 162 iowrite32(status & RCAR_PCI_INT_ALLERRORS, 163 priv->reg + RCAR_PCI_INT_STATUS_REG); 164 return IRQ_HANDLED; 165 } 166 167 return IRQ_NONE; 168 } 169 170 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) 171 { 172 struct device *dev = priv->dev; 173 int ret; 174 u32 val; 175 176 ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq, 177 IRQF_SHARED, "error irq", priv); 178 if (ret) { 179 dev_err(dev, "cannot claim IRQ for error handling\n"); 180 return; 181 } 182 183 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG); 184 val |= RCAR_PCI_INT_ALLERRORS; 185 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); 186 } 187 #else 188 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { } 189 #endif 190 191 /* PCI host controller setup */ 192 static int rcar_pci_setup(int nr, struct pci_sys_data *sys) 193 { 194 struct rcar_pci_priv *priv = sys->private_data; 195 struct device *dev = priv->dev; 196 void __iomem *reg = priv->reg; 197 u32 val; 198 int ret; 199 200 pm_runtime_enable(dev); 201 pm_runtime_get_sync(dev); 202 203 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG); 204 dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val); 205 206 /* Disable Direct Power Down State and assert reset */ 207 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; 208 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST; 209 iowrite32(val, reg + RCAR_USBCTR_REG); 210 udelay(4); 211 212 /* De-assert reset and reset PCIAHB window1 size */ 213 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK | 214 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST); 215 216 /* Setup PCIAHB window1 size */ 217 switch (priv->window_size) { 218 case SZ_2G: 219 val |= RCAR_USBCTR_PCIAHB_WIN1_2G; 220 break; 221 case SZ_1G: 222 val |= RCAR_USBCTR_PCIAHB_WIN1_1G; 223 break; 224 case SZ_512M: 225 val |= RCAR_USBCTR_PCIAHB_WIN1_512M; 226 break; 227 default: 228 pr_warn("unknown window size %ld - defaulting to 256M\n", 229 priv->window_size); 230 priv->window_size = SZ_256M; 231 /* fall-through */ 232 case SZ_256M: 233 val |= RCAR_USBCTR_PCIAHB_WIN1_256M; 234 break; 235 } 236 iowrite32(val, reg + RCAR_USBCTR_REG); 237 238 /* Configure AHB master and slave modes */ 239 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG); 240 241 /* Configure PCI arbiter */ 242 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG); 243 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 | 244 RCAR_PCI_ARBITER_PCIBP_MODE; 245 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG); 246 247 /* PCI-AHB mapping */ 248 iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16, 249 reg + RCAR_PCIAHB_WIN1_CTR_REG); 250 251 /* AHB-PCI mapping: OHCI/EHCI registers */ 252 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM; 253 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG); 254 255 /* Enable AHB-PCI bridge PCI configuration access */ 256 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG, 257 reg + RCAR_AHBPCI_WIN1_CTR_REG); 258 /* Set PCI-AHB Window1 address */ 259 iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH, 260 reg + PCI_BASE_ADDRESS_1); 261 /* Set AHB-PCI bridge PCI communication area address */ 262 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET; 263 iowrite32(val, reg + PCI_BASE_ADDRESS_0); 264 265 val = ioread32(reg + PCI_COMMAND); 266 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | 267 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 268 iowrite32(val, reg + PCI_COMMAND); 269 270 /* Enable PCI interrupts */ 271 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME, 272 reg + RCAR_PCI_INT_ENABLE_REG); 273 274 if (priv->irq > 0) 275 rcar_pci_setup_errirq(priv); 276 277 /* Add PCI resources */ 278 pci_add_resource(&sys->resources, &priv->mem_res); 279 ret = devm_request_pci_bus_resources(dev, &sys->resources); 280 if (ret < 0) 281 return ret; 282 283 /* Setup bus number based on platform device id / of bus-range */ 284 sys->busnr = priv->busnr; 285 return 1; 286 } 287 288 static struct pci_ops rcar_pci_ops = { 289 .map_bus = rcar_pci_cfg_base, 290 .read = pci_generic_config_read, 291 .write = pci_generic_config_write, 292 }; 293 294 static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci, 295 struct device_node *np) 296 { 297 struct device *dev = pci->dev; 298 struct of_pci_range range; 299 struct of_pci_range_parser parser; 300 int index = 0; 301 302 /* Failure to parse is ok as we fall back to defaults */ 303 if (of_pci_dma_range_parser_init(&parser, np)) 304 return 0; 305 306 /* Get the dma-ranges from DT */ 307 for_each_of_pci_range(&parser, &range) { 308 /* Hardware only allows one inbound 32-bit range */ 309 if (index) 310 return -EINVAL; 311 312 pci->window_addr = (unsigned long)range.cpu_addr; 313 pci->window_pci = (unsigned long)range.pci_addr; 314 pci->window_size = (unsigned long)range.size; 315 316 /* Catch HW limitations */ 317 if (!(range.flags & IORESOURCE_PREFETCH)) { 318 dev_err(dev, "window must be prefetchable\n"); 319 return -EINVAL; 320 } 321 if (pci->window_addr) { 322 u32 lowaddr = 1 << (ffs(pci->window_addr) - 1); 323 324 if (lowaddr < pci->window_size) { 325 dev_err(dev, "invalid window size/addr\n"); 326 return -EINVAL; 327 } 328 } 329 index++; 330 } 331 332 return 0; 333 } 334 335 static int rcar_pci_probe(struct platform_device *pdev) 336 { 337 struct device *dev = &pdev->dev; 338 struct resource *cfg_res, *mem_res; 339 struct rcar_pci_priv *priv; 340 void __iomem *reg; 341 struct hw_pci hw; 342 void *hw_private[1]; 343 344 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 345 reg = devm_ioremap_resource(dev, cfg_res); 346 if (IS_ERR(reg)) 347 return PTR_ERR(reg); 348 349 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 350 if (!mem_res || !mem_res->start) 351 return -ENODEV; 352 353 if (mem_res->start & 0xFFFF) 354 return -EINVAL; 355 356 priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL); 357 if (!priv) 358 return -ENOMEM; 359 360 priv->mem_res = *mem_res; 361 priv->cfg_res = cfg_res; 362 363 priv->irq = platform_get_irq(pdev, 0); 364 priv->reg = reg; 365 priv->dev = dev; 366 367 if (priv->irq < 0) { 368 dev_err(dev, "no valid irq found\n"); 369 return priv->irq; 370 } 371 372 /* default window addr and size if not specified in DT */ 373 priv->window_addr = 0x40000000; 374 priv->window_pci = 0x40000000; 375 priv->window_size = SZ_1G; 376 377 if (dev->of_node) { 378 struct resource busnr; 379 int ret; 380 381 ret = of_pci_parse_bus_range(dev->of_node, &busnr); 382 if (ret < 0) { 383 dev_err(dev, "failed to parse bus-range\n"); 384 return ret; 385 } 386 387 priv->busnr = busnr.start; 388 if (busnr.end != busnr.start) 389 dev_warn(dev, "only one bus number supported\n"); 390 391 ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node); 392 if (ret < 0) { 393 dev_err(dev, "failed to parse dma-range\n"); 394 return ret; 395 } 396 } else { 397 priv->busnr = pdev->id; 398 } 399 400 hw_private[0] = priv; 401 memset(&hw, 0, sizeof(hw)); 402 hw.nr_controllers = ARRAY_SIZE(hw_private); 403 hw.io_optional = 1; 404 hw.private_data = hw_private; 405 hw.map_irq = rcar_pci_map_irq; 406 hw.ops = &rcar_pci_ops; 407 hw.setup = rcar_pci_setup; 408 pci_common_init_dev(dev, &hw); 409 return 0; 410 } 411 412 static const struct of_device_id rcar_pci_of_match[] = { 413 { .compatible = "renesas,pci-r8a7790", }, 414 { .compatible = "renesas,pci-r8a7791", }, 415 { .compatible = "renesas,pci-r8a7794", }, 416 { .compatible = "renesas,pci-rcar-gen2", }, 417 { }, 418 }; 419 420 static struct platform_driver rcar_pci_driver = { 421 .driver = { 422 .name = "pci-rcar-gen2", 423 .suppress_bind_attrs = true, 424 .of_match_table = rcar_pci_of_match, 425 }, 426 .probe = rcar_pci_probe, 427 }; 428 builtin_platform_driver(rcar_pci_driver); 429