1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio.h> 13 #include <linux/init.h> 14 #include <linux/mbus.h> 15 #include <linux/msi.h> 16 #include <linux/slab.h> 17 #include <linux/platform_device.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_pci.h> 22 #include <linux/of_platform.h> 23 24 #include "../pci.h" 25 #include "../pci-bridge-emul.h" 26 27 /* 28 * PCIe unit register offsets. 29 */ 30 #define PCIE_DEV_ID_OFF 0x0000 31 #define PCIE_CMD_OFF 0x0004 32 #define PCIE_DEV_REV_OFF 0x0008 33 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 34 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 35 #define PCIE_CAP_PCIEXP 0x0060 36 #define PCIE_HEADER_LOG_4_OFF 0x0128 37 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 38 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 39 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 40 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 41 #define PCIE_WIN5_CTRL_OFF 0x1880 42 #define PCIE_WIN5_BASE_OFF 0x1884 43 #define PCIE_WIN5_REMAP_OFF 0x188c 44 #define PCIE_CONF_ADDR_OFF 0x18f8 45 #define PCIE_CONF_ADDR_EN 0x80000000 46 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 47 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 48 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 49 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 50 #define PCIE_CONF_ADDR(bus, devfn, where) \ 51 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 52 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 53 PCIE_CONF_ADDR_EN) 54 #define PCIE_CONF_DATA_OFF 0x18fc 55 #define PCIE_MASK_OFF 0x1910 56 #define PCIE_MASK_ENABLE_INTS 0x0f000000 57 #define PCIE_CTRL_OFF 0x1a00 58 #define PCIE_CTRL_X1_MODE 0x0001 59 #define PCIE_STAT_OFF 0x1a04 60 #define PCIE_STAT_BUS 0xff00 61 #define PCIE_STAT_DEV 0x1f0000 62 #define PCIE_STAT_LINK_DOWN BIT(0) 63 #define PCIE_RC_RTSTA 0x1a14 64 #define PCIE_DEBUG_CTRL 0x1a60 65 #define PCIE_DEBUG_SOFT_RESET BIT(20) 66 67 struct mvebu_pcie_port; 68 69 /* Structure representing all PCIe interfaces */ 70 struct mvebu_pcie { 71 struct platform_device *pdev; 72 struct mvebu_pcie_port *ports; 73 struct msi_controller *msi; 74 struct resource io; 75 struct resource realio; 76 struct resource mem; 77 struct resource busn; 78 int nports; 79 }; 80 81 struct mvebu_pcie_window { 82 phys_addr_t base; 83 phys_addr_t remap; 84 size_t size; 85 }; 86 87 /* Structure representing one PCIe interface */ 88 struct mvebu_pcie_port { 89 char *name; 90 void __iomem *base; 91 u32 port; 92 u32 lane; 93 int devfn; 94 unsigned int mem_target; 95 unsigned int mem_attr; 96 unsigned int io_target; 97 unsigned int io_attr; 98 struct clk *clk; 99 struct gpio_desc *reset_gpio; 100 char *reset_name; 101 struct pci_bridge_emul bridge; 102 struct device_node *dn; 103 struct mvebu_pcie *pcie; 104 struct mvebu_pcie_window memwin; 105 struct mvebu_pcie_window iowin; 106 u32 saved_pcie_stat; 107 struct resource regs; 108 }; 109 110 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 111 { 112 writel(val, port->base + reg); 113 } 114 115 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 116 { 117 return readl(port->base + reg); 118 } 119 120 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 121 { 122 return port->io_target != -1 && port->io_attr != -1; 123 } 124 125 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 126 { 127 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 128 } 129 130 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 131 { 132 u32 stat; 133 134 stat = mvebu_readl(port, PCIE_STAT_OFF); 135 stat &= ~PCIE_STAT_BUS; 136 stat |= nr << 8; 137 mvebu_writel(port, stat, PCIE_STAT_OFF); 138 } 139 140 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 141 { 142 u32 stat; 143 144 stat = mvebu_readl(port, PCIE_STAT_OFF); 145 stat &= ~PCIE_STAT_DEV; 146 stat |= nr << 16; 147 mvebu_writel(port, stat, PCIE_STAT_OFF); 148 } 149 150 /* 151 * Setup PCIE BARs and Address Decode Wins: 152 * BAR[0] -> internal registers (needed for MSI) 153 * BAR[1] -> covers all DRAM banks 154 * BAR[2] -> Disabled 155 * WIN[0-3] -> DRAM bank[0-3] 156 */ 157 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 158 { 159 const struct mbus_dram_target_info *dram; 160 u32 size; 161 int i; 162 163 dram = mv_mbus_dram_info(); 164 165 /* First, disable and clear BARs and windows. */ 166 for (i = 1; i < 3; i++) { 167 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 168 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 169 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 170 } 171 172 for (i = 0; i < 5; i++) { 173 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 174 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 175 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 176 } 177 178 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 179 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 180 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 181 182 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 183 size = 0; 184 for (i = 0; i < dram->num_cs; i++) { 185 const struct mbus_dram_window *cs = dram->cs + i; 186 187 mvebu_writel(port, cs->base & 0xffff0000, 188 PCIE_WIN04_BASE_OFF(i)); 189 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 190 mvebu_writel(port, 191 ((cs->size - 1) & 0xffff0000) | 192 (cs->mbus_attr << 8) | 193 (dram->mbus_dram_target_id << 4) | 1, 194 PCIE_WIN04_CTRL_OFF(i)); 195 196 size += cs->size; 197 } 198 199 /* Round up 'size' to the nearest power of two. */ 200 if ((size & (size - 1)) != 0) 201 size = 1 << fls(size); 202 203 /* Setup BAR[1] to all DRAM banks. */ 204 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 205 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 206 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 207 PCIE_BAR_CTRL_OFF(1)); 208 209 /* 210 * Point BAR[0] to the device's internal registers. 211 */ 212 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); 213 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); 214 } 215 216 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 217 { 218 u32 cmd, mask; 219 220 /* Point PCIe unit MBUS decode windows to DRAM space. */ 221 mvebu_pcie_setup_wins(port); 222 223 /* Master + slave enable. */ 224 cmd = mvebu_readl(port, PCIE_CMD_OFF); 225 cmd |= PCI_COMMAND_IO; 226 cmd |= PCI_COMMAND_MEMORY; 227 cmd |= PCI_COMMAND_MASTER; 228 mvebu_writel(port, cmd, PCIE_CMD_OFF); 229 230 /* Enable interrupt lines A-D. */ 231 mask = mvebu_readl(port, PCIE_MASK_OFF); 232 mask |= PCIE_MASK_ENABLE_INTS; 233 mvebu_writel(port, mask, PCIE_MASK_OFF); 234 } 235 236 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, 237 struct pci_bus *bus, 238 u32 devfn, int where, int size, u32 *val) 239 { 240 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 241 242 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 243 PCIE_CONF_ADDR_OFF); 244 245 switch (size) { 246 case 1: 247 *val = readb_relaxed(conf_data + (where & 3)); 248 break; 249 case 2: 250 *val = readw_relaxed(conf_data + (where & 2)); 251 break; 252 case 4: 253 *val = readl_relaxed(conf_data); 254 break; 255 } 256 257 return PCIBIOS_SUCCESSFUL; 258 } 259 260 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, 261 struct pci_bus *bus, 262 u32 devfn, int where, int size, u32 val) 263 { 264 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 265 266 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 267 PCIE_CONF_ADDR_OFF); 268 269 switch (size) { 270 case 1: 271 writeb(val, conf_data + (where & 3)); 272 break; 273 case 2: 274 writew(val, conf_data + (where & 2)); 275 break; 276 case 4: 277 writel(val, conf_data); 278 break; 279 default: 280 return PCIBIOS_BAD_REGISTER_NUMBER; 281 } 282 283 return PCIBIOS_SUCCESSFUL; 284 } 285 286 /* 287 * Remove windows, starting from the largest ones to the smallest 288 * ones. 289 */ 290 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, 291 phys_addr_t base, size_t size) 292 { 293 while (size) { 294 size_t sz = 1 << (fls(size) - 1); 295 296 mvebu_mbus_del_window(base, sz); 297 base += sz; 298 size -= sz; 299 } 300 } 301 302 /* 303 * MBus windows can only have a power of two size, but PCI BARs do not 304 * have this constraint. Therefore, we have to split the PCI BAR into 305 * areas each having a power of two size. We start from the largest 306 * one (i.e highest order bit set in the size). 307 */ 308 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, 309 unsigned int target, unsigned int attribute, 310 phys_addr_t base, size_t size, 311 phys_addr_t remap) 312 { 313 size_t size_mapped = 0; 314 315 while (size) { 316 size_t sz = 1 << (fls(size) - 1); 317 int ret; 318 319 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, 320 sz, remap); 321 if (ret) { 322 phys_addr_t end = base + sz - 1; 323 324 dev_err(&port->pcie->pdev->dev, 325 "Could not create MBus window at [mem %pa-%pa]: %d\n", 326 &base, &end, ret); 327 mvebu_pcie_del_windows(port, base - size_mapped, 328 size_mapped); 329 return; 330 } 331 332 size -= sz; 333 size_mapped += sz; 334 base += sz; 335 if (remap != MVEBU_MBUS_NO_REMAP) 336 remap += sz; 337 } 338 } 339 340 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port, 341 unsigned int target, unsigned int attribute, 342 const struct mvebu_pcie_window *desired, 343 struct mvebu_pcie_window *cur) 344 { 345 if (desired->base == cur->base && desired->remap == cur->remap && 346 desired->size == cur->size) 347 return; 348 349 if (cur->size != 0) { 350 mvebu_pcie_del_windows(port, cur->base, cur->size); 351 cur->size = 0; 352 cur->base = 0; 353 354 /* 355 * If something tries to change the window while it is enabled 356 * the change will not be done atomically. That would be 357 * difficult to do in the general case. 358 */ 359 } 360 361 if (desired->size == 0) 362 return; 363 364 mvebu_pcie_add_windows(port, target, attribute, desired->base, 365 desired->size, desired->remap); 366 *cur = *desired; 367 } 368 369 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 370 { 371 struct mvebu_pcie_window desired = {}; 372 struct pci_bridge_emul_conf *conf = &port->bridge.conf; 373 374 /* Are the new iobase/iolimit values invalid? */ 375 if (conf->iolimit < conf->iobase || 376 conf->iolimitupper < conf->iobaseupper || 377 !(conf->command & PCI_COMMAND_IO)) { 378 mvebu_pcie_set_window(port, port->io_target, port->io_attr, 379 &desired, &port->iowin); 380 return; 381 } 382 383 if (!mvebu_has_ioport(port)) { 384 dev_WARN(&port->pcie->pdev->dev, 385 "Attempt to set IO when IO is disabled\n"); 386 return; 387 } 388 389 /* 390 * We read the PCI-to-PCI bridge emulated registers, and 391 * calculate the base address and size of the address decoding 392 * window to setup, according to the PCI-to-PCI bridge 393 * specifications. iobase is the bus address, port->iowin_base 394 * is the CPU address. 395 */ 396 desired.remap = ((conf->iobase & 0xF0) << 8) | 397 (conf->iobaseupper << 16); 398 desired.base = port->pcie->io.start + desired.remap; 399 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) | 400 (conf->iolimitupper << 16)) - 401 desired.remap) + 402 1; 403 404 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, 405 &port->iowin); 406 } 407 408 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 409 { 410 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; 411 struct pci_bridge_emul_conf *conf = &port->bridge.conf; 412 413 /* Are the new membase/memlimit values invalid? */ 414 if (conf->memlimit < conf->membase || 415 !(conf->command & PCI_COMMAND_MEMORY)) { 416 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, 417 &desired, &port->memwin); 418 return; 419 } 420 421 /* 422 * We read the PCI-to-PCI bridge emulated registers, and 423 * calculate the base address and size of the address decoding 424 * window to setup, according to the PCI-to-PCI bridge 425 * specifications. 426 */ 427 desired.base = ((conf->membase & 0xFFF0) << 16); 428 desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) - 429 desired.base + 1; 430 431 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, 432 &port->memwin); 433 } 434 435 static pci_bridge_emul_read_status_t 436 mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 437 int reg, u32 *value) 438 { 439 struct mvebu_pcie_port *port = bridge->data; 440 441 switch (reg) { 442 case PCI_EXP_DEVCAP: 443 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); 444 break; 445 446 case PCI_EXP_DEVCTL: 447 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) & 448 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 449 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 450 break; 451 452 case PCI_EXP_LNKCAP: 453 /* 454 * PCIe requires the clock power management capability to be 455 * hard-wired to zero for downstream ports 456 */ 457 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & 458 ~PCI_EXP_LNKCAP_CLKPM; 459 break; 460 461 case PCI_EXP_LNKCTL: 462 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 463 break; 464 465 case PCI_EXP_SLTCTL: 466 *value = PCI_EXP_SLTSTA_PDS << 16; 467 break; 468 469 case PCI_EXP_RTSTA: 470 *value = mvebu_readl(port, PCIE_RC_RTSTA); 471 break; 472 473 default: 474 return PCI_BRIDGE_EMUL_NOT_HANDLED; 475 } 476 477 return PCI_BRIDGE_EMUL_HANDLED; 478 } 479 480 static void 481 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 482 int reg, u32 old, u32 new, u32 mask) 483 { 484 struct mvebu_pcie_port *port = bridge->data; 485 struct pci_bridge_emul_conf *conf = &bridge->conf; 486 487 switch (reg) { 488 case PCI_COMMAND: 489 { 490 if (!mvebu_has_ioport(port)) 491 conf->command &= ~PCI_COMMAND_IO; 492 493 if ((old ^ new) & PCI_COMMAND_IO) 494 mvebu_pcie_handle_iobase_change(port); 495 if ((old ^ new) & PCI_COMMAND_MEMORY) 496 mvebu_pcie_handle_membase_change(port); 497 498 break; 499 } 500 501 case PCI_IO_BASE: 502 /* 503 * We keep bit 1 set, it is a read-only bit that 504 * indicates we support 32 bits addressing for the 505 * I/O 506 */ 507 conf->iobase |= PCI_IO_RANGE_TYPE_32; 508 conf->iolimit |= PCI_IO_RANGE_TYPE_32; 509 mvebu_pcie_handle_iobase_change(port); 510 break; 511 512 case PCI_MEMORY_BASE: 513 mvebu_pcie_handle_membase_change(port); 514 break; 515 516 case PCI_IO_BASE_UPPER16: 517 mvebu_pcie_handle_iobase_change(port); 518 break; 519 520 case PCI_PRIMARY_BUS: 521 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); 522 break; 523 524 default: 525 break; 526 } 527 } 528 529 static void 530 mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 531 int reg, u32 old, u32 new, u32 mask) 532 { 533 struct mvebu_pcie_port *port = bridge->data; 534 535 switch (reg) { 536 case PCI_EXP_DEVCTL: 537 /* 538 * Armada370 data says these bits must always 539 * be zero when in root complex mode. 540 */ 541 new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 542 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 543 544 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 545 break; 546 547 case PCI_EXP_LNKCTL: 548 /* 549 * If we don't support CLKREQ, we must ensure that the 550 * CLKREQ enable bit always reads zero. Since we haven't 551 * had this capability, and it's dependent on board wiring, 552 * disable it for the time being. 553 */ 554 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 555 556 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 557 break; 558 559 case PCI_EXP_RTSTA: 560 mvebu_writel(port, new, PCIE_RC_RTSTA); 561 break; 562 } 563 } 564 565 static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { 566 .write_base = mvebu_pci_bridge_emul_base_conf_write, 567 .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, 568 .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write, 569 }; 570 571 /* 572 * Initialize the configuration space of the PCI-to-PCI bridge 573 * associated with the given PCIe interface. 574 */ 575 static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) 576 { 577 struct pci_bridge_emul *bridge = &port->bridge; 578 579 bridge->conf.vendor = PCI_VENDOR_ID_MARVELL; 580 bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; 581 bridge->conf.class_revision = 582 mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; 583 584 if (mvebu_has_ioport(port)) { 585 /* We support 32 bits I/O addressing */ 586 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 587 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 588 } 589 590 bridge->has_pcie = true; 591 bridge->data = port; 592 bridge->ops = &mvebu_pci_bridge_emul_ops; 593 594 pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR); 595 } 596 597 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 598 { 599 return sys->private_data; 600 } 601 602 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 603 struct pci_bus *bus, 604 int devfn) 605 { 606 int i; 607 608 for (i = 0; i < pcie->nports; i++) { 609 struct mvebu_pcie_port *port = &pcie->ports[i]; 610 611 if (bus->number == 0 && port->devfn == devfn) 612 return port; 613 if (bus->number != 0 && 614 bus->number >= port->bridge.conf.secondary_bus && 615 bus->number <= port->bridge.conf.subordinate_bus) 616 return port; 617 } 618 619 return NULL; 620 } 621 622 /* PCI configuration space write function */ 623 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 624 int where, int size, u32 val) 625 { 626 struct mvebu_pcie *pcie = bus->sysdata; 627 struct mvebu_pcie_port *port; 628 int ret; 629 630 port = mvebu_pcie_find_port(pcie, bus, devfn); 631 if (!port) 632 return PCIBIOS_DEVICE_NOT_FOUND; 633 634 /* Access the emulated PCI-to-PCI bridge */ 635 if (bus->number == 0) 636 return pci_bridge_emul_conf_write(&port->bridge, where, 637 size, val); 638 639 if (!mvebu_pcie_link_up(port)) 640 return PCIBIOS_DEVICE_NOT_FOUND; 641 642 /* Access the real PCIe interface */ 643 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 644 where, size, val); 645 646 return ret; 647 } 648 649 /* PCI configuration space read function */ 650 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 651 int size, u32 *val) 652 { 653 struct mvebu_pcie *pcie = bus->sysdata; 654 struct mvebu_pcie_port *port; 655 int ret; 656 657 port = mvebu_pcie_find_port(pcie, bus, devfn); 658 if (!port) { 659 *val = 0xffffffff; 660 return PCIBIOS_DEVICE_NOT_FOUND; 661 } 662 663 /* Access the emulated PCI-to-PCI bridge */ 664 if (bus->number == 0) 665 return pci_bridge_emul_conf_read(&port->bridge, where, 666 size, val); 667 668 if (!mvebu_pcie_link_up(port)) { 669 *val = 0xffffffff; 670 return PCIBIOS_DEVICE_NOT_FOUND; 671 } 672 673 /* Access the real PCIe interface */ 674 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 675 where, size, val); 676 677 return ret; 678 } 679 680 static struct pci_ops mvebu_pcie_ops = { 681 .read = mvebu_pcie_rd_conf, 682 .write = mvebu_pcie_wr_conf, 683 }; 684 685 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 686 const struct resource *res, 687 resource_size_t start, 688 resource_size_t size, 689 resource_size_t align) 690 { 691 if (dev->bus->number != 0) 692 return start; 693 694 /* 695 * On the PCI-to-PCI bridge side, the I/O windows must have at 696 * least a 64 KB size and the memory windows must have at 697 * least a 1 MB size. Moreover, MBus windows need to have a 698 * base address aligned on their size, and their size must be 699 * a power of two. This means that if the BAR doesn't have a 700 * power of two size, several MBus windows will actually be 701 * created. We need to ensure that the biggest MBus window 702 * (which will be the first one) is aligned on its size, which 703 * explains the rounddown_pow_of_two() being done here. 704 */ 705 if (res->flags & IORESOURCE_IO) 706 return round_up(start, max_t(resource_size_t, SZ_64K, 707 rounddown_pow_of_two(size))); 708 else if (res->flags & IORESOURCE_MEM) 709 return round_up(start, max_t(resource_size_t, SZ_1M, 710 rounddown_pow_of_two(size))); 711 else 712 return start; 713 } 714 715 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 716 struct device_node *np, 717 struct mvebu_pcie_port *port) 718 { 719 int ret = 0; 720 721 ret = of_address_to_resource(np, 0, &port->regs); 722 if (ret) 723 return (void __iomem *)ERR_PTR(ret); 724 725 return devm_ioremap_resource(&pdev->dev, &port->regs); 726 } 727 728 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 729 #define DT_TYPE_IO 0x1 730 #define DT_TYPE_MEM32 0x2 731 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 732 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 733 734 static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 735 unsigned long type, 736 unsigned int *tgt, 737 unsigned int *attr) 738 { 739 const int na = 3, ns = 2; 740 const __be32 *range; 741 int rlen, nranges, rangesz, pna, i; 742 743 *tgt = -1; 744 *attr = -1; 745 746 range = of_get_property(np, "ranges", &rlen); 747 if (!range) 748 return -EINVAL; 749 750 pna = of_n_addr_cells(np); 751 rangesz = pna + na + ns; 752 nranges = rlen / sizeof(__be32) / rangesz; 753 754 for (i = 0; i < nranges; i++, range += rangesz) { 755 u32 flags = of_read_number(range, 1); 756 u32 slot = of_read_number(range + 1, 1); 757 u64 cpuaddr = of_read_number(range + na, pna); 758 unsigned long rtype; 759 760 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 761 rtype = IORESOURCE_IO; 762 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 763 rtype = IORESOURCE_MEM; 764 else 765 continue; 766 767 if (slot == PCI_SLOT(devfn) && type == rtype) { 768 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 769 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 770 return 0; 771 } 772 } 773 774 return -ENOENT; 775 } 776 777 #ifdef CONFIG_PM_SLEEP 778 static int mvebu_pcie_suspend(struct device *dev) 779 { 780 struct mvebu_pcie *pcie; 781 int i; 782 783 pcie = dev_get_drvdata(dev); 784 for (i = 0; i < pcie->nports; i++) { 785 struct mvebu_pcie_port *port = pcie->ports + i; 786 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); 787 } 788 789 return 0; 790 } 791 792 static int mvebu_pcie_resume(struct device *dev) 793 { 794 struct mvebu_pcie *pcie; 795 int i; 796 797 pcie = dev_get_drvdata(dev); 798 for (i = 0; i < pcie->nports; i++) { 799 struct mvebu_pcie_port *port = pcie->ports + i; 800 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); 801 mvebu_pcie_setup_hw(port); 802 } 803 804 return 0; 805 } 806 #endif 807 808 static void mvebu_pcie_port_clk_put(void *data) 809 { 810 struct mvebu_pcie_port *port = data; 811 812 clk_put(port->clk); 813 } 814 815 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, 816 struct mvebu_pcie_port *port, struct device_node *child) 817 { 818 struct device *dev = &pcie->pdev->dev; 819 enum of_gpio_flags flags; 820 int reset_gpio, ret; 821 822 port->pcie = pcie; 823 824 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { 825 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", 826 child); 827 goto skip; 828 } 829 830 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) 831 port->lane = 0; 832 833 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, 834 port->lane); 835 if (!port->name) { 836 ret = -ENOMEM; 837 goto err; 838 } 839 840 port->devfn = of_pci_get_devfn(child); 841 if (port->devfn < 0) 842 goto skip; 843 844 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, 845 &port->mem_target, &port->mem_attr); 846 if (ret < 0) { 847 dev_err(dev, "%s: cannot get tgt/attr for mem window\n", 848 port->name); 849 goto skip; 850 } 851 852 if (resource_size(&pcie->io) != 0) { 853 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, 854 &port->io_target, &port->io_attr); 855 } else { 856 port->io_target = -1; 857 port->io_attr = -1; 858 } 859 860 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); 861 if (reset_gpio == -EPROBE_DEFER) { 862 ret = reset_gpio; 863 goto err; 864 } 865 866 if (gpio_is_valid(reset_gpio)) { 867 unsigned long gpio_flags; 868 869 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", 870 port->name); 871 if (!port->reset_name) { 872 ret = -ENOMEM; 873 goto err; 874 } 875 876 if (flags & OF_GPIO_ACTIVE_LOW) { 877 dev_info(dev, "%pOF: reset gpio is active low\n", 878 child); 879 gpio_flags = GPIOF_ACTIVE_LOW | 880 GPIOF_OUT_INIT_LOW; 881 } else { 882 gpio_flags = GPIOF_OUT_INIT_HIGH; 883 } 884 885 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags, 886 port->reset_name); 887 if (ret) { 888 if (ret == -EPROBE_DEFER) 889 goto err; 890 goto skip; 891 } 892 893 port->reset_gpio = gpio_to_desc(reset_gpio); 894 } 895 896 port->clk = of_clk_get_by_name(child, NULL); 897 if (IS_ERR(port->clk)) { 898 dev_err(dev, "%s: cannot get clock\n", port->name); 899 goto skip; 900 } 901 902 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port); 903 if (ret < 0) { 904 clk_put(port->clk); 905 goto err; 906 } 907 908 return 1; 909 910 skip: 911 ret = 0; 912 913 /* In the case of skipping, we need to free these */ 914 devm_kfree(dev, port->reset_name); 915 port->reset_name = NULL; 916 devm_kfree(dev, port->name); 917 port->name = NULL; 918 919 err: 920 return ret; 921 } 922 923 /* 924 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs 925 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications 926 * of the PCI Express Card Electromechanical Specification, 1.1. 927 */ 928 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) 929 { 930 int ret; 931 932 ret = clk_prepare_enable(port->clk); 933 if (ret < 0) 934 return ret; 935 936 if (port->reset_gpio) { 937 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; 938 939 of_property_read_u32(port->dn, "reset-delay-us", 940 &reset_udelay); 941 942 udelay(100); 943 944 gpiod_set_value_cansleep(port->reset_gpio, 0); 945 msleep(reset_udelay / 1000); 946 } 947 948 return 0; 949 } 950 951 /* 952 * Power down a PCIe port. Strictly, PCIe requires us to place the card 953 * in D3hot state before asserting PERST#. 954 */ 955 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port) 956 { 957 gpiod_set_value_cansleep(port->reset_gpio, 1); 958 959 clk_disable_unprepare(port->clk); 960 } 961 962 /* 963 * We can't use devm_of_pci_get_host_bridge_resources() because we 964 * need to parse our special DT properties encoding the MEM and IO 965 * apertures. 966 */ 967 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie) 968 { 969 struct device *dev = &pcie->pdev->dev; 970 struct device_node *np = dev->of_node; 971 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 972 int ret; 973 974 /* Get the bus range */ 975 ret = of_pci_parse_bus_range(np, &pcie->busn); 976 if (ret) { 977 dev_err(dev, "failed to parse bus-range property: %d\n", ret); 978 return ret; 979 } 980 pci_add_resource(&bridge->windows, &pcie->busn); 981 982 /* Get the PCIe memory aperture */ 983 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 984 if (resource_size(&pcie->mem) == 0) { 985 dev_err(dev, "invalid memory aperture size\n"); 986 return -EINVAL; 987 } 988 989 pcie->mem.name = "PCI MEM"; 990 pci_add_resource(&bridge->windows, &pcie->mem); 991 992 /* Get the PCIe IO aperture */ 993 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 994 995 if (resource_size(&pcie->io) != 0) { 996 pcie->realio.flags = pcie->io.flags; 997 pcie->realio.start = PCIBIOS_MIN_IO; 998 pcie->realio.end = min_t(resource_size_t, 999 IO_SPACE_LIMIT - SZ_64K, 1000 resource_size(&pcie->io) - 1); 1001 pcie->realio.name = "PCI I/O"; 1002 1003 pci_add_resource(&bridge->windows, &pcie->realio); 1004 } 1005 1006 return devm_request_pci_bus_resources(dev, &bridge->windows); 1007 } 1008 1009 /* 1010 * This is a copy of pci_host_probe(), except that it does the I/O 1011 * remap as the last step, once we are sure we won't fail. 1012 * 1013 * It should be removed once the I/O remap error handling issue has 1014 * been sorted out. 1015 */ 1016 static int mvebu_pci_host_probe(struct pci_host_bridge *bridge) 1017 { 1018 struct mvebu_pcie *pcie; 1019 struct pci_bus *bus, *child; 1020 int ret; 1021 1022 ret = pci_scan_root_bus_bridge(bridge); 1023 if (ret < 0) { 1024 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 1025 return ret; 1026 } 1027 1028 pcie = pci_host_bridge_priv(bridge); 1029 if (resource_size(&pcie->io) != 0) { 1030 unsigned int i; 1031 1032 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K) 1033 pci_ioremap_io(i, pcie->io.start + i); 1034 } 1035 1036 bus = bridge->bus; 1037 1038 /* 1039 * We insert PCI resources into the iomem_resource and 1040 * ioport_resource trees in either pci_bus_claim_resources() 1041 * or pci_bus_assign_resources(). 1042 */ 1043 if (pci_has_flag(PCI_PROBE_ONLY)) { 1044 pci_bus_claim_resources(bus); 1045 } else { 1046 pci_bus_size_bridges(bus); 1047 pci_bus_assign_resources(bus); 1048 1049 list_for_each_entry(child, &bus->children, node) 1050 pcie_bus_configure_settings(child); 1051 } 1052 1053 pci_bus_add_devices(bus); 1054 return 0; 1055 } 1056 1057 static int mvebu_pcie_probe(struct platform_device *pdev) 1058 { 1059 struct device *dev = &pdev->dev; 1060 struct mvebu_pcie *pcie; 1061 struct pci_host_bridge *bridge; 1062 struct device_node *np = dev->of_node; 1063 struct device_node *child; 1064 int num, i, ret; 1065 1066 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie)); 1067 if (!bridge) 1068 return -ENOMEM; 1069 1070 pcie = pci_host_bridge_priv(bridge); 1071 pcie->pdev = pdev; 1072 platform_set_drvdata(pdev, pcie); 1073 1074 ret = mvebu_pcie_parse_request_resources(pcie); 1075 if (ret) 1076 return ret; 1077 1078 num = of_get_available_child_count(np); 1079 1080 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); 1081 if (!pcie->ports) 1082 return -ENOMEM; 1083 1084 i = 0; 1085 for_each_available_child_of_node(np, child) { 1086 struct mvebu_pcie_port *port = &pcie->ports[i]; 1087 1088 ret = mvebu_pcie_parse_port(pcie, port, child); 1089 if (ret < 0) { 1090 of_node_put(child); 1091 return ret; 1092 } else if (ret == 0) { 1093 continue; 1094 } 1095 1096 port->dn = child; 1097 i++; 1098 } 1099 pcie->nports = i; 1100 1101 for (i = 0; i < pcie->nports; i++) { 1102 struct mvebu_pcie_port *port = &pcie->ports[i]; 1103 1104 child = port->dn; 1105 if (!child) 1106 continue; 1107 1108 ret = mvebu_pcie_powerup(port); 1109 if (ret < 0) 1110 continue; 1111 1112 port->base = mvebu_pcie_map_registers(pdev, child, port); 1113 if (IS_ERR(port->base)) { 1114 dev_err(dev, "%s: cannot map registers\n", port->name); 1115 port->base = NULL; 1116 mvebu_pcie_powerdown(port); 1117 continue; 1118 } 1119 1120 mvebu_pcie_setup_hw(port); 1121 mvebu_pcie_set_local_dev_nr(port, 1); 1122 mvebu_pci_bridge_emul_init(port); 1123 } 1124 1125 pcie->nports = i; 1126 1127 bridge->sysdata = pcie; 1128 bridge->ops = &mvebu_pcie_ops; 1129 bridge->align_resource = mvebu_pcie_align_resource; 1130 bridge->msi = pcie->msi; 1131 1132 return mvebu_pci_host_probe(bridge); 1133 } 1134 1135 static const struct of_device_id mvebu_pcie_of_match_table[] = { 1136 { .compatible = "marvell,armada-xp-pcie", }, 1137 { .compatible = "marvell,armada-370-pcie", }, 1138 { .compatible = "marvell,dove-pcie", }, 1139 { .compatible = "marvell,kirkwood-pcie", }, 1140 {}, 1141 }; 1142 1143 static const struct dev_pm_ops mvebu_pcie_pm_ops = { 1144 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume) 1145 }; 1146 1147 static struct platform_driver mvebu_pcie_driver = { 1148 .driver = { 1149 .name = "mvebu-pcie", 1150 .of_match_table = mvebu_pcie_of_match_table, 1151 /* driver unloading/unbinding currently not supported */ 1152 .suppress_bind_attrs = true, 1153 .pm = &mvebu_pcie_pm_ops, 1154 }, 1155 .probe = mvebu_pcie_probe, 1156 }; 1157 builtin_platform_driver(mvebu_pcie_driver); 1158