1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio.h> 13 #include <linux/init.h> 14 #include <linux/mbus.h> 15 #include <linux/msi.h> 16 #include <linux/slab.h> 17 #include <linux/platform_device.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_pci.h> 22 #include <linux/of_platform.h> 23 24 #include "../pci.h" 25 26 /* 27 * PCIe unit register offsets. 28 */ 29 #define PCIE_DEV_ID_OFF 0x0000 30 #define PCIE_CMD_OFF 0x0004 31 #define PCIE_DEV_REV_OFF 0x0008 32 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 33 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 34 #define PCIE_CAP_PCIEXP 0x0060 35 #define PCIE_HEADER_LOG_4_OFF 0x0128 36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 37 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 38 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 39 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 40 #define PCIE_WIN5_CTRL_OFF 0x1880 41 #define PCIE_WIN5_BASE_OFF 0x1884 42 #define PCIE_WIN5_REMAP_OFF 0x188c 43 #define PCIE_CONF_ADDR_OFF 0x18f8 44 #define PCIE_CONF_ADDR_EN 0x80000000 45 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 46 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 47 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 48 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 49 #define PCIE_CONF_ADDR(bus, devfn, where) \ 50 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 51 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 52 PCIE_CONF_ADDR_EN) 53 #define PCIE_CONF_DATA_OFF 0x18fc 54 #define PCIE_MASK_OFF 0x1910 55 #define PCIE_MASK_ENABLE_INTS 0x0f000000 56 #define PCIE_CTRL_OFF 0x1a00 57 #define PCIE_CTRL_X1_MODE 0x0001 58 #define PCIE_STAT_OFF 0x1a04 59 #define PCIE_STAT_BUS 0xff00 60 #define PCIE_STAT_DEV 0x1f0000 61 #define PCIE_STAT_LINK_DOWN BIT(0) 62 #define PCIE_RC_RTSTA 0x1a14 63 #define PCIE_DEBUG_CTRL 0x1a60 64 #define PCIE_DEBUG_SOFT_RESET BIT(20) 65 66 enum { 67 PCISWCAP = PCI_BRIDGE_CONTROL + 2, 68 PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID, 69 PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP, 70 PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL, 71 PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP, 72 PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL, 73 PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP, 74 PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL, 75 PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL, 76 PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA, 77 PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2, 78 PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2, 79 PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2, 80 PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2, 81 PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2, 82 PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2, 83 }; 84 85 /* PCI configuration space of a PCI-to-PCI bridge */ 86 struct mvebu_sw_pci_bridge { 87 u16 vendor; 88 u16 device; 89 u16 command; 90 u16 status; 91 u16 class; 92 u8 interface; 93 u8 revision; 94 u8 bist; 95 u8 header_type; 96 u8 latency_timer; 97 u8 cache_line_size; 98 u32 bar[2]; 99 u8 primary_bus; 100 u8 secondary_bus; 101 u8 subordinate_bus; 102 u8 secondary_latency_timer; 103 u8 iobase; 104 u8 iolimit; 105 u16 secondary_status; 106 u16 membase; 107 u16 memlimit; 108 u16 iobaseupper; 109 u16 iolimitupper; 110 u32 romaddr; 111 u8 intline; 112 u8 intpin; 113 u16 bridgectrl; 114 115 /* PCI express capability */ 116 u32 pcie_sltcap; 117 u16 pcie_devctl; 118 u16 pcie_rtctl; 119 }; 120 121 struct mvebu_pcie_port; 122 123 /* Structure representing all PCIe interfaces */ 124 struct mvebu_pcie { 125 struct platform_device *pdev; 126 struct mvebu_pcie_port *ports; 127 struct msi_controller *msi; 128 struct resource io; 129 struct resource realio; 130 struct resource mem; 131 struct resource busn; 132 int nports; 133 }; 134 135 struct mvebu_pcie_window { 136 phys_addr_t base; 137 phys_addr_t remap; 138 size_t size; 139 }; 140 141 /* Structure representing one PCIe interface */ 142 struct mvebu_pcie_port { 143 char *name; 144 void __iomem *base; 145 u32 port; 146 u32 lane; 147 int devfn; 148 unsigned int mem_target; 149 unsigned int mem_attr; 150 unsigned int io_target; 151 unsigned int io_attr; 152 struct clk *clk; 153 struct gpio_desc *reset_gpio; 154 char *reset_name; 155 struct mvebu_sw_pci_bridge bridge; 156 struct device_node *dn; 157 struct mvebu_pcie *pcie; 158 struct mvebu_pcie_window memwin; 159 struct mvebu_pcie_window iowin; 160 u32 saved_pcie_stat; 161 }; 162 163 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 164 { 165 writel(val, port->base + reg); 166 } 167 168 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 169 { 170 return readl(port->base + reg); 171 } 172 173 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 174 { 175 return port->io_target != -1 && port->io_attr != -1; 176 } 177 178 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 179 { 180 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 181 } 182 183 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 184 { 185 u32 stat; 186 187 stat = mvebu_readl(port, PCIE_STAT_OFF); 188 stat &= ~PCIE_STAT_BUS; 189 stat |= nr << 8; 190 mvebu_writel(port, stat, PCIE_STAT_OFF); 191 } 192 193 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 194 { 195 u32 stat; 196 197 stat = mvebu_readl(port, PCIE_STAT_OFF); 198 stat &= ~PCIE_STAT_DEV; 199 stat |= nr << 16; 200 mvebu_writel(port, stat, PCIE_STAT_OFF); 201 } 202 203 /* 204 * Setup PCIE BARs and Address Decode Wins: 205 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 206 * WIN[0-3] -> DRAM bank[0-3] 207 */ 208 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 209 { 210 const struct mbus_dram_target_info *dram; 211 u32 size; 212 int i; 213 214 dram = mv_mbus_dram_info(); 215 216 /* First, disable and clear BARs and windows. */ 217 for (i = 1; i < 3; i++) { 218 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 219 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 220 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 221 } 222 223 for (i = 0; i < 5; i++) { 224 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 225 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 226 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 227 } 228 229 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 230 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 231 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 232 233 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 234 size = 0; 235 for (i = 0; i < dram->num_cs; i++) { 236 const struct mbus_dram_window *cs = dram->cs + i; 237 238 mvebu_writel(port, cs->base & 0xffff0000, 239 PCIE_WIN04_BASE_OFF(i)); 240 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 241 mvebu_writel(port, 242 ((cs->size - 1) & 0xffff0000) | 243 (cs->mbus_attr << 8) | 244 (dram->mbus_dram_target_id << 4) | 1, 245 PCIE_WIN04_CTRL_OFF(i)); 246 247 size += cs->size; 248 } 249 250 /* Round up 'size' to the nearest power of two. */ 251 if ((size & (size - 1)) != 0) 252 size = 1 << fls(size); 253 254 /* Setup BAR[1] to all DRAM banks. */ 255 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 256 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 257 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 258 PCIE_BAR_CTRL_OFF(1)); 259 } 260 261 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 262 { 263 u32 cmd, mask; 264 265 /* Point PCIe unit MBUS decode windows to DRAM space. */ 266 mvebu_pcie_setup_wins(port); 267 268 /* Master + slave enable. */ 269 cmd = mvebu_readl(port, PCIE_CMD_OFF); 270 cmd |= PCI_COMMAND_IO; 271 cmd |= PCI_COMMAND_MEMORY; 272 cmd |= PCI_COMMAND_MASTER; 273 mvebu_writel(port, cmd, PCIE_CMD_OFF); 274 275 /* Enable interrupt lines A-D. */ 276 mask = mvebu_readl(port, PCIE_MASK_OFF); 277 mask |= PCIE_MASK_ENABLE_INTS; 278 mvebu_writel(port, mask, PCIE_MASK_OFF); 279 } 280 281 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, 282 struct pci_bus *bus, 283 u32 devfn, int where, int size, u32 *val) 284 { 285 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 286 287 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 288 PCIE_CONF_ADDR_OFF); 289 290 switch (size) { 291 case 1: 292 *val = readb_relaxed(conf_data + (where & 3)); 293 break; 294 case 2: 295 *val = readw_relaxed(conf_data + (where & 2)); 296 break; 297 case 4: 298 *val = readl_relaxed(conf_data); 299 break; 300 } 301 302 return PCIBIOS_SUCCESSFUL; 303 } 304 305 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, 306 struct pci_bus *bus, 307 u32 devfn, int where, int size, u32 val) 308 { 309 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 310 311 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 312 PCIE_CONF_ADDR_OFF); 313 314 switch (size) { 315 case 1: 316 writeb(val, conf_data + (where & 3)); 317 break; 318 case 2: 319 writew(val, conf_data + (where & 2)); 320 break; 321 case 4: 322 writel(val, conf_data); 323 break; 324 default: 325 return PCIBIOS_BAD_REGISTER_NUMBER; 326 } 327 328 return PCIBIOS_SUCCESSFUL; 329 } 330 331 /* 332 * Remove windows, starting from the largest ones to the smallest 333 * ones. 334 */ 335 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, 336 phys_addr_t base, size_t size) 337 { 338 while (size) { 339 size_t sz = 1 << (fls(size) - 1); 340 341 mvebu_mbus_del_window(base, sz); 342 base += sz; 343 size -= sz; 344 } 345 } 346 347 /* 348 * MBus windows can only have a power of two size, but PCI BARs do not 349 * have this constraint. Therefore, we have to split the PCI BAR into 350 * areas each having a power of two size. We start from the largest 351 * one (i.e highest order bit set in the size). 352 */ 353 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, 354 unsigned int target, unsigned int attribute, 355 phys_addr_t base, size_t size, 356 phys_addr_t remap) 357 { 358 size_t size_mapped = 0; 359 360 while (size) { 361 size_t sz = 1 << (fls(size) - 1); 362 int ret; 363 364 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, 365 sz, remap); 366 if (ret) { 367 phys_addr_t end = base + sz - 1; 368 369 dev_err(&port->pcie->pdev->dev, 370 "Could not create MBus window at [mem %pa-%pa]: %d\n", 371 &base, &end, ret); 372 mvebu_pcie_del_windows(port, base - size_mapped, 373 size_mapped); 374 return; 375 } 376 377 size -= sz; 378 size_mapped += sz; 379 base += sz; 380 if (remap != MVEBU_MBUS_NO_REMAP) 381 remap += sz; 382 } 383 } 384 385 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port, 386 unsigned int target, unsigned int attribute, 387 const struct mvebu_pcie_window *desired, 388 struct mvebu_pcie_window *cur) 389 { 390 if (desired->base == cur->base && desired->remap == cur->remap && 391 desired->size == cur->size) 392 return; 393 394 if (cur->size != 0) { 395 mvebu_pcie_del_windows(port, cur->base, cur->size); 396 cur->size = 0; 397 cur->base = 0; 398 399 /* 400 * If something tries to change the window while it is enabled 401 * the change will not be done atomically. That would be 402 * difficult to do in the general case. 403 */ 404 } 405 406 if (desired->size == 0) 407 return; 408 409 mvebu_pcie_add_windows(port, target, attribute, desired->base, 410 desired->size, desired->remap); 411 *cur = *desired; 412 } 413 414 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 415 { 416 struct mvebu_pcie_window desired = {}; 417 418 /* Are the new iobase/iolimit values invalid? */ 419 if (port->bridge.iolimit < port->bridge.iobase || 420 port->bridge.iolimitupper < port->bridge.iobaseupper || 421 !(port->bridge.command & PCI_COMMAND_IO)) { 422 mvebu_pcie_set_window(port, port->io_target, port->io_attr, 423 &desired, &port->iowin); 424 return; 425 } 426 427 if (!mvebu_has_ioport(port)) { 428 dev_WARN(&port->pcie->pdev->dev, 429 "Attempt to set IO when IO is disabled\n"); 430 return; 431 } 432 433 /* 434 * We read the PCI-to-PCI bridge emulated registers, and 435 * calculate the base address and size of the address decoding 436 * window to setup, according to the PCI-to-PCI bridge 437 * specifications. iobase is the bus address, port->iowin_base 438 * is the CPU address. 439 */ 440 desired.remap = ((port->bridge.iobase & 0xF0) << 8) | 441 (port->bridge.iobaseupper << 16); 442 desired.base = port->pcie->io.start + desired.remap; 443 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 444 (port->bridge.iolimitupper << 16)) - 445 desired.remap) + 446 1; 447 448 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, 449 &port->iowin); 450 } 451 452 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 453 { 454 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; 455 456 /* Are the new membase/memlimit values invalid? */ 457 if (port->bridge.memlimit < port->bridge.membase || 458 !(port->bridge.command & PCI_COMMAND_MEMORY)) { 459 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, 460 &desired, &port->memwin); 461 return; 462 } 463 464 /* 465 * We read the PCI-to-PCI bridge emulated registers, and 466 * calculate the base address and size of the address decoding 467 * window to setup, according to the PCI-to-PCI bridge 468 * specifications. 469 */ 470 desired.base = ((port->bridge.membase & 0xFFF0) << 16); 471 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 472 desired.base + 1; 473 474 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, 475 &port->memwin); 476 } 477 478 /* 479 * Initialize the configuration space of the PCI-to-PCI bridge 480 * associated with the given PCIe interface. 481 */ 482 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) 483 { 484 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 485 486 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); 487 488 bridge->class = PCI_CLASS_BRIDGE_PCI; 489 bridge->vendor = PCI_VENDOR_ID_MARVELL; 490 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; 491 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; 492 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; 493 bridge->cache_line_size = 0x10; 494 495 /* We support 32 bits I/O addressing */ 496 bridge->iobase = PCI_IO_RANGE_TYPE_32; 497 bridge->iolimit = PCI_IO_RANGE_TYPE_32; 498 499 /* Add capabilities */ 500 bridge->status = PCI_STATUS_CAP_LIST; 501 } 502 503 /* 504 * Read the configuration space of the PCI-to-PCI bridge associated to 505 * the given PCIe interface. 506 */ 507 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, 508 unsigned int where, int size, u32 *value) 509 { 510 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 511 512 switch (where & ~3) { 513 case PCI_VENDOR_ID: 514 *value = bridge->device << 16 | bridge->vendor; 515 break; 516 517 case PCI_COMMAND: 518 *value = bridge->command | bridge->status << 16; 519 break; 520 521 case PCI_CLASS_REVISION: 522 *value = bridge->class << 16 | bridge->interface << 8 | 523 bridge->revision; 524 break; 525 526 case PCI_CACHE_LINE_SIZE: 527 *value = bridge->bist << 24 | bridge->header_type << 16 | 528 bridge->latency_timer << 8 | bridge->cache_line_size; 529 break; 530 531 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 532 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; 533 break; 534 535 case PCI_PRIMARY_BUS: 536 *value = (bridge->secondary_latency_timer << 24 | 537 bridge->subordinate_bus << 16 | 538 bridge->secondary_bus << 8 | 539 bridge->primary_bus); 540 break; 541 542 case PCI_IO_BASE: 543 if (!mvebu_has_ioport(port)) 544 *value = bridge->secondary_status << 16; 545 else 546 *value = (bridge->secondary_status << 16 | 547 bridge->iolimit << 8 | 548 bridge->iobase); 549 break; 550 551 case PCI_MEMORY_BASE: 552 *value = (bridge->memlimit << 16 | bridge->membase); 553 break; 554 555 case PCI_PREF_MEMORY_BASE: 556 *value = 0; 557 break; 558 559 case PCI_IO_BASE_UPPER16: 560 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); 561 break; 562 563 case PCI_CAPABILITY_LIST: 564 *value = PCISWCAP; 565 break; 566 567 case PCI_ROM_ADDRESS1: 568 *value = 0; 569 break; 570 571 case PCI_INTERRUPT_LINE: 572 /* LINE PIN MIN_GNT MAX_LAT */ 573 *value = 0; 574 break; 575 576 case PCISWCAP_EXP_LIST_ID: 577 /* Set PCIe v2, root port, slot support */ 578 *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | 579 PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP; 580 break; 581 582 case PCISWCAP_EXP_DEVCAP: 583 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); 584 break; 585 586 case PCISWCAP_EXP_DEVCTL: 587 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) & 588 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 589 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 590 *value |= bridge->pcie_devctl; 591 break; 592 593 case PCISWCAP_EXP_LNKCAP: 594 /* 595 * PCIe requires the clock power management capability to be 596 * hard-wired to zero for downstream ports 597 */ 598 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & 599 ~PCI_EXP_LNKCAP_CLKPM; 600 break; 601 602 case PCISWCAP_EXP_LNKCTL: 603 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 604 break; 605 606 case PCISWCAP_EXP_SLTCAP: 607 *value = bridge->pcie_sltcap; 608 break; 609 610 case PCISWCAP_EXP_SLTCTL: 611 *value = PCI_EXP_SLTSTA_PDS << 16; 612 break; 613 614 case PCISWCAP_EXP_RTCTL: 615 *value = bridge->pcie_rtctl; 616 break; 617 618 case PCISWCAP_EXP_RTSTA: 619 *value = mvebu_readl(port, PCIE_RC_RTSTA); 620 break; 621 622 /* PCIe requires the v2 fields to be hard-wired to zero */ 623 case PCISWCAP_EXP_DEVCAP2: 624 case PCISWCAP_EXP_DEVCTL2: 625 case PCISWCAP_EXP_LNKCAP2: 626 case PCISWCAP_EXP_LNKCTL2: 627 case PCISWCAP_EXP_SLTCAP2: 628 case PCISWCAP_EXP_SLTCTL2: 629 default: 630 /* 631 * PCI defines configuration read accesses to reserved or 632 * unimplemented registers to read as zero and complete 633 * normally. 634 */ 635 *value = 0; 636 return PCIBIOS_SUCCESSFUL; 637 } 638 639 if (size == 2) 640 *value = (*value >> (8 * (where & 3))) & 0xffff; 641 else if (size == 1) 642 *value = (*value >> (8 * (where & 3))) & 0xff; 643 644 return PCIBIOS_SUCCESSFUL; 645 } 646 647 /* Write to the PCI-to-PCI bridge configuration space */ 648 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, 649 unsigned int where, int size, u32 value) 650 { 651 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 652 u32 mask, reg; 653 int err; 654 655 if (size == 4) 656 mask = 0x0; 657 else if (size == 2) 658 mask = ~(0xffff << ((where & 3) * 8)); 659 else if (size == 1) 660 mask = ~(0xff << ((where & 3) * 8)); 661 else 662 return PCIBIOS_BAD_REGISTER_NUMBER; 663 664 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); 665 if (err) 666 return err; 667 668 value = (reg & mask) | value << ((where & 3) * 8); 669 670 switch (where & ~3) { 671 case PCI_COMMAND: 672 { 673 u32 old = bridge->command; 674 675 if (!mvebu_has_ioport(port)) 676 value &= ~PCI_COMMAND_IO; 677 678 bridge->command = value & 0xffff; 679 if ((old ^ bridge->command) & PCI_COMMAND_IO) 680 mvebu_pcie_handle_iobase_change(port); 681 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) 682 mvebu_pcie_handle_membase_change(port); 683 break; 684 } 685 686 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 687 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; 688 break; 689 690 case PCI_IO_BASE: 691 /* 692 * We also keep bit 1 set, it is a read-only bit that 693 * indicates we support 32 bits addressing for the 694 * I/O 695 */ 696 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; 697 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; 698 mvebu_pcie_handle_iobase_change(port); 699 break; 700 701 case PCI_MEMORY_BASE: 702 bridge->membase = value & 0xffff; 703 bridge->memlimit = value >> 16; 704 mvebu_pcie_handle_membase_change(port); 705 break; 706 707 case PCI_IO_BASE_UPPER16: 708 bridge->iobaseupper = value & 0xffff; 709 bridge->iolimitupper = value >> 16; 710 mvebu_pcie_handle_iobase_change(port); 711 break; 712 713 case PCI_PRIMARY_BUS: 714 bridge->primary_bus = value & 0xff; 715 bridge->secondary_bus = (value >> 8) & 0xff; 716 bridge->subordinate_bus = (value >> 16) & 0xff; 717 bridge->secondary_latency_timer = (value >> 24) & 0xff; 718 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); 719 break; 720 721 case PCISWCAP_EXP_DEVCTL: 722 /* 723 * Armada370 data says these bits must always 724 * be zero when in root complex mode. 725 */ 726 value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 727 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 728 729 /* 730 * If the mask is 0xffff0000, then we only want to write 731 * the device control register, rather than clearing the 732 * RW1C bits in the device status register. Mask out the 733 * status register bits. 734 */ 735 if (mask == 0xffff0000) 736 value &= 0xffff; 737 738 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 739 break; 740 741 case PCISWCAP_EXP_LNKCTL: 742 /* 743 * If we don't support CLKREQ, we must ensure that the 744 * CLKREQ enable bit always reads zero. Since we haven't 745 * had this capability, and it's dependent on board wiring, 746 * disable it for the time being. 747 */ 748 value &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 749 750 /* 751 * If the mask is 0xffff0000, then we only want to write 752 * the link control register, rather than clearing the 753 * RW1C bits in the link status register. Mask out the 754 * RW1C status register bits. 755 */ 756 if (mask == 0xffff0000) 757 value &= ~((PCI_EXP_LNKSTA_LABS | 758 PCI_EXP_LNKSTA_LBMS) << 16); 759 760 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 761 break; 762 763 case PCISWCAP_EXP_RTSTA: 764 mvebu_writel(port, value, PCIE_RC_RTSTA); 765 break; 766 767 default: 768 break; 769 } 770 771 return PCIBIOS_SUCCESSFUL; 772 } 773 774 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 775 { 776 return sys->private_data; 777 } 778 779 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 780 struct pci_bus *bus, 781 int devfn) 782 { 783 int i; 784 785 for (i = 0; i < pcie->nports; i++) { 786 struct mvebu_pcie_port *port = &pcie->ports[i]; 787 788 if (bus->number == 0 && port->devfn == devfn) 789 return port; 790 if (bus->number != 0 && 791 bus->number >= port->bridge.secondary_bus && 792 bus->number <= port->bridge.subordinate_bus) 793 return port; 794 } 795 796 return NULL; 797 } 798 799 /* PCI configuration space write function */ 800 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 801 int where, int size, u32 val) 802 { 803 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 804 struct mvebu_pcie_port *port; 805 int ret; 806 807 port = mvebu_pcie_find_port(pcie, bus, devfn); 808 if (!port) 809 return PCIBIOS_DEVICE_NOT_FOUND; 810 811 /* Access the emulated PCI-to-PCI bridge */ 812 if (bus->number == 0) 813 return mvebu_sw_pci_bridge_write(port, where, size, val); 814 815 if (!mvebu_pcie_link_up(port)) 816 return PCIBIOS_DEVICE_NOT_FOUND; 817 818 /* Access the real PCIe interface */ 819 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 820 where, size, val); 821 822 return ret; 823 } 824 825 /* PCI configuration space read function */ 826 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 827 int size, u32 *val) 828 { 829 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 830 struct mvebu_pcie_port *port; 831 int ret; 832 833 port = mvebu_pcie_find_port(pcie, bus, devfn); 834 if (!port) { 835 *val = 0xffffffff; 836 return PCIBIOS_DEVICE_NOT_FOUND; 837 } 838 839 /* Access the emulated PCI-to-PCI bridge */ 840 if (bus->number == 0) 841 return mvebu_sw_pci_bridge_read(port, where, size, val); 842 843 if (!mvebu_pcie_link_up(port)) { 844 *val = 0xffffffff; 845 return PCIBIOS_DEVICE_NOT_FOUND; 846 } 847 848 /* Access the real PCIe interface */ 849 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 850 where, size, val); 851 852 return ret; 853 } 854 855 static struct pci_ops mvebu_pcie_ops = { 856 .read = mvebu_pcie_rd_conf, 857 .write = mvebu_pcie_wr_conf, 858 }; 859 860 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) 861 { 862 struct mvebu_pcie *pcie = sys_to_pcie(sys); 863 int err, i; 864 865 pcie->mem.name = "PCI MEM"; 866 pcie->realio.name = "PCI I/O"; 867 868 if (resource_size(&pcie->realio) != 0) 869 pci_add_resource_offset(&sys->resources, &pcie->realio, 870 sys->io_offset); 871 872 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); 873 pci_add_resource(&sys->resources, &pcie->busn); 874 875 err = devm_request_pci_bus_resources(&pcie->pdev->dev, &sys->resources); 876 if (err) 877 return 0; 878 879 for (i = 0; i < pcie->nports; i++) { 880 struct mvebu_pcie_port *port = &pcie->ports[i]; 881 882 if (!port->base) 883 continue; 884 mvebu_pcie_setup_hw(port); 885 } 886 887 return 1; 888 } 889 890 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 891 const struct resource *res, 892 resource_size_t start, 893 resource_size_t size, 894 resource_size_t align) 895 { 896 if (dev->bus->number != 0) 897 return start; 898 899 /* 900 * On the PCI-to-PCI bridge side, the I/O windows must have at 901 * least a 64 KB size and the memory windows must have at 902 * least a 1 MB size. Moreover, MBus windows need to have a 903 * base address aligned on their size, and their size must be 904 * a power of two. This means that if the BAR doesn't have a 905 * power of two size, several MBus windows will actually be 906 * created. We need to ensure that the biggest MBus window 907 * (which will be the first one) is aligned on its size, which 908 * explains the rounddown_pow_of_two() being done here. 909 */ 910 if (res->flags & IORESOURCE_IO) 911 return round_up(start, max_t(resource_size_t, SZ_64K, 912 rounddown_pow_of_two(size))); 913 else if (res->flags & IORESOURCE_MEM) 914 return round_up(start, max_t(resource_size_t, SZ_1M, 915 rounddown_pow_of_two(size))); 916 else 917 return start; 918 } 919 920 static void mvebu_pcie_enable(struct mvebu_pcie *pcie) 921 { 922 struct hw_pci hw; 923 924 memset(&hw, 0, sizeof(hw)); 925 926 #ifdef CONFIG_PCI_MSI 927 hw.msi_ctrl = pcie->msi; 928 #endif 929 930 hw.nr_controllers = 1; 931 hw.private_data = (void **)&pcie; 932 hw.setup = mvebu_pcie_setup; 933 hw.map_irq = of_irq_parse_and_map_pci; 934 hw.ops = &mvebu_pcie_ops; 935 hw.align_resource = mvebu_pcie_align_resource; 936 937 pci_common_init_dev(&pcie->pdev->dev, &hw); 938 } 939 940 /* 941 * Looks up the list of register addresses encoded into the reg = 942 * <...> property for one that matches the given port/lane. Once 943 * found, maps it. 944 */ 945 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 946 struct device_node *np, 947 struct mvebu_pcie_port *port) 948 { 949 struct resource regs; 950 int ret = 0; 951 952 ret = of_address_to_resource(np, 0, ®s); 953 if (ret) 954 return ERR_PTR(ret); 955 956 return devm_ioremap_resource(&pdev->dev, ®s); 957 } 958 959 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 960 #define DT_TYPE_IO 0x1 961 #define DT_TYPE_MEM32 0x2 962 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 963 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 964 965 static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 966 unsigned long type, 967 unsigned int *tgt, 968 unsigned int *attr) 969 { 970 const int na = 3, ns = 2; 971 const __be32 *range; 972 int rlen, nranges, rangesz, pna, i; 973 974 *tgt = -1; 975 *attr = -1; 976 977 range = of_get_property(np, "ranges", &rlen); 978 if (!range) 979 return -EINVAL; 980 981 pna = of_n_addr_cells(np); 982 rangesz = pna + na + ns; 983 nranges = rlen / sizeof(__be32) / rangesz; 984 985 for (i = 0; i < nranges; i++, range += rangesz) { 986 u32 flags = of_read_number(range, 1); 987 u32 slot = of_read_number(range + 1, 1); 988 u64 cpuaddr = of_read_number(range + na, pna); 989 unsigned long rtype; 990 991 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 992 rtype = IORESOURCE_IO; 993 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 994 rtype = IORESOURCE_MEM; 995 else 996 continue; 997 998 if (slot == PCI_SLOT(devfn) && type == rtype) { 999 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 1000 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 1001 return 0; 1002 } 1003 } 1004 1005 return -ENOENT; 1006 } 1007 1008 #ifdef CONFIG_PM_SLEEP 1009 static int mvebu_pcie_suspend(struct device *dev) 1010 { 1011 struct mvebu_pcie *pcie; 1012 int i; 1013 1014 pcie = dev_get_drvdata(dev); 1015 for (i = 0; i < pcie->nports; i++) { 1016 struct mvebu_pcie_port *port = pcie->ports + i; 1017 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static int mvebu_pcie_resume(struct device *dev) 1024 { 1025 struct mvebu_pcie *pcie; 1026 int i; 1027 1028 pcie = dev_get_drvdata(dev); 1029 for (i = 0; i < pcie->nports; i++) { 1030 struct mvebu_pcie_port *port = pcie->ports + i; 1031 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); 1032 mvebu_pcie_setup_hw(port); 1033 } 1034 1035 return 0; 1036 } 1037 #endif 1038 1039 static void mvebu_pcie_port_clk_put(void *data) 1040 { 1041 struct mvebu_pcie_port *port = data; 1042 1043 clk_put(port->clk); 1044 } 1045 1046 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, 1047 struct mvebu_pcie_port *port, struct device_node *child) 1048 { 1049 struct device *dev = &pcie->pdev->dev; 1050 enum of_gpio_flags flags; 1051 int reset_gpio, ret; 1052 1053 port->pcie = pcie; 1054 1055 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { 1056 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", 1057 child); 1058 goto skip; 1059 } 1060 1061 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) 1062 port->lane = 0; 1063 1064 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, 1065 port->lane); 1066 if (!port->name) { 1067 ret = -ENOMEM; 1068 goto err; 1069 } 1070 1071 port->devfn = of_pci_get_devfn(child); 1072 if (port->devfn < 0) 1073 goto skip; 1074 1075 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, 1076 &port->mem_target, &port->mem_attr); 1077 if (ret < 0) { 1078 dev_err(dev, "%s: cannot get tgt/attr for mem window\n", 1079 port->name); 1080 goto skip; 1081 } 1082 1083 if (resource_size(&pcie->io) != 0) { 1084 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, 1085 &port->io_target, &port->io_attr); 1086 } else { 1087 port->io_target = -1; 1088 port->io_attr = -1; 1089 } 1090 1091 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); 1092 if (reset_gpio == -EPROBE_DEFER) { 1093 ret = reset_gpio; 1094 goto err; 1095 } 1096 1097 if (gpio_is_valid(reset_gpio)) { 1098 unsigned long gpio_flags; 1099 1100 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", 1101 port->name); 1102 if (!port->reset_name) { 1103 ret = -ENOMEM; 1104 goto err; 1105 } 1106 1107 if (flags & OF_GPIO_ACTIVE_LOW) { 1108 dev_info(dev, "%pOF: reset gpio is active low\n", 1109 child); 1110 gpio_flags = GPIOF_ACTIVE_LOW | 1111 GPIOF_OUT_INIT_LOW; 1112 } else { 1113 gpio_flags = GPIOF_OUT_INIT_HIGH; 1114 } 1115 1116 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags, 1117 port->reset_name); 1118 if (ret) { 1119 if (ret == -EPROBE_DEFER) 1120 goto err; 1121 goto skip; 1122 } 1123 1124 port->reset_gpio = gpio_to_desc(reset_gpio); 1125 } 1126 1127 port->clk = of_clk_get_by_name(child, NULL); 1128 if (IS_ERR(port->clk)) { 1129 dev_err(dev, "%s: cannot get clock\n", port->name); 1130 goto skip; 1131 } 1132 1133 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port); 1134 if (ret < 0) { 1135 clk_put(port->clk); 1136 goto err; 1137 } 1138 1139 return 1; 1140 1141 skip: 1142 ret = 0; 1143 1144 /* In the case of skipping, we need to free these */ 1145 devm_kfree(dev, port->reset_name); 1146 port->reset_name = NULL; 1147 devm_kfree(dev, port->name); 1148 port->name = NULL; 1149 1150 err: 1151 return ret; 1152 } 1153 1154 /* 1155 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs 1156 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications 1157 * of the PCI Express Card Electromechanical Specification, 1.1. 1158 */ 1159 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) 1160 { 1161 int ret; 1162 1163 ret = clk_prepare_enable(port->clk); 1164 if (ret < 0) 1165 return ret; 1166 1167 if (port->reset_gpio) { 1168 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; 1169 1170 of_property_read_u32(port->dn, "reset-delay-us", 1171 &reset_udelay); 1172 1173 udelay(100); 1174 1175 gpiod_set_value_cansleep(port->reset_gpio, 0); 1176 msleep(reset_udelay / 1000); 1177 } 1178 1179 return 0; 1180 } 1181 1182 /* 1183 * Power down a PCIe port. Strictly, PCIe requires us to place the card 1184 * in D3hot state before asserting PERST#. 1185 */ 1186 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port) 1187 { 1188 gpiod_set_value_cansleep(port->reset_gpio, 1); 1189 1190 clk_disable_unprepare(port->clk); 1191 } 1192 1193 static int mvebu_pcie_probe(struct platform_device *pdev) 1194 { 1195 struct device *dev = &pdev->dev; 1196 struct mvebu_pcie *pcie; 1197 struct device_node *np = dev->of_node; 1198 struct device_node *child; 1199 int num, i, ret; 1200 1201 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1202 if (!pcie) 1203 return -ENOMEM; 1204 1205 pcie->pdev = pdev; 1206 platform_set_drvdata(pdev, pcie); 1207 1208 /* Get the PCIe memory and I/O aperture */ 1209 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 1210 if (resource_size(&pcie->mem) == 0) { 1211 dev_err(dev, "invalid memory aperture size\n"); 1212 return -EINVAL; 1213 } 1214 1215 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 1216 1217 if (resource_size(&pcie->io) != 0) { 1218 pcie->realio.flags = pcie->io.flags; 1219 pcie->realio.start = PCIBIOS_MIN_IO; 1220 pcie->realio.end = min_t(resource_size_t, 1221 IO_SPACE_LIMIT, 1222 resource_size(&pcie->io)); 1223 } else 1224 pcie->realio = pcie->io; 1225 1226 /* Get the bus range */ 1227 ret = of_pci_parse_bus_range(np, &pcie->busn); 1228 if (ret) { 1229 dev_err(dev, "failed to parse bus-range property: %d\n", ret); 1230 return ret; 1231 } 1232 1233 num = of_get_available_child_count(np); 1234 1235 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); 1236 if (!pcie->ports) 1237 return -ENOMEM; 1238 1239 i = 0; 1240 for_each_available_child_of_node(np, child) { 1241 struct mvebu_pcie_port *port = &pcie->ports[i]; 1242 1243 ret = mvebu_pcie_parse_port(pcie, port, child); 1244 if (ret < 0) { 1245 of_node_put(child); 1246 return ret; 1247 } else if (ret == 0) { 1248 continue; 1249 } 1250 1251 port->dn = child; 1252 i++; 1253 } 1254 pcie->nports = i; 1255 1256 for (i = 0; i < pcie->nports; i++) { 1257 struct mvebu_pcie_port *port = &pcie->ports[i]; 1258 1259 child = port->dn; 1260 if (!child) 1261 continue; 1262 1263 ret = mvebu_pcie_powerup(port); 1264 if (ret < 0) 1265 continue; 1266 1267 port->base = mvebu_pcie_map_registers(pdev, child, port); 1268 if (IS_ERR(port->base)) { 1269 dev_err(dev, "%s: cannot map registers\n", port->name); 1270 port->base = NULL; 1271 mvebu_pcie_powerdown(port); 1272 continue; 1273 } 1274 1275 mvebu_pcie_set_local_dev_nr(port, 1); 1276 mvebu_sw_pci_bridge_init(port); 1277 } 1278 1279 pcie->nports = i; 1280 1281 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K) 1282 pci_ioremap_io(i, pcie->io.start + i); 1283 1284 mvebu_pcie_enable(pcie); 1285 1286 platform_set_drvdata(pdev, pcie); 1287 1288 return 0; 1289 } 1290 1291 static const struct of_device_id mvebu_pcie_of_match_table[] = { 1292 { .compatible = "marvell,armada-xp-pcie", }, 1293 { .compatible = "marvell,armada-370-pcie", }, 1294 { .compatible = "marvell,dove-pcie", }, 1295 { .compatible = "marvell,kirkwood-pcie", }, 1296 {}, 1297 }; 1298 1299 static const struct dev_pm_ops mvebu_pcie_pm_ops = { 1300 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume) 1301 }; 1302 1303 static struct platform_driver mvebu_pcie_driver = { 1304 .driver = { 1305 .name = "mvebu-pcie", 1306 .of_match_table = mvebu_pcie_of_match_table, 1307 /* driver unloading/unbinding currently not supported */ 1308 .suppress_bind_attrs = true, 1309 .pm = &mvebu_pcie_pm_ops, 1310 }, 1311 .probe = mvebu_pcie_probe, 1312 }; 1313 builtin_platform_driver(mvebu_pcie_driver); 1314