1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio.h> 13 #include <linux/init.h> 14 #include <linux/mbus.h> 15 #include <linux/msi.h> 16 #include <linux/slab.h> 17 #include <linux/platform_device.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_pci.h> 22 #include <linux/of_platform.h> 23 24 #include "../pci.h" 25 26 /* 27 * PCIe unit register offsets. 28 */ 29 #define PCIE_DEV_ID_OFF 0x0000 30 #define PCIE_CMD_OFF 0x0004 31 #define PCIE_DEV_REV_OFF 0x0008 32 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 33 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 34 #define PCIE_CAP_PCIEXP 0x0060 35 #define PCIE_HEADER_LOG_4_OFF 0x0128 36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 37 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 38 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 39 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 40 #define PCIE_WIN5_CTRL_OFF 0x1880 41 #define PCIE_WIN5_BASE_OFF 0x1884 42 #define PCIE_WIN5_REMAP_OFF 0x188c 43 #define PCIE_CONF_ADDR_OFF 0x18f8 44 #define PCIE_CONF_ADDR_EN 0x80000000 45 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 46 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 47 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 48 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 49 #define PCIE_CONF_ADDR(bus, devfn, where) \ 50 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 51 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 52 PCIE_CONF_ADDR_EN) 53 #define PCIE_CONF_DATA_OFF 0x18fc 54 #define PCIE_MASK_OFF 0x1910 55 #define PCIE_MASK_ENABLE_INTS 0x0f000000 56 #define PCIE_CTRL_OFF 0x1a00 57 #define PCIE_CTRL_X1_MODE 0x0001 58 #define PCIE_STAT_OFF 0x1a04 59 #define PCIE_STAT_BUS 0xff00 60 #define PCIE_STAT_DEV 0x1f0000 61 #define PCIE_STAT_LINK_DOWN BIT(0) 62 #define PCIE_RC_RTSTA 0x1a14 63 #define PCIE_DEBUG_CTRL 0x1a60 64 #define PCIE_DEBUG_SOFT_RESET BIT(20) 65 66 enum { 67 PCISWCAP = PCI_BRIDGE_CONTROL + 2, 68 PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID, 69 PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP, 70 PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL, 71 PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP, 72 PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL, 73 PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP, 74 PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL, 75 PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL, 76 PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA, 77 PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2, 78 PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2, 79 PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2, 80 PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2, 81 PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2, 82 PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2, 83 }; 84 85 /* PCI configuration space of a PCI-to-PCI bridge */ 86 struct mvebu_sw_pci_bridge { 87 u16 vendor; 88 u16 device; 89 u16 command; 90 u16 status; 91 u16 class; 92 u8 interface; 93 u8 revision; 94 u8 bist; 95 u8 header_type; 96 u8 latency_timer; 97 u8 cache_line_size; 98 u32 bar[2]; 99 u8 primary_bus; 100 u8 secondary_bus; 101 u8 subordinate_bus; 102 u8 secondary_latency_timer; 103 u8 iobase; 104 u8 iolimit; 105 u16 secondary_status; 106 u16 membase; 107 u16 memlimit; 108 u16 iobaseupper; 109 u16 iolimitupper; 110 u32 romaddr; 111 u8 intline; 112 u8 intpin; 113 u16 bridgectrl; 114 115 /* PCI express capability */ 116 u32 pcie_sltcap; 117 u16 pcie_devctl; 118 u16 pcie_rtctl; 119 }; 120 121 struct mvebu_pcie_port; 122 123 /* Structure representing all PCIe interfaces */ 124 struct mvebu_pcie { 125 struct platform_device *pdev; 126 struct mvebu_pcie_port *ports; 127 struct msi_controller *msi; 128 struct list_head resources; 129 struct resource io; 130 struct resource realio; 131 struct resource mem; 132 struct resource busn; 133 int nports; 134 }; 135 136 struct mvebu_pcie_window { 137 phys_addr_t base; 138 phys_addr_t remap; 139 size_t size; 140 }; 141 142 /* Structure representing one PCIe interface */ 143 struct mvebu_pcie_port { 144 char *name; 145 void __iomem *base; 146 u32 port; 147 u32 lane; 148 int devfn; 149 unsigned int mem_target; 150 unsigned int mem_attr; 151 unsigned int io_target; 152 unsigned int io_attr; 153 struct clk *clk; 154 struct gpio_desc *reset_gpio; 155 char *reset_name; 156 struct mvebu_sw_pci_bridge bridge; 157 struct device_node *dn; 158 struct mvebu_pcie *pcie; 159 struct mvebu_pcie_window memwin; 160 struct mvebu_pcie_window iowin; 161 u32 saved_pcie_stat; 162 }; 163 164 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 165 { 166 writel(val, port->base + reg); 167 } 168 169 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 170 { 171 return readl(port->base + reg); 172 } 173 174 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 175 { 176 return port->io_target != -1 && port->io_attr != -1; 177 } 178 179 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 180 { 181 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 182 } 183 184 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 185 { 186 u32 stat; 187 188 stat = mvebu_readl(port, PCIE_STAT_OFF); 189 stat &= ~PCIE_STAT_BUS; 190 stat |= nr << 8; 191 mvebu_writel(port, stat, PCIE_STAT_OFF); 192 } 193 194 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 195 { 196 u32 stat; 197 198 stat = mvebu_readl(port, PCIE_STAT_OFF); 199 stat &= ~PCIE_STAT_DEV; 200 stat |= nr << 16; 201 mvebu_writel(port, stat, PCIE_STAT_OFF); 202 } 203 204 /* 205 * Setup PCIE BARs and Address Decode Wins: 206 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 207 * WIN[0-3] -> DRAM bank[0-3] 208 */ 209 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 210 { 211 const struct mbus_dram_target_info *dram; 212 u32 size; 213 int i; 214 215 dram = mv_mbus_dram_info(); 216 217 /* First, disable and clear BARs and windows. */ 218 for (i = 1; i < 3; i++) { 219 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 220 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 221 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 222 } 223 224 for (i = 0; i < 5; i++) { 225 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 226 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 227 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 228 } 229 230 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 231 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 232 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 233 234 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 235 size = 0; 236 for (i = 0; i < dram->num_cs; i++) { 237 const struct mbus_dram_window *cs = dram->cs + i; 238 239 mvebu_writel(port, cs->base & 0xffff0000, 240 PCIE_WIN04_BASE_OFF(i)); 241 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 242 mvebu_writel(port, 243 ((cs->size - 1) & 0xffff0000) | 244 (cs->mbus_attr << 8) | 245 (dram->mbus_dram_target_id << 4) | 1, 246 PCIE_WIN04_CTRL_OFF(i)); 247 248 size += cs->size; 249 } 250 251 /* Round up 'size' to the nearest power of two. */ 252 if ((size & (size - 1)) != 0) 253 size = 1 << fls(size); 254 255 /* Setup BAR[1] to all DRAM banks. */ 256 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 257 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 258 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 259 PCIE_BAR_CTRL_OFF(1)); 260 } 261 262 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 263 { 264 u32 cmd, mask; 265 266 /* Point PCIe unit MBUS decode windows to DRAM space. */ 267 mvebu_pcie_setup_wins(port); 268 269 /* Master + slave enable. */ 270 cmd = mvebu_readl(port, PCIE_CMD_OFF); 271 cmd |= PCI_COMMAND_IO; 272 cmd |= PCI_COMMAND_MEMORY; 273 cmd |= PCI_COMMAND_MASTER; 274 mvebu_writel(port, cmd, PCIE_CMD_OFF); 275 276 /* Enable interrupt lines A-D. */ 277 mask = mvebu_readl(port, PCIE_MASK_OFF); 278 mask |= PCIE_MASK_ENABLE_INTS; 279 mvebu_writel(port, mask, PCIE_MASK_OFF); 280 } 281 282 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, 283 struct pci_bus *bus, 284 u32 devfn, int where, int size, u32 *val) 285 { 286 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 287 288 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 289 PCIE_CONF_ADDR_OFF); 290 291 switch (size) { 292 case 1: 293 *val = readb_relaxed(conf_data + (where & 3)); 294 break; 295 case 2: 296 *val = readw_relaxed(conf_data + (where & 2)); 297 break; 298 case 4: 299 *val = readl_relaxed(conf_data); 300 break; 301 } 302 303 return PCIBIOS_SUCCESSFUL; 304 } 305 306 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, 307 struct pci_bus *bus, 308 u32 devfn, int where, int size, u32 val) 309 { 310 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; 311 312 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 313 PCIE_CONF_ADDR_OFF); 314 315 switch (size) { 316 case 1: 317 writeb(val, conf_data + (where & 3)); 318 break; 319 case 2: 320 writew(val, conf_data + (where & 2)); 321 break; 322 case 4: 323 writel(val, conf_data); 324 break; 325 default: 326 return PCIBIOS_BAD_REGISTER_NUMBER; 327 } 328 329 return PCIBIOS_SUCCESSFUL; 330 } 331 332 /* 333 * Remove windows, starting from the largest ones to the smallest 334 * ones. 335 */ 336 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, 337 phys_addr_t base, size_t size) 338 { 339 while (size) { 340 size_t sz = 1 << (fls(size) - 1); 341 342 mvebu_mbus_del_window(base, sz); 343 base += sz; 344 size -= sz; 345 } 346 } 347 348 /* 349 * MBus windows can only have a power of two size, but PCI BARs do not 350 * have this constraint. Therefore, we have to split the PCI BAR into 351 * areas each having a power of two size. We start from the largest 352 * one (i.e highest order bit set in the size). 353 */ 354 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, 355 unsigned int target, unsigned int attribute, 356 phys_addr_t base, size_t size, 357 phys_addr_t remap) 358 { 359 size_t size_mapped = 0; 360 361 while (size) { 362 size_t sz = 1 << (fls(size) - 1); 363 int ret; 364 365 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, 366 sz, remap); 367 if (ret) { 368 phys_addr_t end = base + sz - 1; 369 370 dev_err(&port->pcie->pdev->dev, 371 "Could not create MBus window at [mem %pa-%pa]: %d\n", 372 &base, &end, ret); 373 mvebu_pcie_del_windows(port, base - size_mapped, 374 size_mapped); 375 return; 376 } 377 378 size -= sz; 379 size_mapped += sz; 380 base += sz; 381 if (remap != MVEBU_MBUS_NO_REMAP) 382 remap += sz; 383 } 384 } 385 386 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port, 387 unsigned int target, unsigned int attribute, 388 const struct mvebu_pcie_window *desired, 389 struct mvebu_pcie_window *cur) 390 { 391 if (desired->base == cur->base && desired->remap == cur->remap && 392 desired->size == cur->size) 393 return; 394 395 if (cur->size != 0) { 396 mvebu_pcie_del_windows(port, cur->base, cur->size); 397 cur->size = 0; 398 cur->base = 0; 399 400 /* 401 * If something tries to change the window while it is enabled 402 * the change will not be done atomically. That would be 403 * difficult to do in the general case. 404 */ 405 } 406 407 if (desired->size == 0) 408 return; 409 410 mvebu_pcie_add_windows(port, target, attribute, desired->base, 411 desired->size, desired->remap); 412 *cur = *desired; 413 } 414 415 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 416 { 417 struct mvebu_pcie_window desired = {}; 418 419 /* Are the new iobase/iolimit values invalid? */ 420 if (port->bridge.iolimit < port->bridge.iobase || 421 port->bridge.iolimitupper < port->bridge.iobaseupper || 422 !(port->bridge.command & PCI_COMMAND_IO)) { 423 mvebu_pcie_set_window(port, port->io_target, port->io_attr, 424 &desired, &port->iowin); 425 return; 426 } 427 428 if (!mvebu_has_ioport(port)) { 429 dev_WARN(&port->pcie->pdev->dev, 430 "Attempt to set IO when IO is disabled\n"); 431 return; 432 } 433 434 /* 435 * We read the PCI-to-PCI bridge emulated registers, and 436 * calculate the base address and size of the address decoding 437 * window to setup, according to the PCI-to-PCI bridge 438 * specifications. iobase is the bus address, port->iowin_base 439 * is the CPU address. 440 */ 441 desired.remap = ((port->bridge.iobase & 0xF0) << 8) | 442 (port->bridge.iobaseupper << 16); 443 desired.base = port->pcie->io.start + desired.remap; 444 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 445 (port->bridge.iolimitupper << 16)) - 446 desired.remap) + 447 1; 448 449 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, 450 &port->iowin); 451 } 452 453 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 454 { 455 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; 456 457 /* Are the new membase/memlimit values invalid? */ 458 if (port->bridge.memlimit < port->bridge.membase || 459 !(port->bridge.command & PCI_COMMAND_MEMORY)) { 460 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, 461 &desired, &port->memwin); 462 return; 463 } 464 465 /* 466 * We read the PCI-to-PCI bridge emulated registers, and 467 * calculate the base address and size of the address decoding 468 * window to setup, according to the PCI-to-PCI bridge 469 * specifications. 470 */ 471 desired.base = ((port->bridge.membase & 0xFFF0) << 16); 472 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 473 desired.base + 1; 474 475 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, 476 &port->memwin); 477 } 478 479 /* 480 * Initialize the configuration space of the PCI-to-PCI bridge 481 * associated with the given PCIe interface. 482 */ 483 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) 484 { 485 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 486 487 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); 488 489 bridge->class = PCI_CLASS_BRIDGE_PCI; 490 bridge->vendor = PCI_VENDOR_ID_MARVELL; 491 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; 492 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; 493 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; 494 bridge->cache_line_size = 0x10; 495 496 /* We support 32 bits I/O addressing */ 497 bridge->iobase = PCI_IO_RANGE_TYPE_32; 498 bridge->iolimit = PCI_IO_RANGE_TYPE_32; 499 500 /* Add capabilities */ 501 bridge->status = PCI_STATUS_CAP_LIST; 502 } 503 504 /* 505 * Read the configuration space of the PCI-to-PCI bridge associated to 506 * the given PCIe interface. 507 */ 508 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, 509 unsigned int where, int size, u32 *value) 510 { 511 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 512 513 switch (where & ~3) { 514 case PCI_VENDOR_ID: 515 *value = bridge->device << 16 | bridge->vendor; 516 break; 517 518 case PCI_COMMAND: 519 *value = bridge->command | bridge->status << 16; 520 break; 521 522 case PCI_CLASS_REVISION: 523 *value = bridge->class << 16 | bridge->interface << 8 | 524 bridge->revision; 525 break; 526 527 case PCI_CACHE_LINE_SIZE: 528 *value = bridge->bist << 24 | bridge->header_type << 16 | 529 bridge->latency_timer << 8 | bridge->cache_line_size; 530 break; 531 532 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 533 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; 534 break; 535 536 case PCI_PRIMARY_BUS: 537 *value = (bridge->secondary_latency_timer << 24 | 538 bridge->subordinate_bus << 16 | 539 bridge->secondary_bus << 8 | 540 bridge->primary_bus); 541 break; 542 543 case PCI_IO_BASE: 544 if (!mvebu_has_ioport(port)) 545 *value = bridge->secondary_status << 16; 546 else 547 *value = (bridge->secondary_status << 16 | 548 bridge->iolimit << 8 | 549 bridge->iobase); 550 break; 551 552 case PCI_MEMORY_BASE: 553 *value = (bridge->memlimit << 16 | bridge->membase); 554 break; 555 556 case PCI_PREF_MEMORY_BASE: 557 *value = 0; 558 break; 559 560 case PCI_IO_BASE_UPPER16: 561 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); 562 break; 563 564 case PCI_CAPABILITY_LIST: 565 *value = PCISWCAP; 566 break; 567 568 case PCI_ROM_ADDRESS1: 569 *value = 0; 570 break; 571 572 case PCI_INTERRUPT_LINE: 573 /* LINE PIN MIN_GNT MAX_LAT */ 574 *value = 0; 575 break; 576 577 case PCISWCAP_EXP_LIST_ID: 578 /* Set PCIe v2, root port, slot support */ 579 *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | 580 PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP; 581 break; 582 583 case PCISWCAP_EXP_DEVCAP: 584 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); 585 break; 586 587 case PCISWCAP_EXP_DEVCTL: 588 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) & 589 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 590 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 591 *value |= bridge->pcie_devctl; 592 break; 593 594 case PCISWCAP_EXP_LNKCAP: 595 /* 596 * PCIe requires the clock power management capability to be 597 * hard-wired to zero for downstream ports 598 */ 599 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & 600 ~PCI_EXP_LNKCAP_CLKPM; 601 break; 602 603 case PCISWCAP_EXP_LNKCTL: 604 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 605 break; 606 607 case PCISWCAP_EXP_SLTCAP: 608 *value = bridge->pcie_sltcap; 609 break; 610 611 case PCISWCAP_EXP_SLTCTL: 612 *value = PCI_EXP_SLTSTA_PDS << 16; 613 break; 614 615 case PCISWCAP_EXP_RTCTL: 616 *value = bridge->pcie_rtctl; 617 break; 618 619 case PCISWCAP_EXP_RTSTA: 620 *value = mvebu_readl(port, PCIE_RC_RTSTA); 621 break; 622 623 /* PCIe requires the v2 fields to be hard-wired to zero */ 624 case PCISWCAP_EXP_DEVCAP2: 625 case PCISWCAP_EXP_DEVCTL2: 626 case PCISWCAP_EXP_LNKCAP2: 627 case PCISWCAP_EXP_LNKCTL2: 628 case PCISWCAP_EXP_SLTCAP2: 629 case PCISWCAP_EXP_SLTCTL2: 630 default: 631 /* 632 * PCI defines configuration read accesses to reserved or 633 * unimplemented registers to read as zero and complete 634 * normally. 635 */ 636 *value = 0; 637 return PCIBIOS_SUCCESSFUL; 638 } 639 640 if (size == 2) 641 *value = (*value >> (8 * (where & 3))) & 0xffff; 642 else if (size == 1) 643 *value = (*value >> (8 * (where & 3))) & 0xff; 644 645 return PCIBIOS_SUCCESSFUL; 646 } 647 648 /* Write to the PCI-to-PCI bridge configuration space */ 649 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, 650 unsigned int where, int size, u32 value) 651 { 652 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 653 u32 mask, reg; 654 int err; 655 656 if (size == 4) 657 mask = 0x0; 658 else if (size == 2) 659 mask = ~(0xffff << ((where & 3) * 8)); 660 else if (size == 1) 661 mask = ~(0xff << ((where & 3) * 8)); 662 else 663 return PCIBIOS_BAD_REGISTER_NUMBER; 664 665 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); 666 if (err) 667 return err; 668 669 value = (reg & mask) | value << ((where & 3) * 8); 670 671 switch (where & ~3) { 672 case PCI_COMMAND: 673 { 674 u32 old = bridge->command; 675 676 if (!mvebu_has_ioport(port)) 677 value &= ~PCI_COMMAND_IO; 678 679 bridge->command = value & 0xffff; 680 if ((old ^ bridge->command) & PCI_COMMAND_IO) 681 mvebu_pcie_handle_iobase_change(port); 682 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) 683 mvebu_pcie_handle_membase_change(port); 684 break; 685 } 686 687 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 688 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; 689 break; 690 691 case PCI_IO_BASE: 692 /* 693 * We also keep bit 1 set, it is a read-only bit that 694 * indicates we support 32 bits addressing for the 695 * I/O 696 */ 697 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; 698 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; 699 mvebu_pcie_handle_iobase_change(port); 700 break; 701 702 case PCI_MEMORY_BASE: 703 bridge->membase = value & 0xffff; 704 bridge->memlimit = value >> 16; 705 mvebu_pcie_handle_membase_change(port); 706 break; 707 708 case PCI_IO_BASE_UPPER16: 709 bridge->iobaseupper = value & 0xffff; 710 bridge->iolimitupper = value >> 16; 711 mvebu_pcie_handle_iobase_change(port); 712 break; 713 714 case PCI_PRIMARY_BUS: 715 bridge->primary_bus = value & 0xff; 716 bridge->secondary_bus = (value >> 8) & 0xff; 717 bridge->subordinate_bus = (value >> 16) & 0xff; 718 bridge->secondary_latency_timer = (value >> 24) & 0xff; 719 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); 720 break; 721 722 case PCISWCAP_EXP_DEVCTL: 723 /* 724 * Armada370 data says these bits must always 725 * be zero when in root complex mode. 726 */ 727 value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 728 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 729 730 /* 731 * If the mask is 0xffff0000, then we only want to write 732 * the device control register, rather than clearing the 733 * RW1C bits in the device status register. Mask out the 734 * status register bits. 735 */ 736 if (mask == 0xffff0000) 737 value &= 0xffff; 738 739 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 740 break; 741 742 case PCISWCAP_EXP_LNKCTL: 743 /* 744 * If we don't support CLKREQ, we must ensure that the 745 * CLKREQ enable bit always reads zero. Since we haven't 746 * had this capability, and it's dependent on board wiring, 747 * disable it for the time being. 748 */ 749 value &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 750 751 /* 752 * If the mask is 0xffff0000, then we only want to write 753 * the link control register, rather than clearing the 754 * RW1C bits in the link status register. Mask out the 755 * RW1C status register bits. 756 */ 757 if (mask == 0xffff0000) 758 value &= ~((PCI_EXP_LNKSTA_LABS | 759 PCI_EXP_LNKSTA_LBMS) << 16); 760 761 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 762 break; 763 764 case PCISWCAP_EXP_RTSTA: 765 mvebu_writel(port, value, PCIE_RC_RTSTA); 766 break; 767 768 default: 769 break; 770 } 771 772 return PCIBIOS_SUCCESSFUL; 773 } 774 775 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 776 { 777 return sys->private_data; 778 } 779 780 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 781 struct pci_bus *bus, 782 int devfn) 783 { 784 int i; 785 786 for (i = 0; i < pcie->nports; i++) { 787 struct mvebu_pcie_port *port = &pcie->ports[i]; 788 789 if (bus->number == 0 && port->devfn == devfn) 790 return port; 791 if (bus->number != 0 && 792 bus->number >= port->bridge.secondary_bus && 793 bus->number <= port->bridge.subordinate_bus) 794 return port; 795 } 796 797 return NULL; 798 } 799 800 /* PCI configuration space write function */ 801 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 802 int where, int size, u32 val) 803 { 804 struct mvebu_pcie *pcie = bus->sysdata; 805 struct mvebu_pcie_port *port; 806 int ret; 807 808 port = mvebu_pcie_find_port(pcie, bus, devfn); 809 if (!port) 810 return PCIBIOS_DEVICE_NOT_FOUND; 811 812 /* Access the emulated PCI-to-PCI bridge */ 813 if (bus->number == 0) 814 return mvebu_sw_pci_bridge_write(port, where, size, val); 815 816 if (!mvebu_pcie_link_up(port)) 817 return PCIBIOS_DEVICE_NOT_FOUND; 818 819 /* Access the real PCIe interface */ 820 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 821 where, size, val); 822 823 return ret; 824 } 825 826 /* PCI configuration space read function */ 827 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 828 int size, u32 *val) 829 { 830 struct mvebu_pcie *pcie = bus->sysdata; 831 struct mvebu_pcie_port *port; 832 int ret; 833 834 port = mvebu_pcie_find_port(pcie, bus, devfn); 835 if (!port) { 836 *val = 0xffffffff; 837 return PCIBIOS_DEVICE_NOT_FOUND; 838 } 839 840 /* Access the emulated PCI-to-PCI bridge */ 841 if (bus->number == 0) 842 return mvebu_sw_pci_bridge_read(port, where, size, val); 843 844 if (!mvebu_pcie_link_up(port)) { 845 *val = 0xffffffff; 846 return PCIBIOS_DEVICE_NOT_FOUND; 847 } 848 849 /* Access the real PCIe interface */ 850 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 851 where, size, val); 852 853 return ret; 854 } 855 856 static struct pci_ops mvebu_pcie_ops = { 857 .read = mvebu_pcie_rd_conf, 858 .write = mvebu_pcie_wr_conf, 859 }; 860 861 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 862 const struct resource *res, 863 resource_size_t start, 864 resource_size_t size, 865 resource_size_t align) 866 { 867 if (dev->bus->number != 0) 868 return start; 869 870 /* 871 * On the PCI-to-PCI bridge side, the I/O windows must have at 872 * least a 64 KB size and the memory windows must have at 873 * least a 1 MB size. Moreover, MBus windows need to have a 874 * base address aligned on their size, and their size must be 875 * a power of two. This means that if the BAR doesn't have a 876 * power of two size, several MBus windows will actually be 877 * created. We need to ensure that the biggest MBus window 878 * (which will be the first one) is aligned on its size, which 879 * explains the rounddown_pow_of_two() being done here. 880 */ 881 if (res->flags & IORESOURCE_IO) 882 return round_up(start, max_t(resource_size_t, SZ_64K, 883 rounddown_pow_of_two(size))); 884 else if (res->flags & IORESOURCE_MEM) 885 return round_up(start, max_t(resource_size_t, SZ_1M, 886 rounddown_pow_of_two(size))); 887 else 888 return start; 889 } 890 891 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 892 struct device_node *np, 893 struct mvebu_pcie_port *port) 894 { 895 struct resource regs; 896 int ret = 0; 897 898 ret = of_address_to_resource(np, 0, ®s); 899 if (ret) 900 return ERR_PTR(ret); 901 902 return devm_ioremap_resource(&pdev->dev, ®s); 903 } 904 905 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 906 #define DT_TYPE_IO 0x1 907 #define DT_TYPE_MEM32 0x2 908 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 909 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 910 911 static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 912 unsigned long type, 913 unsigned int *tgt, 914 unsigned int *attr) 915 { 916 const int na = 3, ns = 2; 917 const __be32 *range; 918 int rlen, nranges, rangesz, pna, i; 919 920 *tgt = -1; 921 *attr = -1; 922 923 range = of_get_property(np, "ranges", &rlen); 924 if (!range) 925 return -EINVAL; 926 927 pna = of_n_addr_cells(np); 928 rangesz = pna + na + ns; 929 nranges = rlen / sizeof(__be32) / rangesz; 930 931 for (i = 0; i < nranges; i++, range += rangesz) { 932 u32 flags = of_read_number(range, 1); 933 u32 slot = of_read_number(range + 1, 1); 934 u64 cpuaddr = of_read_number(range + na, pna); 935 unsigned long rtype; 936 937 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 938 rtype = IORESOURCE_IO; 939 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 940 rtype = IORESOURCE_MEM; 941 else 942 continue; 943 944 if (slot == PCI_SLOT(devfn) && type == rtype) { 945 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 946 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 947 return 0; 948 } 949 } 950 951 return -ENOENT; 952 } 953 954 #ifdef CONFIG_PM_SLEEP 955 static int mvebu_pcie_suspend(struct device *dev) 956 { 957 struct mvebu_pcie *pcie; 958 int i; 959 960 pcie = dev_get_drvdata(dev); 961 for (i = 0; i < pcie->nports; i++) { 962 struct mvebu_pcie_port *port = pcie->ports + i; 963 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); 964 } 965 966 return 0; 967 } 968 969 static int mvebu_pcie_resume(struct device *dev) 970 { 971 struct mvebu_pcie *pcie; 972 int i; 973 974 pcie = dev_get_drvdata(dev); 975 for (i = 0; i < pcie->nports; i++) { 976 struct mvebu_pcie_port *port = pcie->ports + i; 977 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); 978 mvebu_pcie_setup_hw(port); 979 } 980 981 return 0; 982 } 983 #endif 984 985 static void mvebu_pcie_port_clk_put(void *data) 986 { 987 struct mvebu_pcie_port *port = data; 988 989 clk_put(port->clk); 990 } 991 992 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, 993 struct mvebu_pcie_port *port, struct device_node *child) 994 { 995 struct device *dev = &pcie->pdev->dev; 996 enum of_gpio_flags flags; 997 int reset_gpio, ret; 998 999 port->pcie = pcie; 1000 1001 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { 1002 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", 1003 child); 1004 goto skip; 1005 } 1006 1007 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) 1008 port->lane = 0; 1009 1010 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, 1011 port->lane); 1012 if (!port->name) { 1013 ret = -ENOMEM; 1014 goto err; 1015 } 1016 1017 port->devfn = of_pci_get_devfn(child); 1018 if (port->devfn < 0) 1019 goto skip; 1020 1021 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, 1022 &port->mem_target, &port->mem_attr); 1023 if (ret < 0) { 1024 dev_err(dev, "%s: cannot get tgt/attr for mem window\n", 1025 port->name); 1026 goto skip; 1027 } 1028 1029 if (resource_size(&pcie->io) != 0) { 1030 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, 1031 &port->io_target, &port->io_attr); 1032 } else { 1033 port->io_target = -1; 1034 port->io_attr = -1; 1035 } 1036 1037 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); 1038 if (reset_gpio == -EPROBE_DEFER) { 1039 ret = reset_gpio; 1040 goto err; 1041 } 1042 1043 if (gpio_is_valid(reset_gpio)) { 1044 unsigned long gpio_flags; 1045 1046 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", 1047 port->name); 1048 if (!port->reset_name) { 1049 ret = -ENOMEM; 1050 goto err; 1051 } 1052 1053 if (flags & OF_GPIO_ACTIVE_LOW) { 1054 dev_info(dev, "%pOF: reset gpio is active low\n", 1055 child); 1056 gpio_flags = GPIOF_ACTIVE_LOW | 1057 GPIOF_OUT_INIT_LOW; 1058 } else { 1059 gpio_flags = GPIOF_OUT_INIT_HIGH; 1060 } 1061 1062 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags, 1063 port->reset_name); 1064 if (ret) { 1065 if (ret == -EPROBE_DEFER) 1066 goto err; 1067 goto skip; 1068 } 1069 1070 port->reset_gpio = gpio_to_desc(reset_gpio); 1071 } 1072 1073 port->clk = of_clk_get_by_name(child, NULL); 1074 if (IS_ERR(port->clk)) { 1075 dev_err(dev, "%s: cannot get clock\n", port->name); 1076 goto skip; 1077 } 1078 1079 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port); 1080 if (ret < 0) { 1081 clk_put(port->clk); 1082 goto err; 1083 } 1084 1085 return 1; 1086 1087 skip: 1088 ret = 0; 1089 1090 /* In the case of skipping, we need to free these */ 1091 devm_kfree(dev, port->reset_name); 1092 port->reset_name = NULL; 1093 devm_kfree(dev, port->name); 1094 port->name = NULL; 1095 1096 err: 1097 return ret; 1098 } 1099 1100 /* 1101 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs 1102 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications 1103 * of the PCI Express Card Electromechanical Specification, 1.1. 1104 */ 1105 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) 1106 { 1107 int ret; 1108 1109 ret = clk_prepare_enable(port->clk); 1110 if (ret < 0) 1111 return ret; 1112 1113 if (port->reset_gpio) { 1114 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; 1115 1116 of_property_read_u32(port->dn, "reset-delay-us", 1117 &reset_udelay); 1118 1119 udelay(100); 1120 1121 gpiod_set_value_cansleep(port->reset_gpio, 0); 1122 msleep(reset_udelay / 1000); 1123 } 1124 1125 return 0; 1126 } 1127 1128 /* 1129 * Power down a PCIe port. Strictly, PCIe requires us to place the card 1130 * in D3hot state before asserting PERST#. 1131 */ 1132 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port) 1133 { 1134 gpiod_set_value_cansleep(port->reset_gpio, 1); 1135 1136 clk_disable_unprepare(port->clk); 1137 } 1138 1139 /* 1140 * We can't use devm_of_pci_get_host_bridge_resources() because we 1141 * need to parse our special DT properties encoding the MEM and IO 1142 * apertures. 1143 */ 1144 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie) 1145 { 1146 struct device *dev = &pcie->pdev->dev; 1147 struct device_node *np = dev->of_node; 1148 unsigned int i; 1149 int ret; 1150 1151 INIT_LIST_HEAD(&pcie->resources); 1152 1153 /* Get the bus range */ 1154 ret = of_pci_parse_bus_range(np, &pcie->busn); 1155 if (ret) { 1156 dev_err(dev, "failed to parse bus-range property: %d\n", ret); 1157 return ret; 1158 } 1159 pci_add_resource(&pcie->resources, &pcie->busn); 1160 1161 /* Get the PCIe memory aperture */ 1162 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 1163 if (resource_size(&pcie->mem) == 0) { 1164 dev_err(dev, "invalid memory aperture size\n"); 1165 return -EINVAL; 1166 } 1167 1168 pcie->mem.name = "PCI MEM"; 1169 pci_add_resource(&pcie->resources, &pcie->mem); 1170 1171 /* Get the PCIe IO aperture */ 1172 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 1173 1174 if (resource_size(&pcie->io) != 0) { 1175 pcie->realio.flags = pcie->io.flags; 1176 pcie->realio.start = PCIBIOS_MIN_IO; 1177 pcie->realio.end = min_t(resource_size_t, 1178 IO_SPACE_LIMIT - SZ_64K, 1179 resource_size(&pcie->io) - 1); 1180 pcie->realio.name = "PCI I/O"; 1181 1182 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K) 1183 pci_ioremap_io(i, pcie->io.start + i); 1184 1185 pci_add_resource(&pcie->resources, &pcie->realio); 1186 } 1187 1188 return devm_request_pci_bus_resources(dev, &pcie->resources); 1189 } 1190 1191 static int mvebu_pcie_probe(struct platform_device *pdev) 1192 { 1193 struct device *dev = &pdev->dev; 1194 struct mvebu_pcie *pcie; 1195 struct pci_host_bridge *bridge; 1196 struct device_node *np = dev->of_node; 1197 struct device_node *child; 1198 int num, i, ret; 1199 1200 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie)); 1201 if (!bridge) 1202 return -ENOMEM; 1203 1204 pcie = pci_host_bridge_priv(bridge); 1205 pcie->pdev = pdev; 1206 platform_set_drvdata(pdev, pcie); 1207 1208 ret = mvebu_pcie_parse_request_resources(pcie); 1209 if (ret) 1210 return ret; 1211 1212 num = of_get_available_child_count(np); 1213 1214 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); 1215 if (!pcie->ports) 1216 return -ENOMEM; 1217 1218 i = 0; 1219 for_each_available_child_of_node(np, child) { 1220 struct mvebu_pcie_port *port = &pcie->ports[i]; 1221 1222 ret = mvebu_pcie_parse_port(pcie, port, child); 1223 if (ret < 0) { 1224 of_node_put(child); 1225 return ret; 1226 } else if (ret == 0) { 1227 continue; 1228 } 1229 1230 port->dn = child; 1231 i++; 1232 } 1233 pcie->nports = i; 1234 1235 for (i = 0; i < pcie->nports; i++) { 1236 struct mvebu_pcie_port *port = &pcie->ports[i]; 1237 1238 child = port->dn; 1239 if (!child) 1240 continue; 1241 1242 ret = mvebu_pcie_powerup(port); 1243 if (ret < 0) 1244 continue; 1245 1246 port->base = mvebu_pcie_map_registers(pdev, child, port); 1247 if (IS_ERR(port->base)) { 1248 dev_err(dev, "%s: cannot map registers\n", port->name); 1249 port->base = NULL; 1250 mvebu_pcie_powerdown(port); 1251 continue; 1252 } 1253 1254 mvebu_pcie_setup_hw(port); 1255 mvebu_pcie_set_local_dev_nr(port, 1); 1256 mvebu_sw_pci_bridge_init(port); 1257 } 1258 1259 pcie->nports = i; 1260 1261 list_splice_init(&pcie->resources, &bridge->windows); 1262 bridge->dev.parent = dev; 1263 bridge->sysdata = pcie; 1264 bridge->busnr = 0; 1265 bridge->ops = &mvebu_pcie_ops; 1266 bridge->map_irq = of_irq_parse_and_map_pci; 1267 bridge->swizzle_irq = pci_common_swizzle; 1268 bridge->align_resource = mvebu_pcie_align_resource; 1269 bridge->msi = pcie->msi; 1270 1271 return pci_host_probe(bridge); 1272 } 1273 1274 static const struct of_device_id mvebu_pcie_of_match_table[] = { 1275 { .compatible = "marvell,armada-xp-pcie", }, 1276 { .compatible = "marvell,armada-370-pcie", }, 1277 { .compatible = "marvell,dove-pcie", }, 1278 { .compatible = "marvell,kirkwood-pcie", }, 1279 {}, 1280 }; 1281 1282 static const struct dev_pm_ops mvebu_pcie_pm_ops = { 1283 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume) 1284 }; 1285 1286 static struct platform_driver mvebu_pcie_driver = { 1287 .driver = { 1288 .name = "mvebu-pcie", 1289 .of_match_table = mvebu_pcie_of_match_table, 1290 /* driver unloading/unbinding currently not supported */ 1291 .suppress_bind_attrs = true, 1292 .pm = &mvebu_pcie_pm_ops, 1293 }, 1294 .probe = mvebu_pcie_probe, 1295 }; 1296 builtin_platform_driver(mvebu_pcie_driver); 1297