1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Loongson PCI Host Controller Driver 4 * 5 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 */ 7 8 #include <linux/of_device.h> 9 #include <linux/of_pci.h> 10 #include <linux/pci.h> 11 #include <linux/pci_ids.h> 12 #include <linux/pci-acpi.h> 13 #include <linux/pci-ecam.h> 14 15 #include "../pci.h" 16 17 /* Device IDs */ 18 #define DEV_PCIE_PORT_0 0x7a09 19 #define DEV_PCIE_PORT_1 0x7a19 20 #define DEV_PCIE_PORT_2 0x7a29 21 22 #define DEV_LS2K_APB 0x7a02 23 #define DEV_LS7A_GMAC 0x7a03 24 #define DEV_LS7A_DC1 0x7a06 25 #define DEV_LS7A_LPC 0x7a0c 26 #define DEV_LS7A_AHCI 0x7a08 27 #define DEV_LS7A_CONF 0x7a10 28 #define DEV_LS7A_GNET 0x7a13 29 #define DEV_LS7A_EHCI 0x7a14 30 #define DEV_LS7A_DC2 0x7a36 31 #define DEV_LS7A_HDMI 0x7a37 32 33 #define FLAG_CFG0 BIT(0) 34 #define FLAG_CFG1 BIT(1) 35 #define FLAG_DEV_FIX BIT(2) 36 #define FLAG_DEV_HIDDEN BIT(3) 37 38 struct loongson_pci_data { 39 u32 flags; 40 struct pci_ops *ops; 41 }; 42 43 struct loongson_pci { 44 void __iomem *cfg0_base; 45 void __iomem *cfg1_base; 46 struct platform_device *pdev; 47 const struct loongson_pci_data *data; 48 }; 49 50 /* Fixup wrong class code in PCIe bridges */ 51 static void bridge_class_quirk(struct pci_dev *dev) 52 { 53 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 54 } 55 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 56 DEV_PCIE_PORT_0, bridge_class_quirk); 57 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 58 DEV_PCIE_PORT_1, bridge_class_quirk); 59 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 60 DEV_PCIE_PORT_2, bridge_class_quirk); 61 62 static void system_bus_quirk(struct pci_dev *pdev) 63 { 64 /* 65 * The address space consumed by these devices is outside the 66 * resources of the host bridge. 67 */ 68 pdev->mmio_always_on = 1; 69 pdev->non_compliant_bars = 1; 70 } 71 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 72 DEV_LS2K_APB, system_bus_quirk); 73 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 74 DEV_LS7A_CONF, system_bus_quirk); 75 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 76 DEV_LS7A_LPC, system_bus_quirk); 77 78 static void loongson_mrrs_quirk(struct pci_dev *dev) 79 { 80 struct pci_bus *bus = dev->bus; 81 struct pci_dev *bridge; 82 static const struct pci_device_id bridge_devids[] = { 83 { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) }, 84 { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) }, 85 { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) }, 86 { 0, }, 87 }; 88 89 /* look for the matching bridge */ 90 while (!pci_is_root_bus(bus)) { 91 bridge = bus->self; 92 bus = bus->parent; 93 /* 94 * Some Loongson PCIe ports have a h/w limitation of 95 * 256 bytes maximum read request size. They can't handle 96 * anything larger than this. So force this limit on 97 * any devices attached under these ports. 98 */ 99 if (pci_match_id(bridge_devids, bridge)) { 100 if (pcie_get_readrq(dev) > 256) { 101 pci_info(dev, "limiting MRRS to 256\n"); 102 pcie_set_readrq(dev, 256); 103 } 104 break; 105 } 106 } 107 } 108 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk); 109 110 static void loongson_pci_pin_quirk(struct pci_dev *pdev) 111 { 112 pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3); 113 } 114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 115 DEV_LS7A_DC1, loongson_pci_pin_quirk); 116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 117 DEV_LS7A_DC2, loongson_pci_pin_quirk); 118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 119 DEV_LS7A_GMAC, loongson_pci_pin_quirk); 120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 121 DEV_LS7A_AHCI, loongson_pci_pin_quirk); 122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 123 DEV_LS7A_EHCI, loongson_pci_pin_quirk); 124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 125 DEV_LS7A_GNET, loongson_pci_pin_quirk); 126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 127 DEV_LS7A_HDMI, loongson_pci_pin_quirk); 128 129 static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus) 130 { 131 struct pci_config_window *cfg; 132 133 if (acpi_disabled) 134 return (struct loongson_pci *)(bus->sysdata); 135 136 cfg = bus->sysdata; 137 return (struct loongson_pci *)(cfg->priv); 138 } 139 140 static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus, 141 unsigned int devfn, int where) 142 { 143 unsigned long addroff = 0x0; 144 unsigned char busnum = bus->number; 145 146 if (!pci_is_root_bus(bus)) { 147 addroff |= BIT(24); /* Type 1 Access */ 148 addroff |= (busnum << 16); 149 } 150 addroff |= (devfn << 8) | where; 151 return priv->cfg0_base + addroff; 152 } 153 154 static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus, 155 unsigned int devfn, int where) 156 { 157 unsigned long addroff = 0x0; 158 unsigned char busnum = bus->number; 159 160 if (!pci_is_root_bus(bus)) { 161 addroff |= BIT(28); /* Type 1 Access */ 162 addroff |= (busnum << 16); 163 } 164 addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16); 165 return priv->cfg1_base + addroff; 166 } 167 168 static bool pdev_may_exist(struct pci_bus *bus, unsigned int device, 169 unsigned int function) 170 { 171 return !(pci_is_root_bus(bus) && 172 (device >= 9 && device <= 20) && (function > 0)); 173 } 174 175 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, 176 unsigned int devfn, int where) 177 { 178 unsigned int device = PCI_SLOT(devfn); 179 unsigned int function = PCI_FUNC(devfn); 180 struct loongson_pci *priv = pci_bus_to_loongson_pci(bus); 181 182 /* 183 * Do not read more than one device on the bus other than 184 * the host bus. 185 */ 186 if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) { 187 if (!pci_is_root_bus(bus) && (device > 0)) 188 return NULL; 189 } 190 191 /* Don't access non-existent devices */ 192 if (priv->data->flags & FLAG_DEV_HIDDEN) { 193 if (!pdev_may_exist(bus, device, function)) 194 return NULL; 195 } 196 197 /* CFG0 can only access standard space */ 198 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base) 199 return cfg0_map(priv, bus, devfn, where); 200 201 /* CFG1 can access extended space */ 202 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base) 203 return cfg1_map(priv, bus, devfn, where); 204 205 return NULL; 206 } 207 208 #ifdef CONFIG_OF 209 210 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 211 { 212 int irq; 213 u8 val; 214 215 irq = of_irq_parse_and_map_pci(dev, slot, pin); 216 if (irq > 0) 217 return irq; 218 219 /* Care i8259 legacy systems */ 220 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val); 221 /* i8259 only have 15 IRQs */ 222 if (val > 15) 223 return 0; 224 225 return val; 226 } 227 228 /* LS2K/LS7A accept 8/16/32-bit PCI config operations */ 229 static struct pci_ops loongson_pci_ops = { 230 .map_bus = pci_loongson_map_bus, 231 .read = pci_generic_config_read, 232 .write = pci_generic_config_write, 233 }; 234 235 /* RS780/SR5690 only accept 32-bit PCI config operations */ 236 static struct pci_ops loongson_pci_ops32 = { 237 .map_bus = pci_loongson_map_bus, 238 .read = pci_generic_config_read32, 239 .write = pci_generic_config_write32, 240 }; 241 242 static const struct loongson_pci_data ls2k_pci_data = { 243 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN, 244 .ops = &loongson_pci_ops, 245 }; 246 247 static const struct loongson_pci_data ls7a_pci_data = { 248 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN, 249 .ops = &loongson_pci_ops, 250 }; 251 252 static const struct loongson_pci_data rs780e_pci_data = { 253 .flags = FLAG_CFG0, 254 .ops = &loongson_pci_ops32, 255 }; 256 257 static const struct of_device_id loongson_pci_of_match[] = { 258 { .compatible = "loongson,ls2k-pci", 259 .data = &ls2k_pci_data, }, 260 { .compatible = "loongson,ls7a-pci", 261 .data = &ls7a_pci_data, }, 262 { .compatible = "loongson,rs780e-pci", 263 .data = &rs780e_pci_data, }, 264 {} 265 }; 266 267 static int loongson_pci_probe(struct platform_device *pdev) 268 { 269 struct loongson_pci *priv; 270 struct device *dev = &pdev->dev; 271 struct device_node *node = dev->of_node; 272 struct pci_host_bridge *bridge; 273 struct resource *regs; 274 275 if (!node) 276 return -ENODEV; 277 278 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv)); 279 if (!bridge) 280 return -ENODEV; 281 282 priv = pci_host_bridge_priv(bridge); 283 priv->pdev = pdev; 284 priv->data = of_device_get_match_data(dev); 285 286 if (priv->data->flags & FLAG_CFG0) { 287 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 288 if (!regs) 289 dev_err(dev, "missing mem resources for cfg0\n"); 290 else { 291 priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs); 292 if (IS_ERR(priv->cfg0_base)) 293 return PTR_ERR(priv->cfg0_base); 294 } 295 } 296 297 if (priv->data->flags & FLAG_CFG1) { 298 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 299 if (!regs) 300 dev_info(dev, "missing mem resource for cfg1\n"); 301 else { 302 priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs); 303 if (IS_ERR(priv->cfg1_base)) 304 priv->cfg1_base = NULL; 305 } 306 } 307 308 bridge->sysdata = priv; 309 bridge->ops = priv->data->ops; 310 bridge->map_irq = loongson_map_irq; 311 312 return pci_host_probe(bridge); 313 } 314 315 static struct platform_driver loongson_pci_driver = { 316 .driver = { 317 .name = "loongson-pci", 318 .of_match_table = loongson_pci_of_match, 319 }, 320 .probe = loongson_pci_probe, 321 }; 322 builtin_platform_driver(loongson_pci_driver); 323 324 #endif 325 326 #ifdef CONFIG_ACPI 327 328 static int loongson_pci_ecam_init(struct pci_config_window *cfg) 329 { 330 struct device *dev = cfg->parent; 331 struct loongson_pci *priv; 332 struct loongson_pci_data *data; 333 334 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 335 if (!priv) 336 return -ENOMEM; 337 338 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 339 if (!data) 340 return -ENOMEM; 341 342 cfg->priv = priv; 343 data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN; 344 priv->data = data; 345 priv->cfg1_base = cfg->win - (cfg->busr.start << 16); 346 347 return 0; 348 } 349 350 const struct pci_ecam_ops loongson_pci_ecam_ops = { 351 .bus_shift = 16, 352 .init = loongson_pci_ecam_init, 353 .pci_ops = { 354 .map_bus = pci_loongson_map_bus, 355 .read = pci_generic_config_read, 356 .write = pci_generic_config_write, 357 } 358 }; 359 360 #endif 361