1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Loongson PCI Host Controller Driver
4  *
5  * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
6  */
7 
8 #include <linux/of_device.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci.h>
11 #include <linux/pci_ids.h>
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
14 
15 #include "../pci.h"
16 
17 /* Device IDs */
18 #define DEV_LS2K_PCIE_PORT0	0x1a05
19 #define DEV_LS7A_PCIE_PORT0	0x7a09
20 #define DEV_LS7A_PCIE_PORT1	0x7a19
21 #define DEV_LS7A_PCIE_PORT2	0x7a29
22 #define DEV_LS7A_PCIE_PORT3	0x7a39
23 #define DEV_LS7A_PCIE_PORT4	0x7a49
24 #define DEV_LS7A_PCIE_PORT5	0x7a59
25 #define DEV_LS7A_PCIE_PORT6	0x7a69
26 
27 #define DEV_LS2K_APB	0x7a02
28 #define DEV_LS7A_GMAC	0x7a03
29 #define DEV_LS7A_DC1	0x7a06
30 #define DEV_LS7A_LPC	0x7a0c
31 #define DEV_LS7A_AHCI	0x7a08
32 #define DEV_LS7A_CONF	0x7a10
33 #define DEV_LS7A_GNET	0x7a13
34 #define DEV_LS7A_EHCI	0x7a14
35 #define DEV_LS7A_DC2	0x7a36
36 #define DEV_LS7A_HDMI	0x7a37
37 
38 #define FLAG_CFG0	BIT(0)
39 #define FLAG_CFG1	BIT(1)
40 #define FLAG_DEV_FIX	BIT(2)
41 #define FLAG_DEV_HIDDEN	BIT(3)
42 
43 struct loongson_pci_data {
44 	u32 flags;
45 	struct pci_ops *ops;
46 };
47 
48 struct loongson_pci {
49 	void __iomem *cfg0_base;
50 	void __iomem *cfg1_base;
51 	struct platform_device *pdev;
52 	const struct loongson_pci_data *data;
53 };
54 
55 /* Fixup wrong class code in PCIe bridges */
56 static void bridge_class_quirk(struct pci_dev *dev)
57 {
58 	dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
59 }
60 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
61 			DEV_LS7A_PCIE_PORT0, bridge_class_quirk);
62 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
63 			DEV_LS7A_PCIE_PORT1, bridge_class_quirk);
64 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
65 			DEV_LS7A_PCIE_PORT2, bridge_class_quirk);
66 
67 static void system_bus_quirk(struct pci_dev *pdev)
68 {
69 	/*
70 	 * The address space consumed by these devices is outside the
71 	 * resources of the host bridge.
72 	 */
73 	pdev->mmio_always_on = 1;
74 	pdev->non_compliant_bars = 1;
75 }
76 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
77 			DEV_LS2K_APB, system_bus_quirk);
78 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
79 			DEV_LS7A_CONF, system_bus_quirk);
80 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
81 			DEV_LS7A_LPC, system_bus_quirk);
82 
83 static void loongson_mrrs_quirk(struct pci_dev *pdev)
84 {
85 	/*
86 	 * Some Loongson PCIe ports have h/w limitations of maximum read
87 	 * request size. They can't handle anything larger than this. So
88 	 * force this limit on any devices attached under these ports.
89 	 */
90 	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
91 
92 	bridge->no_inc_mrrs = 1;
93 }
94 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
95 			DEV_LS2K_PCIE_PORT0, loongson_mrrs_quirk);
96 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
97 			DEV_LS7A_PCIE_PORT0, loongson_mrrs_quirk);
98 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
99 			DEV_LS7A_PCIE_PORT1, loongson_mrrs_quirk);
100 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
101 			DEV_LS7A_PCIE_PORT2, loongson_mrrs_quirk);
102 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
103 			DEV_LS7A_PCIE_PORT3, loongson_mrrs_quirk);
104 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
105 			DEV_LS7A_PCIE_PORT4, loongson_mrrs_quirk);
106 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
107 			DEV_LS7A_PCIE_PORT5, loongson_mrrs_quirk);
108 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
109 			DEV_LS7A_PCIE_PORT6, loongson_mrrs_quirk);
110 
111 static void loongson_pci_pin_quirk(struct pci_dev *pdev)
112 {
113 	pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
114 }
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
116 			DEV_LS7A_DC1, loongson_pci_pin_quirk);
117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
118 			DEV_LS7A_DC2, loongson_pci_pin_quirk);
119 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
120 			DEV_LS7A_GMAC, loongson_pci_pin_quirk);
121 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
122 			DEV_LS7A_AHCI, loongson_pci_pin_quirk);
123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
124 			DEV_LS7A_EHCI, loongson_pci_pin_quirk);
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
126 			DEV_LS7A_GNET, loongson_pci_pin_quirk);
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
128 			DEV_LS7A_HDMI, loongson_pci_pin_quirk);
129 
130 static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
131 {
132 	struct pci_config_window *cfg;
133 
134 	if (acpi_disabled)
135 		return (struct loongson_pci *)(bus->sysdata);
136 
137 	cfg = bus->sysdata;
138 	return (struct loongson_pci *)(cfg->priv);
139 }
140 
141 static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus,
142 			      unsigned int devfn, int where)
143 {
144 	unsigned long addroff = 0x0;
145 	unsigned char busnum = bus->number;
146 
147 	if (!pci_is_root_bus(bus)) {
148 		addroff |= BIT(24); /* Type 1 Access */
149 		addroff |= (busnum << 16);
150 	}
151 	addroff |= (devfn << 8) | where;
152 	return priv->cfg0_base + addroff;
153 }
154 
155 static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus,
156 			      unsigned int devfn, int where)
157 {
158 	unsigned long addroff = 0x0;
159 	unsigned char busnum = bus->number;
160 
161 	if (!pci_is_root_bus(bus)) {
162 		addroff |= BIT(28); /* Type 1 Access */
163 		addroff |= (busnum << 16);
164 	}
165 	addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16);
166 	return priv->cfg1_base + addroff;
167 }
168 
169 static bool pdev_may_exist(struct pci_bus *bus, unsigned int device,
170 			   unsigned int function)
171 {
172 	return !(pci_is_root_bus(bus) &&
173 		(device >= 9 && device <= 20) && (function > 0));
174 }
175 
176 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus,
177 					  unsigned int devfn, int where)
178 {
179 	unsigned int device = PCI_SLOT(devfn);
180 	unsigned int function = PCI_FUNC(devfn);
181 	struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
182 
183 	/*
184 	 * Do not read more than one device on the bus other than
185 	 * the host bus.
186 	 */
187 	if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) {
188 		if (!pci_is_root_bus(bus) && (device > 0))
189 			return NULL;
190 	}
191 
192 	/* Don't access non-existent devices */
193 	if (priv->data->flags & FLAG_DEV_HIDDEN) {
194 		if (!pdev_may_exist(bus, device, function))
195 			return NULL;
196 	}
197 
198 	/* CFG0 can only access standard space */
199 	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
200 		return cfg0_map(priv, bus, devfn, where);
201 
202 	/* CFG1 can access extended space */
203 	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
204 		return cfg1_map(priv, bus, devfn, where);
205 
206 	return NULL;
207 }
208 
209 #ifdef CONFIG_OF
210 
211 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
212 {
213 	int irq;
214 	u8 val;
215 
216 	irq = of_irq_parse_and_map_pci(dev, slot, pin);
217 	if (irq > 0)
218 		return irq;
219 
220 	/* Care i8259 legacy systems */
221 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
222 	/* i8259 only have 15 IRQs */
223 	if (val > 15)
224 		return 0;
225 
226 	return val;
227 }
228 
229 /* LS2K/LS7A accept 8/16/32-bit PCI config operations */
230 static struct pci_ops loongson_pci_ops = {
231 	.map_bus = pci_loongson_map_bus,
232 	.read	= pci_generic_config_read,
233 	.write	= pci_generic_config_write,
234 };
235 
236 /* RS780/SR5690 only accept 32-bit PCI config operations */
237 static struct pci_ops loongson_pci_ops32 = {
238 	.map_bus = pci_loongson_map_bus,
239 	.read	= pci_generic_config_read32,
240 	.write	= pci_generic_config_write32,
241 };
242 
243 static const struct loongson_pci_data ls2k_pci_data = {
244 	.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
245 	.ops = &loongson_pci_ops,
246 };
247 
248 static const struct loongson_pci_data ls7a_pci_data = {
249 	.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
250 	.ops = &loongson_pci_ops,
251 };
252 
253 static const struct loongson_pci_data rs780e_pci_data = {
254 	.flags = FLAG_CFG0,
255 	.ops = &loongson_pci_ops32,
256 };
257 
258 static const struct of_device_id loongson_pci_of_match[] = {
259 	{ .compatible = "loongson,ls2k-pci",
260 		.data = &ls2k_pci_data, },
261 	{ .compatible = "loongson,ls7a-pci",
262 		.data = &ls7a_pci_data, },
263 	{ .compatible = "loongson,rs780e-pci",
264 		.data = &rs780e_pci_data, },
265 	{}
266 };
267 
268 static int loongson_pci_probe(struct platform_device *pdev)
269 {
270 	struct loongson_pci *priv;
271 	struct device *dev = &pdev->dev;
272 	struct device_node *node = dev->of_node;
273 	struct pci_host_bridge *bridge;
274 	struct resource *regs;
275 
276 	if (!node)
277 		return -ENODEV;
278 
279 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
280 	if (!bridge)
281 		return -ENODEV;
282 
283 	priv = pci_host_bridge_priv(bridge);
284 	priv->pdev = pdev;
285 	priv->data = of_device_get_match_data(dev);
286 
287 	if (priv->data->flags & FLAG_CFG0) {
288 		regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 		if (!regs)
290 			dev_err(dev, "missing mem resources for cfg0\n");
291 		else {
292 			priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
293 			if (IS_ERR(priv->cfg0_base))
294 				return PTR_ERR(priv->cfg0_base);
295 		}
296 	}
297 
298 	if (priv->data->flags & FLAG_CFG1) {
299 		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
300 		if (!regs)
301 			dev_info(dev, "missing mem resource for cfg1\n");
302 		else {
303 			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
304 			if (IS_ERR(priv->cfg1_base))
305 				priv->cfg1_base = NULL;
306 		}
307 	}
308 
309 	bridge->sysdata = priv;
310 	bridge->ops = priv->data->ops;
311 	bridge->map_irq = loongson_map_irq;
312 
313 	return pci_host_probe(bridge);
314 }
315 
316 static struct platform_driver loongson_pci_driver = {
317 	.driver = {
318 		.name = "loongson-pci",
319 		.of_match_table = loongson_pci_of_match,
320 	},
321 	.probe = loongson_pci_probe,
322 };
323 builtin_platform_driver(loongson_pci_driver);
324 
325 #endif
326 
327 #ifdef CONFIG_ACPI
328 
329 static int loongson_pci_ecam_init(struct pci_config_window *cfg)
330 {
331 	struct device *dev = cfg->parent;
332 	struct loongson_pci *priv;
333 	struct loongson_pci_data *data;
334 
335 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
336 	if (!priv)
337 		return -ENOMEM;
338 
339 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
340 	if (!data)
341 		return -ENOMEM;
342 
343 	cfg->priv = priv;
344 	data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN;
345 	priv->data = data;
346 	priv->cfg1_base = cfg->win - (cfg->busr.start << 16);
347 
348 	return 0;
349 }
350 
351 const struct pci_ecam_ops loongson_pci_ecam_ops = {
352 	.bus_shift = 16,
353 	.init	   = loongson_pci_ecam_init,
354 	.pci_ops   = {
355 		.map_bus = pci_loongson_map_bus,
356 		.read	 = pci_generic_config_read,
357 		.write	 = pci_generic_config_write,
358 	}
359 };
360 
361 #endif
362