1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Intel IXP4xx PCI host controller 4 * 5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver 8 * Copyright (C) 2002 Intel Corporation 9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org> 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net> 12 * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it> 13 * 14 * TODO: 15 * - Test IO-space access 16 * - DMA support 17 */ 18 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_pci.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/bits.h> 29 30 /* Register offsets */ 31 #define IXP4XX_PCI_NP_AD 0x00 32 #define IXP4XX_PCI_NP_CBE 0x04 33 #define IXP4XX_PCI_NP_WDATA 0x08 34 #define IXP4XX_PCI_NP_RDATA 0x0c 35 #define IXP4XX_PCI_CRP_AD_CBE 0x10 36 #define IXP4XX_PCI_CRP_WDATA 0x14 37 #define IXP4XX_PCI_CRP_RDATA 0x18 38 #define IXP4XX_PCI_CSR 0x1c 39 #define IXP4XX_PCI_ISR 0x20 40 #define IXP4XX_PCI_INTEN 0x24 41 #define IXP4XX_PCI_DMACTRL 0x28 42 #define IXP4XX_PCI_AHBMEMBASE 0x2c 43 #define IXP4XX_PCI_AHBIOBASE 0x30 44 #define IXP4XX_PCI_PCIMEMBASE 0x34 45 #define IXP4XX_PCI_AHBDOORBELL 0x38 46 #define IXP4XX_PCI_PCIDOORBELL 0x3c 47 #define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 48 #define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 49 #define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 50 #define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c 51 #define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 52 #define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 53 54 /* CSR bit definitions */ 55 #define IXP4XX_PCI_CSR_HOST BIT(0) 56 #define IXP4XX_PCI_CSR_ARBEN BIT(1) 57 #define IXP4XX_PCI_CSR_ADS BIT(2) 58 #define IXP4XX_PCI_CSR_PDS BIT(3) 59 #define IXP4XX_PCI_CSR_ABE BIT(4) 60 #define IXP4XX_PCI_CSR_DBT BIT(5) 61 #define IXP4XX_PCI_CSR_ASE BIT(8) 62 #define IXP4XX_PCI_CSR_IC BIT(15) 63 #define IXP4XX_PCI_CSR_PRST BIT(16) 64 65 /* ISR (Interrupt status) Register bit definitions */ 66 #define IXP4XX_PCI_ISR_PSE BIT(0) 67 #define IXP4XX_PCI_ISR_PFE BIT(1) 68 #define IXP4XX_PCI_ISR_PPE BIT(2) 69 #define IXP4XX_PCI_ISR_AHBE BIT(3) 70 #define IXP4XX_PCI_ISR_APDC BIT(4) 71 #define IXP4XX_PCI_ISR_PADC BIT(5) 72 #define IXP4XX_PCI_ISR_ADB BIT(6) 73 #define IXP4XX_PCI_ISR_PDB BIT(7) 74 75 /* INTEN (Interrupt Enable) Register bit definitions */ 76 #define IXP4XX_PCI_INTEN_PSE BIT(0) 77 #define IXP4XX_PCI_INTEN_PFE BIT(1) 78 #define IXP4XX_PCI_INTEN_PPE BIT(2) 79 #define IXP4XX_PCI_INTEN_AHBE BIT(3) 80 #define IXP4XX_PCI_INTEN_APDC BIT(4) 81 #define IXP4XX_PCI_INTEN_PADC BIT(5) 82 #define IXP4XX_PCI_INTEN_ADB BIT(6) 83 #define IXP4XX_PCI_INTEN_PDB BIT(7) 84 85 /* Shift value for byte enable on NP cmd/byte enable register */ 86 #define IXP4XX_PCI_NP_CBE_BESL 4 87 88 /* PCI commands supported by NP access unit */ 89 #define NP_CMD_IOREAD 0x2 90 #define NP_CMD_IOWRITE 0x3 91 #define NP_CMD_CONFIGREAD 0xa 92 #define NP_CMD_CONFIGWRITE 0xb 93 #define NP_CMD_MEMREAD 0x6 94 #define NP_CMD_MEMWRITE 0x7 95 96 /* Constants for CRP access into local config space */ 97 #define CRP_AD_CBE_BESL 20 98 #define CRP_AD_CBE_WRITE 0x00010000 99 100 /* Special PCI configuration space registers for this controller */ 101 #define IXP4XX_PCI_RTOTTO 0x40 102 103 struct ixp4xx_pci { 104 struct device *dev; 105 void __iomem *base; 106 bool errata_hammer; 107 bool host_mode; 108 }; 109 110 /* 111 * The IXP4xx has a peculiar address bus that will change the 112 * byte order on SoC peripherals depending on whether the device 113 * operates in big-endian or little-endian mode. That means that 114 * readl() and writel() that always use little-endian access 115 * will not work for SoC peripherals such as the PCI controller 116 * when used in big-endian mode. The accesses to the individual 117 * PCI devices on the other hand, are always little-endian and 118 * can use readl() and writel(). 119 * 120 * For local AHB bus access we need to use __raw_[readl|writel]() 121 * to make sure that we access the SoC devices in the CPU native 122 * endianness. 123 */ 124 static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) 125 { 126 return __raw_readl(p->base + reg); 127 } 128 129 static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) 130 { 131 __raw_writel(val, p->base + reg); 132 } 133 134 static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) 135 { 136 u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 137 138 if (isr & IXP4XX_PCI_ISR_PFE) { 139 /* Make sure the master abort bit is reset */ 140 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 141 dev_dbg(p->dev, "master abort detected\n"); 142 return -EINVAL; 143 } 144 145 return 0; 146 } 147 148 static int ixp4xx_pci_read(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) 149 { 150 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 151 152 if (p->errata_hammer) { 153 int i; 154 155 /* 156 * PCI workaround - only works if NP PCI space reads have 157 * no side effects. Hammer the register and read twice 8 158 * times. last one will be good. 159 */ 160 for (i = 0; i < 8; i++) { 161 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 162 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 163 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 164 } 165 } else { 166 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 167 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 168 } 169 170 return ixp4xx_pci_check_master_abort(p); 171 } 172 173 static int ixp4xx_pci_write(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) 174 { 175 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 176 177 /* Set up the write */ 178 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 179 180 /* Execute the write by writing to NP_WDATA */ 181 ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); 182 183 return ixp4xx_pci_check_master_abort(p); 184 } 185 186 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) 187 { 188 /* Root bus is always 0 in this hardware */ 189 if (bus_num == 0) { 190 /* type 0 */ 191 return BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 192 (where & ~3); 193 } else { 194 /* type 1 */ 195 return (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 196 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; 197 } 198 } 199 200 /* 201 * CRP functions are "Controller Configuration Port" accesses 202 * initiated from within this driver itself to read/write PCI 203 * control information in the config space. 204 */ 205 static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size) 206 { 207 if (size == 1) 208 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; 209 if (size == 2) 210 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; 211 if (size == 4) 212 return 0; 213 return 0xffffffff; 214 } 215 216 static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, 217 u32 *value) 218 { 219 u32 n, cmd, val; 220 221 n = where % 4; 222 cmd = where & ~3; 223 224 dev_dbg(p->dev, "%s from %d size %d cmd %08x\n", 225 __func__, where, size, cmd); 226 227 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 228 val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA); 229 230 val >>= (8*n); 231 switch (size) { 232 case 1: 233 val &= U8_MAX; 234 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 235 break; 236 case 2: 237 val &= U16_MAX; 238 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 239 break; 240 case 4: 241 val &= U32_MAX; 242 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 243 break; 244 default: 245 /* Should not happen */ 246 dev_err(p->dev, "%s illegal size\n", __func__); 247 return PCIBIOS_DEVICE_NOT_FOUND; 248 } 249 *value = val; 250 251 return PCIBIOS_SUCCESSFUL; 252 } 253 254 static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, 255 u32 value) 256 { 257 u32 n, cmd, val; 258 259 n = where % 4; 260 cmd = ixp4xx_crp_byte_lane_enable_bits(n, size); 261 if (cmd == 0xffffffff) 262 return PCIBIOS_BAD_REGISTER_NUMBER; 263 cmd |= where & ~3; 264 cmd |= CRP_AD_CBE_WRITE; 265 266 val = value << (8*n); 267 268 dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n", 269 __func__, where, size, cmd, val); 270 271 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 272 ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val); 273 274 return PCIBIOS_SUCCESSFUL; 275 } 276 277 /* 278 * Then follows the functions that read and write from the common PCI 279 * configuration space. 280 */ 281 static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size) 282 { 283 if (size == 1) 284 return (0xf & ~BIT(n)) << 4; 285 if (size == 2) 286 return (0xf & ~(BIT(n) | BIT(n+1))) << 4; 287 if (size == 4) 288 return 0; 289 return 0xffffffff; 290 } 291 292 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 293 int where, int size, u32 *value) 294 { 295 struct ixp4xx_pci *p = bus->sysdata; 296 u32 n, addr, val, cmd; 297 u8 bus_num = bus->number; 298 int ret; 299 300 *value = 0xffffffff; 301 n = where % 4; 302 cmd = ixp4xx_byte_lane_enable_bits(n, size); 303 if (cmd == 0xffffffff) 304 return PCIBIOS_BAD_REGISTER_NUMBER; 305 306 addr = ixp4xx_config_addr(bus_num, devfn, where); 307 cmd |= NP_CMD_CONFIGREAD; 308 dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n", 309 where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 310 311 ret = ixp4xx_pci_read(p, addr, cmd, &val); 312 if (ret) 313 return PCIBIOS_DEVICE_NOT_FOUND; 314 315 val >>= (8*n); 316 switch (size) { 317 case 1: 318 val &= U8_MAX; 319 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 320 break; 321 case 2: 322 val &= U16_MAX; 323 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 324 break; 325 case 4: 326 val &= U32_MAX; 327 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 328 break; 329 default: 330 /* Should not happen */ 331 dev_err(p->dev, "%s illegal size\n", __func__); 332 return PCIBIOS_DEVICE_NOT_FOUND; 333 } 334 *value = val; 335 336 return PCIBIOS_SUCCESSFUL; 337 } 338 339 static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 340 int where, int size, u32 value) 341 { 342 struct ixp4xx_pci *p = bus->sysdata; 343 u32 n, addr, val, cmd; 344 u8 bus_num = bus->number; 345 int ret; 346 347 n = where % 4; 348 cmd = ixp4xx_byte_lane_enable_bits(n, size); 349 if (cmd == 0xffffffff) 350 return PCIBIOS_BAD_REGISTER_NUMBER; 351 352 addr = ixp4xx_config_addr(bus_num, devfn, where); 353 cmd |= NP_CMD_CONFIGWRITE; 354 val = value << (8*n); 355 356 dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n", 357 value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 358 359 ret = ixp4xx_pci_write(p, addr, cmd, val); 360 if (ret) 361 return PCIBIOS_DEVICE_NOT_FOUND; 362 363 return PCIBIOS_SUCCESSFUL; 364 } 365 366 static struct pci_ops ixp4xx_pci_ops = { 367 .read = ixp4xx_pci_read_config, 368 .write = ixp4xx_pci_write_config, 369 }; 370 371 static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr) 372 { 373 u8 base; 374 375 base = ((addr & 0xff000000) >> 24); 376 return (base << 24) | ((base + 1) << 16) 377 | ((base + 2) << 8) | (base + 3); 378 } 379 380 static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p) 381 { 382 struct device *dev = p->dev; 383 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 384 struct resource_entry *win; 385 struct resource *res; 386 phys_addr_t addr; 387 388 win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 389 if (win) { 390 u32 pcimembase; 391 392 res = win->res; 393 addr = res->start - win->offset; 394 395 if (res->flags & IORESOURCE_PREFETCH) 396 res->name = "IXP4xx PCI PRE-MEM"; 397 else 398 res->name = "IXP4xx PCI NON-PRE-MEM"; 399 400 dev_dbg(dev, "%s window %pR, bus addr %pa\n", 401 res->name, res, &addr); 402 if (resource_size(res) != SZ_64M) { 403 dev_err(dev, "memory range is not 64MB\n"); 404 return -EINVAL; 405 } 406 407 pcimembase = ixp4xx_pci_addr_to_64mconf(addr); 408 /* Commit configuration */ 409 ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase); 410 } else { 411 dev_err(dev, "no AHB memory mapping defined\n"); 412 } 413 414 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 415 if (win) { 416 res = win->res; 417 418 addr = pci_pio_to_address(res->start); 419 if (addr & 0xff) { 420 dev_err(dev, "IO mem at uneven address: %pa\n", &addr); 421 return -EINVAL; 422 } 423 424 res->name = "IXP4xx PCI IO MEM"; 425 /* 426 * Setup I/O space location for PCI->AHB access, the 427 * upper 24 bits of the address goes into the lower 428 * 24 bits of this register. 429 */ 430 ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8)); 431 } else { 432 dev_info(dev, "no IO space AHB memory mapping defined\n"); 433 } 434 435 return 0; 436 } 437 438 static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p) 439 { 440 struct device *dev = p->dev; 441 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 442 struct resource_entry *win; 443 struct resource *res; 444 phys_addr_t addr; 445 u32 ahbmembase; 446 447 win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); 448 if (win) { 449 res = win->res; 450 addr = res->start - win->offset; 451 452 if (resource_size(res) != SZ_64M) { 453 dev_err(dev, "DMA memory range is not 64MB\n"); 454 return -EINVAL; 455 } 456 457 dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr); 458 /* 459 * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits 460 * into each byte of the PCI_AHBMEMBASE register. 461 */ 462 ahbmembase = ixp4xx_pci_addr_to_64mconf(addr); 463 /* Commit AHB membase */ 464 ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase); 465 } else { 466 dev_err(dev, "no DMA memory range defined\n"); 467 } 468 469 return 0; 470 } 471 472 /* Only used to get context for abort handling */ 473 static struct ixp4xx_pci *ixp4xx_pci_abort_singleton; 474 475 static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, 476 struct pt_regs *regs) 477 { 478 struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; 479 u32 isr, status; 480 int ret; 481 482 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 483 ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); 484 if (ret) { 485 dev_err(p->dev, "unable to read abort status\n"); 486 return -EINVAL; 487 } 488 489 dev_err(p->dev, 490 "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", 491 addr, isr, status); 492 493 /* Make sure the Master Abort bit is reset */ 494 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 495 status |= PCI_STATUS_REC_MASTER_ABORT; 496 ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); 497 if (ret) 498 dev_err(p->dev, "unable to clear abort status bit\n"); 499 500 /* 501 * If it was an imprecise abort, then we need to correct the 502 * return address to be _after_ the instruction. 503 */ 504 if (fsr & (1 << 10)) { 505 dev_err(p->dev, "imprecise abort\n"); 506 regs->ARM_pc += 4; 507 } 508 509 return 0; 510 } 511 512 static int __init ixp4xx_pci_probe(struct platform_device *pdev) 513 { 514 struct device *dev = &pdev->dev; 515 struct device_node *np = dev->of_node; 516 struct ixp4xx_pci *p; 517 struct pci_host_bridge *host; 518 int ret; 519 u32 val; 520 phys_addr_t addr; 521 u32 basereg[4] = { 522 PCI_BASE_ADDRESS_0, 523 PCI_BASE_ADDRESS_1, 524 PCI_BASE_ADDRESS_2, 525 PCI_BASE_ADDRESS_3, 526 }; 527 int i; 528 529 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 530 if (!host) 531 return -ENOMEM; 532 533 host->ops = &ixp4xx_pci_ops; 534 p = pci_host_bridge_priv(host); 535 host->sysdata = p; 536 p->dev = dev; 537 dev_set_drvdata(dev, p); 538 539 /* 540 * Set up quirk for erratic behaviour in the 42x variant 541 * when accessing config space. 542 */ 543 if (of_device_is_compatible(np, "intel,ixp42x-pci")) { 544 p->errata_hammer = true; 545 dev_info(dev, "activate hammering errata\n"); 546 } 547 548 p->base = devm_platform_ioremap_resource(pdev, 0); 549 if (IS_ERR(p->base)) 550 return PTR_ERR(p->base); 551 552 val = ixp4xx_readl(p, IXP4XX_PCI_CSR); 553 p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); 554 dev_info(dev, "controller is in %s mode\n", 555 p->host_mode ? "host" : "option"); 556 557 /* Hook in our fault handler for PCI errors */ 558 ixp4xx_pci_abort_singleton = p; 559 hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, 560 "imprecise external abort"); 561 562 ret = ixp4xx_pci_parse_map_ranges(p); 563 if (ret) 564 return ret; 565 566 ret = ixp4xx_pci_parse_map_dma_ranges(p); 567 if (ret) 568 return ret; 569 570 /* This is only configured in host mode */ 571 if (p->host_mode) { 572 addr = __pa(PAGE_OFFSET); 573 /* This is a noop (0x00) but explains what is going on */ 574 addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; 575 576 for (i = 0; i < 4; i++) { 577 /* Write this directly into the config space */ 578 ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); 579 if (ret) 580 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); 581 else 582 dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); 583 addr += SZ_16M; 584 } 585 586 /* 587 * Enable CSR window at 64 MiB to allow PCI masters to continue 588 * prefetching past the 64 MiB boundary, if all AHB to PCI 589 * windows are consecutive. 590 */ 591 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); 592 if (ret) 593 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); 594 else 595 dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); 596 597 /* 598 * Put the IO memory window at the very end of physical memory 599 * at 0xfffffc00. This is when the system is trying to access IO 600 * memory over AHB. 601 */ 602 addr = 0xfffffc00; 603 addr |= PCI_BASE_ADDRESS_SPACE_IO; 604 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); 605 if (ret) 606 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); 607 else 608 dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); 609 610 /* 611 * Retry timeout to 0x80 612 * Transfer ready timeout to 0xff 613 */ 614 ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, 615 0x000080ff); 616 if (ret) 617 dev_err(dev, "failed to set up TRDY limit\n"); 618 else 619 dev_info(dev, "set TRDY limit to 0x80ff\n"); 620 } 621 622 /* Clear interrupts */ 623 val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; 624 ixp4xx_writel(p, IXP4XX_PCI_ISR, val); 625 626 /* 627 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 628 * generate PCI configuration cycles. Specify that the AHB bus is 629 * operating in big-endian mode. Set up byte lane swapping between 630 * little-endian PCI and the big-endian AHB bus. 631 */ 632 val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; 633 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 634 val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); 635 ixp4xx_writel(p, IXP4XX_PCI_CSR, val); 636 637 ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 638 if (ret) 639 dev_err(dev, "unable to initialize master and command memory\n"); 640 else 641 dev_info(dev, "initialized as master\n"); 642 643 pci_host_probe(host); 644 645 return 0; 646 } 647 648 static const struct of_device_id ixp4xx_pci_of_match[] = { 649 { 650 .compatible = "intel,ixp42x-pci", 651 }, 652 { 653 .compatible = "intel,ixp43x-pci", 654 }, 655 {}, 656 }; 657 658 /* 659 * This driver needs to be a builtin module with suppressed bind 660 * attributes since the probe() is initializing a hard exception 661 * handler and this can only be done from __init-tagged code 662 * sections. This module cannot be removed and inserted at all. 663 */ 664 static struct platform_driver ixp4xx_pci_driver = { 665 .driver = { 666 .name = "ixp4xx-pci", 667 .suppress_bind_attrs = true, 668 .of_match_table = ixp4xx_pci_of_match, 669 }, 670 }; 671 builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe); 672