1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Intel IXP4xx PCI host controller 4 * 5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver 8 * Copyright (C) 2002 Intel Corporation 9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org> 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net> 12 * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it> 13 * 14 * TODO: 15 * - Test IO-space access 16 * - DMA support 17 */ 18 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_pci.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/bits.h> 29 #include "../pci.h" 30 31 /* Register offsets */ 32 #define IXP4XX_PCI_NP_AD 0x00 33 #define IXP4XX_PCI_NP_CBE 0x04 34 #define IXP4XX_PCI_NP_WDATA 0x08 35 #define IXP4XX_PCI_NP_RDATA 0x0c 36 #define IXP4XX_PCI_CRP_AD_CBE 0x10 37 #define IXP4XX_PCI_CRP_WDATA 0x14 38 #define IXP4XX_PCI_CRP_RDATA 0x18 39 #define IXP4XX_PCI_CSR 0x1c 40 #define IXP4XX_PCI_ISR 0x20 41 #define IXP4XX_PCI_INTEN 0x24 42 #define IXP4XX_PCI_DMACTRL 0x28 43 #define IXP4XX_PCI_AHBMEMBASE 0x2c 44 #define IXP4XX_PCI_AHBIOBASE 0x30 45 #define IXP4XX_PCI_PCIMEMBASE 0x34 46 #define IXP4XX_PCI_AHBDOORBELL 0x38 47 #define IXP4XX_PCI_PCIDOORBELL 0x3c 48 #define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 49 #define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 50 #define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 51 #define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c 52 #define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 53 #define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 54 55 /* CSR bit definitions */ 56 #define IXP4XX_PCI_CSR_HOST BIT(0) 57 #define IXP4XX_PCI_CSR_ARBEN BIT(1) 58 #define IXP4XX_PCI_CSR_ADS BIT(2) 59 #define IXP4XX_PCI_CSR_PDS BIT(3) 60 #define IXP4XX_PCI_CSR_ABE BIT(4) 61 #define IXP4XX_PCI_CSR_DBT BIT(5) 62 #define IXP4XX_PCI_CSR_ASE BIT(8) 63 #define IXP4XX_PCI_CSR_IC BIT(15) 64 #define IXP4XX_PCI_CSR_PRST BIT(16) 65 66 /* ISR (Interrupt status) Register bit definitions */ 67 #define IXP4XX_PCI_ISR_PSE BIT(0) 68 #define IXP4XX_PCI_ISR_PFE BIT(1) 69 #define IXP4XX_PCI_ISR_PPE BIT(2) 70 #define IXP4XX_PCI_ISR_AHBE BIT(3) 71 #define IXP4XX_PCI_ISR_APDC BIT(4) 72 #define IXP4XX_PCI_ISR_PADC BIT(5) 73 #define IXP4XX_PCI_ISR_ADB BIT(6) 74 #define IXP4XX_PCI_ISR_PDB BIT(7) 75 76 /* INTEN (Interrupt Enable) Register bit definitions */ 77 #define IXP4XX_PCI_INTEN_PSE BIT(0) 78 #define IXP4XX_PCI_INTEN_PFE BIT(1) 79 #define IXP4XX_PCI_INTEN_PPE BIT(2) 80 #define IXP4XX_PCI_INTEN_AHBE BIT(3) 81 #define IXP4XX_PCI_INTEN_APDC BIT(4) 82 #define IXP4XX_PCI_INTEN_PADC BIT(5) 83 #define IXP4XX_PCI_INTEN_ADB BIT(6) 84 #define IXP4XX_PCI_INTEN_PDB BIT(7) 85 86 /* Shift value for byte enable on NP cmd/byte enable register */ 87 #define IXP4XX_PCI_NP_CBE_BESL 4 88 89 /* PCI commands supported by NP access unit */ 90 #define NP_CMD_IOREAD 0x2 91 #define NP_CMD_IOWRITE 0x3 92 #define NP_CMD_CONFIGREAD 0xa 93 #define NP_CMD_CONFIGWRITE 0xb 94 #define NP_CMD_MEMREAD 0x6 95 #define NP_CMD_MEMWRITE 0x7 96 97 /* Constants for CRP access into local config space */ 98 #define CRP_AD_CBE_BESL 20 99 #define CRP_AD_CBE_WRITE 0x00010000 100 101 /* Special PCI configuration space registers for this controller */ 102 #define IXP4XX_PCI_RTOTTO 0x40 103 104 struct ixp4xx_pci { 105 struct device *dev; 106 void __iomem *base; 107 bool errata_hammer; 108 bool host_mode; 109 }; 110 111 /* 112 * The IXP4xx has a peculiar address bus that will change the 113 * byte order on SoC peripherals depending on whether the device 114 * operates in big-endian or little-endian mode. That means that 115 * readl() and writel() that always use little-endian access 116 * will not work for SoC peripherals such as the PCI controller 117 * when used in big-endian mode. The accesses to the individual 118 * PCI devices on the other hand, are always little-endian and 119 * can use readl() and writel(). 120 * 121 * For local AHB bus access we need to use __raw_[readl|writel]() 122 * to make sure that we access the SoC devices in the CPU native 123 * endianness. 124 */ 125 static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) 126 { 127 return __raw_readl(p->base + reg); 128 } 129 130 static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) 131 { 132 __raw_writel(val, p->base + reg); 133 } 134 135 static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) 136 { 137 u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 138 139 if (isr & IXP4XX_PCI_ISR_PFE) { 140 /* Make sure the master abort bit is reset */ 141 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 142 dev_dbg(p->dev, "master abort detected\n"); 143 return -EINVAL; 144 } 145 146 return 0; 147 } 148 149 static int ixp4xx_pci_read_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) 150 { 151 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 152 153 if (p->errata_hammer) { 154 int i; 155 156 /* 157 * PCI workaround - only works if NP PCI space reads have 158 * no side effects. Hammer the register and read twice 8 159 * times. last one will be good. 160 */ 161 for (i = 0; i < 8; i++) { 162 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 163 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 164 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 165 } 166 } else { 167 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 168 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 169 } 170 171 return ixp4xx_pci_check_master_abort(p); 172 } 173 174 static int ixp4xx_pci_write_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) 175 { 176 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 177 178 /* Set up the write */ 179 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 180 181 /* Execute the write by writing to NP_WDATA */ 182 ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); 183 184 return ixp4xx_pci_check_master_abort(p); 185 } 186 187 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) 188 { 189 /* Root bus is always 0 in this hardware */ 190 if (bus_num == 0) { 191 /* type 0 */ 192 return (PCI_CONF1_ADDRESS(0, 0, PCI_FUNC(devfn), where) & 193 ~PCI_CONF1_ENABLE) | BIT(32-PCI_SLOT(devfn)); 194 } else { 195 /* type 1 */ 196 return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), 197 PCI_FUNC(devfn), where) & 198 ~PCI_CONF1_ENABLE) | 1; 199 } 200 } 201 202 /* 203 * CRP functions are "Controller Configuration Port" accesses 204 * initiated from within this driver itself to read/write PCI 205 * control information in the config space. 206 */ 207 static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size) 208 { 209 if (size == 1) 210 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; 211 if (size == 2) 212 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; 213 if (size == 4) 214 return 0; 215 return 0xffffffff; 216 } 217 218 static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, 219 u32 *value) 220 { 221 u32 n, cmd, val; 222 223 n = where % 4; 224 cmd = where & ~3; 225 226 dev_dbg(p->dev, "%s from %d size %d cmd %08x\n", 227 __func__, where, size, cmd); 228 229 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 230 val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA); 231 232 val >>= (8*n); 233 switch (size) { 234 case 1: 235 val &= U8_MAX; 236 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 237 break; 238 case 2: 239 val &= U16_MAX; 240 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 241 break; 242 case 4: 243 val &= U32_MAX; 244 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 245 break; 246 default: 247 /* Should not happen */ 248 dev_err(p->dev, "%s illegal size\n", __func__); 249 return PCIBIOS_DEVICE_NOT_FOUND; 250 } 251 *value = val; 252 253 return PCIBIOS_SUCCESSFUL; 254 } 255 256 static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, 257 u32 value) 258 { 259 u32 n, cmd, val; 260 261 n = where % 4; 262 cmd = ixp4xx_crp_byte_lane_enable_bits(n, size); 263 if (cmd == 0xffffffff) 264 return PCIBIOS_BAD_REGISTER_NUMBER; 265 cmd |= where & ~3; 266 cmd |= CRP_AD_CBE_WRITE; 267 268 val = value << (8*n); 269 270 dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n", 271 __func__, where, size, cmd, val); 272 273 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 274 ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val); 275 276 return PCIBIOS_SUCCESSFUL; 277 } 278 279 /* 280 * Then follows the functions that read and write from the common PCI 281 * configuration space. 282 */ 283 static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size) 284 { 285 if (size == 1) 286 return (0xf & ~BIT(n)) << 4; 287 if (size == 2) 288 return (0xf & ~(BIT(n) | BIT(n+1))) << 4; 289 if (size == 4) 290 return 0; 291 return 0xffffffff; 292 } 293 294 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 295 int where, int size, u32 *value) 296 { 297 struct ixp4xx_pci *p = bus->sysdata; 298 u32 n, addr, val, cmd; 299 u8 bus_num = bus->number; 300 int ret; 301 302 *value = 0xffffffff; 303 n = where % 4; 304 cmd = ixp4xx_byte_lane_enable_bits(n, size); 305 if (cmd == 0xffffffff) 306 return PCIBIOS_BAD_REGISTER_NUMBER; 307 308 addr = ixp4xx_config_addr(bus_num, devfn, where); 309 cmd |= NP_CMD_CONFIGREAD; 310 dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n", 311 where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 312 313 ret = ixp4xx_pci_read_indirect(p, addr, cmd, &val); 314 if (ret) 315 return PCIBIOS_DEVICE_NOT_FOUND; 316 317 val >>= (8*n); 318 switch (size) { 319 case 1: 320 val &= U8_MAX; 321 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 322 break; 323 case 2: 324 val &= U16_MAX; 325 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 326 break; 327 case 4: 328 val &= U32_MAX; 329 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 330 break; 331 default: 332 /* Should not happen */ 333 dev_err(p->dev, "%s illegal size\n", __func__); 334 return PCIBIOS_DEVICE_NOT_FOUND; 335 } 336 *value = val; 337 338 return PCIBIOS_SUCCESSFUL; 339 } 340 341 static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 342 int where, int size, u32 value) 343 { 344 struct ixp4xx_pci *p = bus->sysdata; 345 u32 n, addr, val, cmd; 346 u8 bus_num = bus->number; 347 int ret; 348 349 n = where % 4; 350 cmd = ixp4xx_byte_lane_enable_bits(n, size); 351 if (cmd == 0xffffffff) 352 return PCIBIOS_BAD_REGISTER_NUMBER; 353 354 addr = ixp4xx_config_addr(bus_num, devfn, where); 355 cmd |= NP_CMD_CONFIGWRITE; 356 val = value << (8*n); 357 358 dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n", 359 value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 360 361 ret = ixp4xx_pci_write_indirect(p, addr, cmd, val); 362 if (ret) 363 return PCIBIOS_DEVICE_NOT_FOUND; 364 365 return PCIBIOS_SUCCESSFUL; 366 } 367 368 static struct pci_ops ixp4xx_pci_ops = { 369 .read = ixp4xx_pci_read_config, 370 .write = ixp4xx_pci_write_config, 371 }; 372 373 static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr) 374 { 375 u8 base; 376 377 base = ((addr & 0xff000000) >> 24); 378 return (base << 24) | ((base + 1) << 16) 379 | ((base + 2) << 8) | (base + 3); 380 } 381 382 static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p) 383 { 384 struct device *dev = p->dev; 385 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 386 struct resource_entry *win; 387 struct resource *res; 388 phys_addr_t addr; 389 390 win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 391 if (win) { 392 u32 pcimembase; 393 394 res = win->res; 395 addr = res->start - win->offset; 396 397 if (res->flags & IORESOURCE_PREFETCH) 398 res->name = "IXP4xx PCI PRE-MEM"; 399 else 400 res->name = "IXP4xx PCI NON-PRE-MEM"; 401 402 dev_dbg(dev, "%s window %pR, bus addr %pa\n", 403 res->name, res, &addr); 404 if (resource_size(res) != SZ_64M) { 405 dev_err(dev, "memory range is not 64MB\n"); 406 return -EINVAL; 407 } 408 409 pcimembase = ixp4xx_pci_addr_to_64mconf(addr); 410 /* Commit configuration */ 411 ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase); 412 } else { 413 dev_err(dev, "no AHB memory mapping defined\n"); 414 } 415 416 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 417 if (win) { 418 res = win->res; 419 420 addr = pci_pio_to_address(res->start); 421 if (addr & 0xff) { 422 dev_err(dev, "IO mem at uneven address: %pa\n", &addr); 423 return -EINVAL; 424 } 425 426 res->name = "IXP4xx PCI IO MEM"; 427 /* 428 * Setup I/O space location for PCI->AHB access, the 429 * upper 24 bits of the address goes into the lower 430 * 24 bits of this register. 431 */ 432 ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8)); 433 } else { 434 dev_info(dev, "no IO space AHB memory mapping defined\n"); 435 } 436 437 return 0; 438 } 439 440 static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p) 441 { 442 struct device *dev = p->dev; 443 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 444 struct resource_entry *win; 445 struct resource *res; 446 phys_addr_t addr; 447 u32 ahbmembase; 448 449 win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); 450 if (win) { 451 res = win->res; 452 addr = res->start - win->offset; 453 454 if (resource_size(res) != SZ_64M) { 455 dev_err(dev, "DMA memory range is not 64MB\n"); 456 return -EINVAL; 457 } 458 459 dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr); 460 /* 461 * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits 462 * into each byte of the PCI_AHBMEMBASE register. 463 */ 464 ahbmembase = ixp4xx_pci_addr_to_64mconf(addr); 465 /* Commit AHB membase */ 466 ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase); 467 } else { 468 dev_err(dev, "no DMA memory range defined\n"); 469 } 470 471 return 0; 472 } 473 474 /* Only used to get context for abort handling */ 475 static struct ixp4xx_pci *ixp4xx_pci_abort_singleton; 476 477 static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, 478 struct pt_regs *regs) 479 { 480 struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; 481 u32 isr, status; 482 int ret; 483 484 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 485 ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); 486 if (ret) { 487 dev_err(p->dev, "unable to read abort status\n"); 488 return -EINVAL; 489 } 490 491 dev_err(p->dev, 492 "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", 493 addr, isr, status); 494 495 /* Make sure the Master Abort bit is reset */ 496 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 497 status |= PCI_STATUS_REC_MASTER_ABORT; 498 ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); 499 if (ret) 500 dev_err(p->dev, "unable to clear abort status bit\n"); 501 502 /* 503 * If it was an imprecise abort, then we need to correct the 504 * return address to be _after_ the instruction. 505 */ 506 if (fsr & (1 << 10)) { 507 dev_err(p->dev, "imprecise abort\n"); 508 regs->ARM_pc += 4; 509 } 510 511 return 0; 512 } 513 514 static int __init ixp4xx_pci_probe(struct platform_device *pdev) 515 { 516 struct device *dev = &pdev->dev; 517 struct device_node *np = dev->of_node; 518 struct ixp4xx_pci *p; 519 struct pci_host_bridge *host; 520 int ret; 521 u32 val; 522 phys_addr_t addr; 523 u32 basereg[4] = { 524 PCI_BASE_ADDRESS_0, 525 PCI_BASE_ADDRESS_1, 526 PCI_BASE_ADDRESS_2, 527 PCI_BASE_ADDRESS_3, 528 }; 529 int i; 530 531 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 532 if (!host) 533 return -ENOMEM; 534 535 host->ops = &ixp4xx_pci_ops; 536 p = pci_host_bridge_priv(host); 537 host->sysdata = p; 538 p->dev = dev; 539 dev_set_drvdata(dev, p); 540 541 /* 542 * Set up quirk for erratic behaviour in the 42x variant 543 * when accessing config space. 544 */ 545 if (of_device_is_compatible(np, "intel,ixp42x-pci")) { 546 p->errata_hammer = true; 547 dev_info(dev, "activate hammering errata\n"); 548 } 549 550 p->base = devm_platform_ioremap_resource(pdev, 0); 551 if (IS_ERR(p->base)) 552 return PTR_ERR(p->base); 553 554 val = ixp4xx_readl(p, IXP4XX_PCI_CSR); 555 p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); 556 dev_info(dev, "controller is in %s mode\n", 557 p->host_mode ? "host" : "option"); 558 559 /* Hook in our fault handler for PCI errors */ 560 ixp4xx_pci_abort_singleton = p; 561 hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, 562 "imprecise external abort"); 563 564 ret = ixp4xx_pci_parse_map_ranges(p); 565 if (ret) 566 return ret; 567 568 ret = ixp4xx_pci_parse_map_dma_ranges(p); 569 if (ret) 570 return ret; 571 572 /* This is only configured in host mode */ 573 if (p->host_mode) { 574 addr = __pa(PAGE_OFFSET); 575 /* This is a noop (0x00) but explains what is going on */ 576 addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; 577 578 for (i = 0; i < 4; i++) { 579 /* Write this directly into the config space */ 580 ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); 581 if (ret) 582 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); 583 else 584 dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); 585 addr += SZ_16M; 586 } 587 588 /* 589 * Enable CSR window at 64 MiB to allow PCI masters to continue 590 * prefetching past the 64 MiB boundary, if all AHB to PCI 591 * windows are consecutive. 592 */ 593 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); 594 if (ret) 595 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); 596 else 597 dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); 598 599 /* 600 * Put the IO memory window at the very end of physical memory 601 * at 0xfffffc00. This is when the system is trying to access IO 602 * memory over AHB. 603 */ 604 addr = 0xfffffc00; 605 addr |= PCI_BASE_ADDRESS_SPACE_IO; 606 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); 607 if (ret) 608 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); 609 else 610 dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); 611 612 /* 613 * Retry timeout to 0x80 614 * Transfer ready timeout to 0xff 615 */ 616 ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, 617 0x000080ff); 618 if (ret) 619 dev_err(dev, "failed to set up TRDY limit\n"); 620 else 621 dev_info(dev, "set TRDY limit to 0x80ff\n"); 622 } 623 624 /* Clear interrupts */ 625 val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; 626 ixp4xx_writel(p, IXP4XX_PCI_ISR, val); 627 628 /* 629 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 630 * generate PCI configuration cycles. Specify that the AHB bus is 631 * operating in big-endian mode. Set up byte lane swapping between 632 * little-endian PCI and the big-endian AHB bus. 633 */ 634 val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; 635 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 636 val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); 637 ixp4xx_writel(p, IXP4XX_PCI_CSR, val); 638 639 ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 640 if (ret) 641 dev_err(dev, "unable to initialize master and command memory\n"); 642 else 643 dev_info(dev, "initialized as master\n"); 644 645 pci_host_probe(host); 646 647 return 0; 648 } 649 650 static const struct of_device_id ixp4xx_pci_of_match[] = { 651 { 652 .compatible = "intel,ixp42x-pci", 653 }, 654 { 655 .compatible = "intel,ixp43x-pci", 656 }, 657 {}, 658 }; 659 660 /* 661 * This driver needs to be a builtin module with suppressed bind 662 * attributes since the probe() is initializing a hard exception 663 * handler and this can only be done from __init-tagged code 664 * sections. This module cannot be removed and inserted at all. 665 */ 666 static struct platform_driver ixp4xx_pci_driver = { 667 .driver = { 668 .name = "ixp4xx-pci", 669 .suppress_bind_attrs = true, 670 .of_match_table = ixp4xx_pci_of_match, 671 }, 672 }; 673 builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe); 674