1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Faraday Technology FTPC100 PCI Controller 4 * 5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini: 8 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com> 9 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 10 * Based on SL2312 PCI controller code 11 * Storlink (C) 2003 12 */ 13 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_pci.h> 22 #include <linux/pci.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/irqdomain.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/bitops.h> 28 #include <linux/irq.h> 29 #include <linux/clk.h> 30 31 #include "../pci.h" 32 33 /* 34 * Special configuration registers directly in the first few words 35 * in I/O space. 36 */ 37 #define PCI_IOSIZE 0x00 38 #define PCI_PROT 0x04 /* AHB protection */ 39 #define PCI_CTRL 0x08 /* PCI control signal */ 40 #define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */ 41 #define PCI_CONFIG 0x28 /* PCI configuration command register */ 42 #define PCI_DATA 0x2C 43 44 #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */ 45 #define FARADAY_PCI_PMC 0x40 /* Power management control */ 46 #define FARADAY_PCI_PMCSR 0x44 /* Power management status */ 47 #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */ 48 #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */ 49 #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */ 50 #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */ 51 #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */ 52 53 #define PCI_STATUS_66MHZ_CAPABLE BIT(21) 54 55 /* Bits 31..28 gives INTD..INTA status */ 56 #define PCI_CTRL2_INTSTS_SHIFT 28 57 #define PCI_CTRL2_INTMASK_CMDERR BIT(27) 58 #define PCI_CTRL2_INTMASK_PARERR BIT(26) 59 /* Bits 25..22 masks INTD..INTA */ 60 #define PCI_CTRL2_INTMASK_SHIFT 22 61 #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21) 62 #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20) 63 #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19) 64 #define PCI_CTRL2_INTMASK_RETRY4 BIT(18) 65 #define PCI_CTRL2_INTMASK_SERR_RX BIT(17) 66 #define PCI_CTRL2_INTMASK_PERR_RX BIT(16) 67 /* Bit 15 reserved */ 68 #define PCI_CTRL2_MSTPRI_REQ6 BIT(14) 69 #define PCI_CTRL2_MSTPRI_REQ5 BIT(13) 70 #define PCI_CTRL2_MSTPRI_REQ4 BIT(12) 71 #define PCI_CTRL2_MSTPRI_REQ3 BIT(11) 72 #define PCI_CTRL2_MSTPRI_REQ2 BIT(10) 73 #define PCI_CTRL2_MSTPRI_REQ1 BIT(9) 74 #define PCI_CTRL2_MSTPRI_REQ0 BIT(8) 75 /* Bits 7..4 reserved */ 76 /* Bits 3..0 TRDYW */ 77 78 /* 79 * Memory configs: 80 * Bit 31..20 defines the PCI side memory base 81 * Bit 19..16 (4 bits) defines the size per below 82 */ 83 #define FARADAY_PCI_MEMBASE_MASK 0xfff00000 84 #define FARADAY_PCI_MEMSIZE_1MB 0x0 85 #define FARADAY_PCI_MEMSIZE_2MB 0x1 86 #define FARADAY_PCI_MEMSIZE_4MB 0x2 87 #define FARADAY_PCI_MEMSIZE_8MB 0x3 88 #define FARADAY_PCI_MEMSIZE_16MB 0x4 89 #define FARADAY_PCI_MEMSIZE_32MB 0x5 90 #define FARADAY_PCI_MEMSIZE_64MB 0x6 91 #define FARADAY_PCI_MEMSIZE_128MB 0x7 92 #define FARADAY_PCI_MEMSIZE_256MB 0x8 93 #define FARADAY_PCI_MEMSIZE_512MB 0x9 94 #define FARADAY_PCI_MEMSIZE_1GB 0xa 95 #define FARADAY_PCI_MEMSIZE_2GB 0xb 96 #define FARADAY_PCI_MEMSIZE_SHIFT 16 97 98 /* 99 * The DMA base is set to 0x0 for all memory segments, it reflects the 100 * fact that the memory of the host system starts at 0x0. 101 */ 102 #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000 103 #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000 104 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000 105 106 /* Defines for PCI configuration command register */ 107 #define PCI_CONF_ENABLE BIT(31) 108 #define PCI_CONF_WHERE(r) ((r) & 0xFC) 109 #define PCI_CONF_BUS(b) (((b) & 0xFF) << 16) 110 #define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11) 111 #define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8) 112 113 /** 114 * struct faraday_pci_variant - encodes IP block differences 115 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller 116 * embedded in the host bridge. 117 */ 118 struct faraday_pci_variant { 119 bool cascaded_irq; 120 }; 121 122 struct faraday_pci { 123 struct device *dev; 124 void __iomem *base; 125 struct irq_domain *irqdomain; 126 struct pci_bus *bus; 127 struct clk *bus_clk; 128 }; 129 130 static int faraday_res_to_memcfg(resource_size_t mem_base, 131 resource_size_t mem_size, u32 *val) 132 { 133 u32 outval; 134 135 switch (mem_size) { 136 case SZ_1M: 137 outval = FARADAY_PCI_MEMSIZE_1MB; 138 break; 139 case SZ_2M: 140 outval = FARADAY_PCI_MEMSIZE_2MB; 141 break; 142 case SZ_4M: 143 outval = FARADAY_PCI_MEMSIZE_4MB; 144 break; 145 case SZ_8M: 146 outval = FARADAY_PCI_MEMSIZE_8MB; 147 break; 148 case SZ_16M: 149 outval = FARADAY_PCI_MEMSIZE_16MB; 150 break; 151 case SZ_32M: 152 outval = FARADAY_PCI_MEMSIZE_32MB; 153 break; 154 case SZ_64M: 155 outval = FARADAY_PCI_MEMSIZE_64MB; 156 break; 157 case SZ_128M: 158 outval = FARADAY_PCI_MEMSIZE_128MB; 159 break; 160 case SZ_256M: 161 outval = FARADAY_PCI_MEMSIZE_256MB; 162 break; 163 case SZ_512M: 164 outval = FARADAY_PCI_MEMSIZE_512MB; 165 break; 166 case SZ_1G: 167 outval = FARADAY_PCI_MEMSIZE_1GB; 168 break; 169 case SZ_2G: 170 outval = FARADAY_PCI_MEMSIZE_2GB; 171 break; 172 default: 173 return -EINVAL; 174 } 175 outval <<= FARADAY_PCI_MEMSIZE_SHIFT; 176 177 /* This is probably not good */ 178 if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK)) 179 pr_warn("truncated PCI memory base\n"); 180 /* Translate to bridge side address space */ 181 outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK); 182 pr_debug("Translated pci base @%pap, size %pap to config %08x\n", 183 &mem_base, &mem_size, outval); 184 185 *val = outval; 186 return 0; 187 } 188 189 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, 190 unsigned int fn, int config, int size, 191 u32 *value) 192 { 193 writel(PCI_CONF_BUS(bus_number) | 194 PCI_CONF_DEVICE(PCI_SLOT(fn)) | 195 PCI_CONF_FUNCTION(PCI_FUNC(fn)) | 196 PCI_CONF_WHERE(config) | 197 PCI_CONF_ENABLE, 198 p->base + PCI_CONFIG); 199 200 *value = readl(p->base + PCI_DATA); 201 202 if (size == 1) 203 *value = (*value >> (8 * (config & 3))) & 0xFF; 204 else if (size == 2) 205 *value = (*value >> (8 * (config & 3))) & 0xFFFF; 206 207 return PCIBIOS_SUCCESSFUL; 208 } 209 210 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn, 211 int config, int size, u32 *value) 212 { 213 struct faraday_pci *p = bus->sysdata; 214 215 dev_dbg(&bus->dev, 216 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 217 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); 218 219 return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value); 220 } 221 222 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, 223 unsigned int fn, int config, int size, 224 u32 value) 225 { 226 int ret = PCIBIOS_SUCCESSFUL; 227 228 writel(PCI_CONF_BUS(bus_number) | 229 PCI_CONF_DEVICE(PCI_SLOT(fn)) | 230 PCI_CONF_FUNCTION(PCI_FUNC(fn)) | 231 PCI_CONF_WHERE(config) | 232 PCI_CONF_ENABLE, 233 p->base + PCI_CONFIG); 234 235 switch (size) { 236 case 4: 237 writel(value, p->base + PCI_DATA); 238 break; 239 case 2: 240 writew(value, p->base + PCI_DATA + (config & 3)); 241 break; 242 case 1: 243 writeb(value, p->base + PCI_DATA + (config & 3)); 244 break; 245 default: 246 ret = PCIBIOS_BAD_REGISTER_NUMBER; 247 } 248 249 return ret; 250 } 251 252 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn, 253 int config, int size, u32 value) 254 { 255 struct faraday_pci *p = bus->sysdata; 256 257 dev_dbg(&bus->dev, 258 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 259 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); 260 261 return faraday_raw_pci_write_config(p, bus->number, fn, config, size, 262 value); 263 } 264 265 static struct pci_ops faraday_pci_ops = { 266 .read = faraday_pci_read_config, 267 .write = faraday_pci_write_config, 268 }; 269 270 static void faraday_pci_ack_irq(struct irq_data *d) 271 { 272 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 273 unsigned int reg; 274 275 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 276 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); 277 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT); 278 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 279 } 280 281 static void faraday_pci_mask_irq(struct irq_data *d) 282 { 283 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 284 unsigned int reg; 285 286 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 287 reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT) 288 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT)); 289 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 290 } 291 292 static void faraday_pci_unmask_irq(struct irq_data *d) 293 { 294 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 295 unsigned int reg; 296 297 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 298 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); 299 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT); 300 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 301 } 302 303 static void faraday_pci_irq_handler(struct irq_desc *desc) 304 { 305 struct faraday_pci *p = irq_desc_get_handler_data(desc); 306 struct irq_chip *irqchip = irq_desc_get_chip(desc); 307 unsigned int irq_stat, reg, i; 308 309 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 310 irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT; 311 312 chained_irq_enter(irqchip, desc); 313 314 for (i = 0; i < 4; i++) { 315 if ((irq_stat & BIT(i)) == 0) 316 continue; 317 generic_handle_irq(irq_find_mapping(p->irqdomain, i)); 318 } 319 320 chained_irq_exit(irqchip, desc); 321 } 322 323 static struct irq_chip faraday_pci_irq_chip = { 324 .name = "PCI", 325 .irq_ack = faraday_pci_ack_irq, 326 .irq_mask = faraday_pci_mask_irq, 327 .irq_unmask = faraday_pci_unmask_irq, 328 }; 329 330 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq, 331 irq_hw_number_t hwirq) 332 { 333 irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq); 334 irq_set_chip_data(irq, domain->host_data); 335 336 return 0; 337 } 338 339 static const struct irq_domain_ops faraday_pci_irqdomain_ops = { 340 .map = faraday_pci_irq_map, 341 }; 342 343 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p) 344 { 345 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL); 346 int irq; 347 int i; 348 349 if (!intc) { 350 dev_err(p->dev, "missing child interrupt-controller node\n"); 351 return -EINVAL; 352 } 353 354 /* All PCI IRQs cascade off this one */ 355 irq = of_irq_get(intc, 0); 356 if (irq <= 0) { 357 dev_err(p->dev, "failed to get parent IRQ\n"); 358 return irq ?: -EINVAL; 359 } 360 361 p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX, 362 &faraday_pci_irqdomain_ops, p); 363 if (!p->irqdomain) { 364 dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n"); 365 return -EINVAL; 366 } 367 368 irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p); 369 370 for (i = 0; i < 4; i++) 371 irq_create_mapping(p->irqdomain, i); 372 373 return 0; 374 } 375 376 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p, 377 struct device_node *np) 378 { 379 struct of_pci_range range; 380 struct of_pci_range_parser parser; 381 struct device *dev = p->dev; 382 u32 confreg[3] = { 383 FARADAY_PCI_MEM1_BASE_SIZE, 384 FARADAY_PCI_MEM2_BASE_SIZE, 385 FARADAY_PCI_MEM3_BASE_SIZE, 386 }; 387 int i = 0; 388 u32 val; 389 390 if (of_pci_dma_range_parser_init(&parser, np)) { 391 dev_err(dev, "missing dma-ranges property\n"); 392 return -EINVAL; 393 } 394 395 /* 396 * Get the dma-ranges from the device tree 397 */ 398 for_each_of_pci_range(&parser, &range) { 399 u64 end = range.pci_addr + range.size - 1; 400 int ret; 401 402 ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val); 403 if (ret) { 404 dev_err(dev, 405 "DMA range %d: illegal MEM resource size\n", i); 406 return -EINVAL; 407 } 408 409 dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n", 410 i + 1, range.pci_addr, end, val); 411 if (i <= 2) { 412 faraday_raw_pci_write_config(p, 0, 0, confreg[i], 413 4, val); 414 } else { 415 dev_err(dev, "ignore extraneous dma-range %d\n", i); 416 break; 417 } 418 419 i++; 420 } 421 422 return 0; 423 } 424 425 static int faraday_pci_probe(struct platform_device *pdev) 426 { 427 struct device *dev = &pdev->dev; 428 const struct faraday_pci_variant *variant = 429 of_device_get_match_data(dev); 430 struct resource *regs; 431 resource_size_t io_base; 432 struct resource_entry *win; 433 struct faraday_pci *p; 434 struct resource *mem; 435 struct resource *io; 436 struct pci_host_bridge *host; 437 struct clk *clk; 438 unsigned char max_bus_speed = PCI_SPEED_33MHz; 439 unsigned char cur_bus_speed = PCI_SPEED_33MHz; 440 int ret; 441 u32 val; 442 LIST_HEAD(res); 443 444 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 445 if (!host) 446 return -ENOMEM; 447 448 host->dev.parent = dev; 449 host->ops = &faraday_pci_ops; 450 host->busnr = 0; 451 host->msi = NULL; 452 host->map_irq = of_irq_parse_and_map_pci; 453 host->swizzle_irq = pci_common_swizzle; 454 p = pci_host_bridge_priv(host); 455 host->sysdata = p; 456 p->dev = dev; 457 458 /* Retrieve and enable optional clocks */ 459 clk = devm_clk_get(dev, "PCLK"); 460 if (IS_ERR(clk)) 461 return PTR_ERR(clk); 462 ret = clk_prepare_enable(clk); 463 if (ret) { 464 dev_err(dev, "could not prepare PCLK\n"); 465 return ret; 466 } 467 p->bus_clk = devm_clk_get(dev, "PCICLK"); 468 if (IS_ERR(p->bus_clk)) 469 return PTR_ERR(p->bus_clk); 470 ret = clk_prepare_enable(p->bus_clk); 471 if (ret) { 472 dev_err(dev, "could not prepare PCICLK\n"); 473 return ret; 474 } 475 476 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 477 p->base = devm_ioremap_resource(dev, regs); 478 if (IS_ERR(p->base)) 479 return PTR_ERR(p->base); 480 481 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 482 &res, &io_base); 483 if (ret) 484 return ret; 485 486 ret = devm_request_pci_bus_resources(dev, &res); 487 if (ret) 488 return ret; 489 490 /* Get the I/O and memory ranges from DT */ 491 resource_list_for_each_entry(win, &res) { 492 switch (resource_type(win->res)) { 493 case IORESOURCE_IO: 494 io = win->res; 495 io->name = "Gemini PCI I/O"; 496 if (!faraday_res_to_memcfg(io->start - win->offset, 497 resource_size(io), &val)) { 498 /* setup I/O space size */ 499 writel(val, p->base + PCI_IOSIZE); 500 } else { 501 dev_err(dev, "illegal IO mem size\n"); 502 return -EINVAL; 503 } 504 ret = pci_remap_iospace(io, io_base); 505 if (ret) { 506 dev_warn(dev, "error %d: failed to map resource %pR\n", 507 ret, io); 508 continue; 509 } 510 break; 511 case IORESOURCE_MEM: 512 mem = win->res; 513 mem->name = "Gemini PCI MEM"; 514 break; 515 case IORESOURCE_BUS: 516 break; 517 default: 518 break; 519 } 520 } 521 522 /* Setup hostbridge */ 523 val = readl(p->base + PCI_CTRL); 524 val |= PCI_COMMAND_IO; 525 val |= PCI_COMMAND_MEMORY; 526 val |= PCI_COMMAND_MASTER; 527 writel(val, p->base + PCI_CTRL); 528 /* Mask and clear all interrupts */ 529 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000); 530 if (variant->cascaded_irq) { 531 ret = faraday_pci_setup_cascaded_irq(p); 532 if (ret) { 533 dev_err(dev, "failed to setup cascaded IRQ\n"); 534 return ret; 535 } 536 } 537 538 /* Check bus clock if we can gear up to 66 MHz */ 539 if (!IS_ERR(p->bus_clk)) { 540 unsigned long rate; 541 u32 val; 542 543 faraday_raw_pci_read_config(p, 0, 0, 544 FARADAY_PCI_STATUS_CMD, 4, &val); 545 rate = clk_get_rate(p->bus_clk); 546 547 if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) { 548 dev_info(dev, "33MHz bus is 66MHz capable\n"); 549 max_bus_speed = PCI_SPEED_66MHz; 550 ret = clk_set_rate(p->bus_clk, 66000000); 551 if (ret) 552 dev_err(dev, "failed to set bus clock\n"); 553 } else { 554 dev_info(dev, "33MHz only bus\n"); 555 max_bus_speed = PCI_SPEED_33MHz; 556 } 557 558 /* Bumping the clock may fail so read back the rate */ 559 rate = clk_get_rate(p->bus_clk); 560 if (rate == 33000000) 561 cur_bus_speed = PCI_SPEED_33MHz; 562 if (rate == 66000000) 563 cur_bus_speed = PCI_SPEED_66MHz; 564 } 565 566 ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node); 567 if (ret) 568 return ret; 569 570 list_splice_init(&res, &host->windows); 571 ret = pci_scan_root_bus_bridge(host); 572 if (ret) { 573 dev_err(dev, "failed to scan host: %d\n", ret); 574 return ret; 575 } 576 p->bus = host->bus; 577 p->bus->max_bus_speed = max_bus_speed; 578 p->bus->cur_bus_speed = cur_bus_speed; 579 580 pci_bus_assign_resources(p->bus); 581 pci_bus_add_devices(p->bus); 582 pci_free_resource_list(&res); 583 584 return 0; 585 } 586 587 /* 588 * We encode bridge variants here, we have at least two so it doesn't 589 * hurt to have infrastructure to encompass future variants as well. 590 */ 591 static const struct faraday_pci_variant faraday_regular = { 592 .cascaded_irq = true, 593 }; 594 595 static const struct faraday_pci_variant faraday_dual = { 596 .cascaded_irq = false, 597 }; 598 599 static const struct of_device_id faraday_pci_of_match[] = { 600 { 601 .compatible = "faraday,ftpci100", 602 .data = &faraday_regular, 603 }, 604 { 605 .compatible = "faraday,ftpci100-dual", 606 .data = &faraday_dual, 607 }, 608 {}, 609 }; 610 611 static struct platform_driver faraday_pci_driver = { 612 .driver = { 613 .name = "ftpci100", 614 .of_match_table = of_match_ptr(faraday_pci_of_match), 615 .suppress_bind_attrs = true, 616 }, 617 .probe = faraday_pci_probe, 618 }; 619 builtin_platform_driver(faraday_pci_driver); 620