1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/init.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/msi.h> 24 #include <linux/of_address.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_pci.h> 27 28 #include "../pci.h" 29 #include "../pci-bridge-emul.h" 30 31 /* PCIe core registers */ 32 #define PCIE_CORE_DEV_ID_REG 0x0 33 #define PCIE_CORE_CMD_STATUS_REG 0x4 34 #define PCIE_CORE_DEV_REV_REG 0x8 35 #define PCIE_CORE_PCIEXP_CAP 0xc0 36 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 41 /* PIO registers base address and register offsets */ 42 #define PIO_BASE_ADDR 0x4000 43 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 44 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 45 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 46 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 47 #define PIO_COMPLETION_STATUS_SHIFT 7 48 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 49 #define PIO_COMPLETION_STATUS_OK 0 50 #define PIO_COMPLETION_STATUS_UR 1 51 #define PIO_COMPLETION_STATUS_CRS 2 52 #define PIO_COMPLETION_STATUS_CA 4 53 #define PIO_NON_POSTED_REQ BIT(10) 54 #define PIO_ERR_STATUS BIT(11) 55 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 56 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 57 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 58 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 59 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 60 #define PIO_START (PIO_BASE_ADDR + 0x1c) 61 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 62 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 63 64 /* Aardvark Control registers */ 65 #define CONTROL_BASE_ADDR 0x4800 66 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 67 #define PCIE_GEN_SEL_MSK 0x3 68 #define PCIE_GEN_SEL_SHIFT 0x0 69 #define SPEED_GEN_1 0 70 #define SPEED_GEN_2 1 71 #define SPEED_GEN_3 2 72 #define IS_RC_MSK 1 73 #define IS_RC_SHIFT 2 74 #define LANE_CNT_MSK 0x18 75 #define LANE_CNT_SHIFT 0x3 76 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 77 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 78 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 79 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 80 #define LINK_TRAINING_EN BIT(6) 81 #define LEGACY_INTA BIT(28) 82 #define LEGACY_INTB BIT(29) 83 #define LEGACY_INTC BIT(30) 84 #define LEGACY_INTD BIT(31) 85 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 86 #define HOT_RESET_GEN BIT(0) 87 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 88 #define PCIE_CORE_CTRL2_RESERVED 0x7 89 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 90 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 91 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 92 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 93 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) 94 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) 95 #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2) 96 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 97 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 98 #define PCIE_MSG_PM_PME_MASK BIT(7) 99 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 100 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 101 #define PCIE_ISR0_CORR_ERR BIT(11) 102 #define PCIE_ISR0_NFAT_ERR BIT(12) 103 #define PCIE_ISR0_FAT_ERR BIT(13) 104 #define PCIE_ISR0_ERR_MASK GENMASK(13, 11) 105 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 106 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 107 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) 108 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 109 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 110 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 111 #define PCIE_ISR1_FLUSH BIT(5) 112 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 113 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0) 114 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 115 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 116 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 117 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 118 #define PCIE_MSI_ALL_MASK GENMASK(31, 0) 119 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 120 #define PCIE_MSI_DATA_MASK GENMASK(15, 0) 121 122 /* PCIe window configuration */ 123 #define OB_WIN_BASE_ADDR 0x4c00 124 #define OB_WIN_BLOCK_SIZE 0x20 125 #define OB_WIN_COUNT 8 126 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ 127 OB_WIN_BLOCK_SIZE * (win) + \ 128 (offset)) 129 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) 130 #define OB_WIN_ENABLE BIT(0) 131 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) 132 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) 133 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) 134 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) 135 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) 136 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) 137 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) 138 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) 139 #define OB_WIN_FUNC_NUM_SHIFT 24 140 #define OB_WIN_FUNC_NUM_ENABLE BIT(23) 141 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) 142 #define OB_WIN_BUS_NUM_BITS_SHIFT 20 143 #define OB_WIN_MSG_CODE_ENABLE BIT(22) 144 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) 145 #define OB_WIN_MSG_CODE_SHIFT 14 146 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12) 147 #define OB_WIN_ATTR_ENABLE BIT(11) 148 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) 149 #define OB_WIN_ATTR_TC_SHIFT 8 150 #define OB_WIN_ATTR_RELAXED BIT(7) 151 #define OB_WIN_ATTR_NOSNOOP BIT(6) 152 #define OB_WIN_ATTR_POISON BIT(5) 153 #define OB_WIN_ATTR_IDO BIT(4) 154 #define OB_WIN_TYPE_MASK GENMASK(3, 0) 155 #define OB_WIN_TYPE_SHIFT 0 156 #define OB_WIN_TYPE_MEM 0x0 157 #define OB_WIN_TYPE_IO 0x4 158 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8 159 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9 160 #define OB_WIN_TYPE_MSG 0xc 161 162 /* LMI registers base address and register offsets */ 163 #define LMI_BASE_ADDR 0x6000 164 #define CFG_REG (LMI_BASE_ADDR + 0x0) 165 #define LTSSM_SHIFT 24 166 #define LTSSM_MASK 0x3f 167 #define RC_BAR_CONFIG 0x300 168 169 /* LTSSM values in CFG_REG */ 170 enum { 171 LTSSM_DETECT_QUIET = 0x0, 172 LTSSM_DETECT_ACTIVE = 0x1, 173 LTSSM_POLLING_ACTIVE = 0x2, 174 LTSSM_POLLING_COMPLIANCE = 0x3, 175 LTSSM_POLLING_CONFIGURATION = 0x4, 176 LTSSM_CONFIG_LINKWIDTH_START = 0x5, 177 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6, 178 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7, 179 LTSSM_CONFIG_LANENUM_WAIT = 0x8, 180 LTSSM_CONFIG_COMPLETE = 0x9, 181 LTSSM_CONFIG_IDLE = 0xa, 182 LTSSM_RECOVERY_RCVR_LOCK = 0xb, 183 LTSSM_RECOVERY_SPEED = 0xc, 184 LTSSM_RECOVERY_RCVR_CFG = 0xd, 185 LTSSM_RECOVERY_IDLE = 0xe, 186 LTSSM_L0 = 0x10, 187 LTSSM_RX_L0S_ENTRY = 0x11, 188 LTSSM_RX_L0S_IDLE = 0x12, 189 LTSSM_RX_L0S_FTS = 0x13, 190 LTSSM_TX_L0S_ENTRY = 0x14, 191 LTSSM_TX_L0S_IDLE = 0x15, 192 LTSSM_TX_L0S_FTS = 0x16, 193 LTSSM_L1_ENTRY = 0x17, 194 LTSSM_L1_IDLE = 0x18, 195 LTSSM_L2_IDLE = 0x19, 196 LTSSM_L2_TRANSMIT_WAKE = 0x1a, 197 LTSSM_DISABLED = 0x20, 198 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21, 199 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22, 200 LTSSM_LOOPBACK_EXIT_MASTER = 0x23, 201 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24, 202 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25, 203 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26, 204 LTSSM_HOT_RESET = 0x27, 205 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28, 206 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29, 207 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a, 208 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b, 209 }; 210 211 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) 212 213 /* PCIe core controller registers */ 214 #define CTRL_CORE_BASE_ADDR 0x18000 215 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 216 #define CTRL_MODE_SHIFT 0x0 217 #define CTRL_MODE_MASK 0x1 218 #define PCIE_CORE_MODE_DIRECT 0x0 219 #define PCIE_CORE_MODE_COMMAND 0x1 220 221 /* PCIe Central Interrupts Registers */ 222 #define CENTRAL_INT_BASE_ADDR 0x1b000 223 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 224 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 225 #define PCIE_IRQ_CMDQ_INT BIT(0) 226 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 227 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 228 #define PCIE_IRQ_DMA_INT BIT(4) 229 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 230 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 231 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 232 #define PCIE_IRQ_COMPQ_INT BIT(12) 233 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 234 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 235 #define PCIE_IRQ_CORE_INT BIT(16) 236 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 237 #define PCIE_IRQ_DPMU_INT BIT(18) 238 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 239 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 240 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 241 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 242 #define PCIE_IRQ_EP_STATUS BIT(23) 243 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0) 244 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 245 246 /* Transaction types */ 247 #define PCIE_CONFIG_RD_TYPE0 0x8 248 #define PCIE_CONFIG_RD_TYPE1 0x9 249 #define PCIE_CONFIG_WR_TYPE0 0xa 250 #define PCIE_CONFIG_WR_TYPE1 0xb 251 252 #define PIO_RETRY_CNT 750000 /* 1.5 s */ 253 #define PIO_RETRY_DELAY 2 /* 2 us*/ 254 255 #define LINK_WAIT_MAX_RETRIES 10 256 #define LINK_WAIT_USLEEP_MIN 90000 257 #define LINK_WAIT_USLEEP_MAX 100000 258 #define RETRAIN_WAIT_MAX_RETRIES 10 259 #define RETRAIN_WAIT_USLEEP_US 2000 260 261 #define MSI_IRQ_NUM 32 262 263 #define CFG_RD_CRS_VAL 0xffff0001 264 265 struct advk_pcie { 266 struct platform_device *pdev; 267 void __iomem *base; 268 struct { 269 phys_addr_t match; 270 phys_addr_t remap; 271 phys_addr_t mask; 272 u32 actions; 273 } wins[OB_WIN_COUNT]; 274 u8 wins_count; 275 int irq; 276 struct irq_domain *rp_irq_domain; 277 struct irq_domain *irq_domain; 278 struct irq_chip irq_chip; 279 raw_spinlock_t irq_lock; 280 struct irq_domain *msi_domain; 281 struct irq_domain *msi_inner_domain; 282 raw_spinlock_t msi_irq_lock; 283 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 284 struct mutex msi_used_lock; 285 int link_gen; 286 struct pci_bridge_emul bridge; 287 struct gpio_desc *reset_gpio; 288 struct phy *phy; 289 }; 290 291 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 292 { 293 writel(val, pcie->base + reg); 294 } 295 296 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 297 { 298 return readl(pcie->base + reg); 299 } 300 301 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) 302 { 303 u32 val; 304 u8 ltssm_state; 305 306 val = advk_readl(pcie, CFG_REG); 307 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 308 return ltssm_state; 309 } 310 311 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) 312 { 313 /* check if LTSSM is in normal operation - some L* state */ 314 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 315 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; 316 } 317 318 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) 319 { 320 /* 321 * According to PCIe Base specification 3.0, Table 4-14: Link 322 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle 323 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, 324 * L0s, L1 and L2 states. And according to 3.2.1. Data Link 325 * Control and Management State Machine Rules is DL Up status 326 * reported in DL Active state. 327 */ 328 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 329 return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED; 330 } 331 332 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) 333 { 334 /* 335 * According to PCIe Base specification 3.0, Table 4-14: Link 336 * Status Mapped to the LTSSM is Link Training mapped to LTSSM 337 * Configuration and Recovery states. 338 */ 339 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 340 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START && 341 ltssm_state < LTSSM_L0) || 342 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 && 343 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3)); 344 } 345 346 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 347 { 348 int retries; 349 350 /* check if the link is up or not */ 351 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 352 if (advk_pcie_link_up(pcie)) 353 return 0; 354 355 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 356 } 357 358 return -ETIMEDOUT; 359 } 360 361 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 362 { 363 size_t retries; 364 365 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 366 if (advk_pcie_link_training(pcie)) 367 break; 368 udelay(RETRAIN_WAIT_USLEEP_US); 369 } 370 } 371 372 static void advk_pcie_issue_perst(struct advk_pcie *pcie) 373 { 374 if (!pcie->reset_gpio) 375 return; 376 377 /* 10ms delay is needed for some cards */ 378 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); 379 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 380 usleep_range(10000, 11000); 381 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 382 } 383 384 static void advk_pcie_train_link(struct advk_pcie *pcie) 385 { 386 struct device *dev = &pcie->pdev->dev; 387 u32 reg; 388 int ret; 389 390 /* 391 * Setup PCIe rev / gen compliance based on device tree property 392 * 'max-link-speed' which also forces maximal link speed. 393 */ 394 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 395 reg &= ~PCIE_GEN_SEL_MSK; 396 if (pcie->link_gen == 3) 397 reg |= SPEED_GEN_3; 398 else if (pcie->link_gen == 2) 399 reg |= SPEED_GEN_2; 400 else 401 reg |= SPEED_GEN_1; 402 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 403 404 /* 405 * Set maximal link speed value also into PCIe Link Control 2 register. 406 * Armada 3700 Functional Specification says that default value is based 407 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s. 408 */ 409 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 410 reg &= ~PCI_EXP_LNKCTL2_TLS; 411 if (pcie->link_gen == 3) 412 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT; 413 else if (pcie->link_gen == 2) 414 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT; 415 else 416 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT; 417 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 418 419 /* Enable link training after selecting PCIe generation */ 420 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 421 reg |= LINK_TRAINING_EN; 422 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 423 424 /* 425 * Reset PCIe card via PERST# signal. Some cards are not detected 426 * during link training when they are in some non-initial state. 427 */ 428 advk_pcie_issue_perst(pcie); 429 430 /* 431 * PERST# signal could have been asserted by pinctrl subsystem before 432 * probe() callback has been called or issued explicitly by reset gpio 433 * function advk_pcie_issue_perst(), making the endpoint going into 434 * fundamental reset. As required by PCI Express spec (PCI Express 435 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1 436 * Conventional Reset) a delay for at least 100ms after such a reset 437 * before sending a Configuration Request to the device is needed. 438 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() 439 * waits for link at least 900ms. 440 */ 441 ret = advk_pcie_wait_for_link(pcie); 442 if (ret < 0) 443 dev_err(dev, "link never came up\n"); 444 else 445 dev_info(dev, "link up\n"); 446 } 447 448 /* 449 * Set PCIe address window register which could be used for memory 450 * mapping. 451 */ 452 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, 453 phys_addr_t match, phys_addr_t remap, 454 phys_addr_t mask, u32 actions) 455 { 456 advk_writel(pcie, OB_WIN_ENABLE | 457 lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); 458 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); 459 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); 460 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); 461 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); 462 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); 463 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); 464 } 465 466 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) 467 { 468 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); 469 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); 470 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); 471 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); 472 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); 473 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); 474 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); 475 } 476 477 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 478 { 479 phys_addr_t msi_addr; 480 u32 reg; 481 int i; 482 483 /* 484 * Configure PCIe Reference clock. Direction is from the PCIe 485 * controller to the endpoint card, so enable transmitting of 486 * Reference clock differential signal off-chip and disable 487 * receiving off-chip differential signal. 488 */ 489 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); 490 reg |= PCIE_CORE_REF_CLK_TX_ENABLE; 491 reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE; 492 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); 493 494 /* Set to Direct mode */ 495 reg = advk_readl(pcie, CTRL_CONFIG_REG); 496 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 497 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 498 advk_writel(pcie, reg, CTRL_CONFIG_REG); 499 500 /* Set PCI global control register to RC mode */ 501 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 502 reg |= (IS_RC_MSK << IS_RC_SHIFT); 503 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 504 505 /* 506 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. 507 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor 508 * id in high 16 bits. Updating this register changes readback value of 509 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround 510 * for erratum 4.1: "The value of device and vendor ID is incorrect". 511 */ 512 reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; 513 advk_writel(pcie, reg, VENDOR_ID_REG); 514 515 /* 516 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), 517 * because the default value is Mass storage controller (0x010400). 518 * 519 * Note that this Aardvark PCI Bridge does not have compliant Type 1 520 * Configuration Space and it even cannot be accessed via Aardvark's 521 * PCI config space access method. Something like config space is 522 * available in internal Aardvark registers starting at offset 0x0 523 * and is reported as Type 0. In range 0x10 - 0x34 it has totally 524 * different registers. 525 * 526 * Therefore driver uses emulation of PCI Bridge which emulates 527 * access to configuration space via internal Aardvark registers or 528 * emulated configuration buffer. 529 */ 530 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); 531 reg &= ~0xffffff00; 532 reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; 533 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); 534 535 /* Disable Root Bridge I/O space, memory space and bus mastering */ 536 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 537 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 538 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 539 540 /* Set Advanced Error Capabilities and Control PF0 register */ 541 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 542 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 543 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 544 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 545 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 546 547 /* Set PCIe Device Control register */ 548 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 549 reg &= ~PCI_EXP_DEVCTL_RELAX_EN; 550 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 551 reg &= ~PCI_EXP_DEVCTL_PAYLOAD; 552 reg &= ~PCI_EXP_DEVCTL_READRQ; 553 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; 554 reg |= PCI_EXP_DEVCTL_READRQ_512B; 555 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 556 557 /* Program PCIe Control 2 to disable strict ordering */ 558 reg = PCIE_CORE_CTRL2_RESERVED | 559 PCIE_CORE_CTRL2_TD_ENABLE; 560 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 561 562 /* Set lane X1 */ 563 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 564 reg &= ~LANE_CNT_MSK; 565 reg |= LANE_COUNT_1; 566 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 567 568 /* Set MSI address */ 569 msi_addr = virt_to_phys(pcie); 570 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); 571 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); 572 573 /* Enable MSI */ 574 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 575 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 576 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 577 578 /* Clear all interrupts */ 579 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); 580 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 581 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 582 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 583 584 /* Disable All ISR0/1 and MSI Sources */ 585 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); 586 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 587 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); 588 589 /* Unmask summary MSI interrupt */ 590 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); 591 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 592 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 593 594 /* Unmask PME interrupt for processing of PME requester */ 595 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); 596 reg &= ~PCIE_MSG_PM_PME_MASK; 597 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 598 599 /* Enable summary interrupt for GIC SPI source */ 600 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 601 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 602 603 /* 604 * Enable AXI address window location generation: 605 * When it is enabled, the default outbound window 606 * configurations (Default User Field: 0xD0074CFC) 607 * are used to transparent address translation for 608 * the outbound transactions. Thus, PCIe address 609 * windows are not required for transparent memory 610 * access when default outbound window configuration 611 * is set for memory access. 612 */ 613 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 614 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 615 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 616 617 /* 618 * Set memory access in Default User Field so it 619 * is not required to configure PCIe address for 620 * transparent memory access. 621 */ 622 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); 623 624 /* 625 * Bypass the address window mapping for PIO: 626 * Since PIO access already contains all required 627 * info over AXI interface by PIO registers, the 628 * address window is not required. 629 */ 630 reg = advk_readl(pcie, PIO_CTRL); 631 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 632 advk_writel(pcie, reg, PIO_CTRL); 633 634 /* 635 * Configure PCIe address windows for non-memory or 636 * non-transparent access as by default PCIe uses 637 * transparent memory access. 638 */ 639 for (i = 0; i < pcie->wins_count; i++) 640 advk_pcie_set_ob_win(pcie, i, 641 pcie->wins[i].match, pcie->wins[i].remap, 642 pcie->wins[i].mask, pcie->wins[i].actions); 643 644 /* Disable remaining PCIe outbound windows */ 645 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) 646 advk_pcie_disable_ob_win(pcie, i); 647 648 advk_pcie_train_link(pcie); 649 } 650 651 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) 652 { 653 struct device *dev = &pcie->pdev->dev; 654 u32 reg; 655 unsigned int status; 656 char *strcomp_status, *str_posted; 657 int ret; 658 659 reg = advk_readl(pcie, PIO_STAT); 660 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 661 PIO_COMPLETION_STATUS_SHIFT; 662 663 /* 664 * According to HW spec, the PIO status check sequence as below: 665 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, 666 * it still needs to check Error Status(bit11), only when this bit 667 * indicates no error happen, the operation is successful. 668 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only 669 * means a PIO write error, and for PIO read it is successful with 670 * a read value of 0xFFFFFFFF. 671 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) 672 * only means a PIO write error, and for PIO read it is successful 673 * with a read value of 0xFFFF0001. 674 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means 675 * error for both PIO read and PIO write operation. 676 * 5) other errors are indicated as 'unknown'. 677 */ 678 switch (status) { 679 case PIO_COMPLETION_STATUS_OK: 680 if (reg & PIO_ERR_STATUS) { 681 strcomp_status = "COMP_ERR"; 682 ret = -EFAULT; 683 break; 684 } 685 /* Get the read result */ 686 if (val) 687 *val = advk_readl(pcie, PIO_RD_DATA); 688 /* No error */ 689 strcomp_status = NULL; 690 ret = 0; 691 break; 692 case PIO_COMPLETION_STATUS_UR: 693 strcomp_status = "UR"; 694 ret = -EOPNOTSUPP; 695 break; 696 case PIO_COMPLETION_STATUS_CRS: 697 if (allow_crs && val) { 698 /* PCIe r4.0, sec 2.3.2, says: 699 * If CRS Software Visibility is enabled: 700 * For a Configuration Read Request that includes both 701 * bytes of the Vendor ID field of a device Function's 702 * Configuration Space Header, the Root Complex must 703 * complete the Request to the host by returning a 704 * read-data value of 0001h for the Vendor ID field and 705 * all '1's for any additional bytes included in the 706 * request. 707 * 708 * So CRS in this case is not an error status. 709 */ 710 *val = CFG_RD_CRS_VAL; 711 strcomp_status = NULL; 712 ret = 0; 713 break; 714 } 715 /* PCIe r4.0, sec 2.3.2, says: 716 * If CRS Software Visibility is not enabled, the Root Complex 717 * must re-issue the Configuration Request as a new Request. 718 * If CRS Software Visibility is enabled: For a Configuration 719 * Write Request or for any other Configuration Read Request, 720 * the Root Complex must re-issue the Configuration Request as 721 * a new Request. 722 * A Root Complex implementation may choose to limit the number 723 * of Configuration Request/CRS Completion Status loops before 724 * determining that something is wrong with the target of the 725 * Request and taking appropriate action, e.g., complete the 726 * Request to the host as a failed transaction. 727 * 728 * So return -EAGAIN and caller (pci-aardvark.c driver) will 729 * re-issue request again up to the PIO_RETRY_CNT retries. 730 */ 731 strcomp_status = "CRS"; 732 ret = -EAGAIN; 733 break; 734 case PIO_COMPLETION_STATUS_CA: 735 strcomp_status = "CA"; 736 ret = -ECANCELED; 737 break; 738 default: 739 strcomp_status = "Unknown"; 740 ret = -EINVAL; 741 break; 742 } 743 744 if (!strcomp_status) 745 return ret; 746 747 if (reg & PIO_NON_POSTED_REQ) 748 str_posted = "Non-posted"; 749 else 750 str_posted = "Posted"; 751 752 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 753 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 754 755 return ret; 756 } 757 758 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 759 { 760 struct device *dev = &pcie->pdev->dev; 761 int i; 762 763 for (i = 1; i <= PIO_RETRY_CNT; i++) { 764 u32 start, isr; 765 766 start = advk_readl(pcie, PIO_START); 767 isr = advk_readl(pcie, PIO_ISR); 768 if (!start && isr) 769 return i; 770 udelay(PIO_RETRY_DELAY); 771 } 772 773 dev_err(dev, "PIO read/write transfer time out\n"); 774 return -ETIMEDOUT; 775 } 776 777 static pci_bridge_emul_read_status_t 778 advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 779 int reg, u32 *value) 780 { 781 struct advk_pcie *pcie = bridge->data; 782 783 switch (reg) { 784 case PCI_COMMAND: 785 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 786 return PCI_BRIDGE_EMUL_HANDLED; 787 788 case PCI_INTERRUPT_LINE: { 789 /* 790 * From the whole 32bit register we support reading from HW only 791 * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR. 792 * Other bits are retrieved only from emulated config buffer. 793 */ 794 __le32 *cfgspace = (__le32 *)&bridge->conf; 795 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); 796 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) 797 val &= ~(PCI_BRIDGE_CTL_SERR << 16); 798 else 799 val |= PCI_BRIDGE_CTL_SERR << 16; 800 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) 801 val |= PCI_BRIDGE_CTL_BUS_RESET << 16; 802 else 803 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); 804 *value = val; 805 return PCI_BRIDGE_EMUL_HANDLED; 806 } 807 808 default: 809 return PCI_BRIDGE_EMUL_NOT_HANDLED; 810 } 811 } 812 813 static void 814 advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 815 int reg, u32 old, u32 new, u32 mask) 816 { 817 struct advk_pcie *pcie = bridge->data; 818 819 switch (reg) { 820 case PCI_COMMAND: 821 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); 822 break; 823 824 case PCI_INTERRUPT_LINE: 825 /* 826 * According to Figure 6-3: Pseudo Logic Diagram for Error 827 * Message Controls in PCIe base specification, SERR# Enable bit 828 * in Bridge Control register enable receiving of ERR_* messages 829 */ 830 if (mask & (PCI_BRIDGE_CTL_SERR << 16)) { 831 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 832 if (new & (PCI_BRIDGE_CTL_SERR << 16)) 833 val &= ~PCIE_ISR0_ERR_MASK; 834 else 835 val |= PCIE_ISR0_ERR_MASK; 836 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 837 } 838 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { 839 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); 840 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) 841 val |= HOT_RESET_GEN; 842 else 843 val &= ~HOT_RESET_GEN; 844 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); 845 } 846 break; 847 848 default: 849 break; 850 } 851 } 852 853 static pci_bridge_emul_read_status_t 854 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 855 int reg, u32 *value) 856 { 857 struct advk_pcie *pcie = bridge->data; 858 859 860 switch (reg) { 861 case PCI_EXP_SLTCTL: 862 *value = PCI_EXP_SLTSTA_PDS << 16; 863 return PCI_BRIDGE_EMUL_HANDLED; 864 865 /* 866 * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need 867 * to be handled here, because their values are stored in emulated 868 * config space buffer, and we read them from there when needed. 869 */ 870 871 case PCI_EXP_LNKCAP: { 872 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 873 /* 874 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. 875 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm 876 * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag. 877 */ 878 val |= PCI_EXP_LNKCAP_DLLLARC; 879 *value = val; 880 return PCI_BRIDGE_EMUL_HANDLED; 881 } 882 883 case PCI_EXP_LNKCTL: { 884 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 885 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 886 ~(PCI_EXP_LNKSTA_LT << 16); 887 if (advk_pcie_link_training(pcie)) 888 val |= (PCI_EXP_LNKSTA_LT << 16); 889 if (advk_pcie_link_active(pcie)) 890 val |= (PCI_EXP_LNKSTA_DLLLA << 16); 891 *value = val; 892 return PCI_BRIDGE_EMUL_HANDLED; 893 } 894 895 case PCI_EXP_DEVCAP: 896 case PCI_EXP_DEVCTL: 897 case PCI_EXP_DEVCAP2: 898 case PCI_EXP_DEVCTL2: 899 case PCI_EXP_LNKCAP2: 900 case PCI_EXP_LNKCTL2: 901 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 902 return PCI_BRIDGE_EMUL_HANDLED; 903 904 default: 905 return PCI_BRIDGE_EMUL_NOT_HANDLED; 906 } 907 908 } 909 910 static void 911 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 912 int reg, u32 old, u32 new, u32 mask) 913 { 914 struct advk_pcie *pcie = bridge->data; 915 916 switch (reg) { 917 case PCI_EXP_LNKCTL: 918 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 919 if (new & PCI_EXP_LNKCTL_RL) 920 advk_pcie_wait_for_retrain(pcie); 921 break; 922 923 case PCI_EXP_RTCTL: { 924 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); 925 /* Only emulation of PMEIE and CRSSVE bits is provided */ 926 rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE; 927 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); 928 break; 929 } 930 931 /* 932 * PCI_EXP_RTSTA is also supported, but does not need to be handled 933 * here, because its value is stored in emulated config space buffer, 934 * and we write it there when needed. 935 */ 936 937 case PCI_EXP_DEVCTL: 938 case PCI_EXP_DEVCTL2: 939 case PCI_EXP_LNKCTL2: 940 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 941 break; 942 943 default: 944 break; 945 } 946 } 947 948 static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 949 .read_base = advk_pci_bridge_emul_base_conf_read, 950 .write_base = advk_pci_bridge_emul_base_conf_write, 951 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 952 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 953 }; 954 955 /* 956 * Initialize the configuration space of the PCI-to-PCI bridge 957 * associated with the given PCIe interface. 958 */ 959 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 960 { 961 struct pci_bridge_emul *bridge = &pcie->bridge; 962 963 bridge->conf.vendor = 964 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 965 bridge->conf.device = 966 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 967 bridge->conf.class_revision = 968 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 969 970 /* Support 32 bits I/O addressing */ 971 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 972 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 973 974 /* Support 64 bits memory pref */ 975 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 976 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 977 978 /* Support interrupt A for MSI feature */ 979 bridge->conf.intpin = PCI_INTERRUPT_INTA; 980 981 /* Aardvark HW provides PCIe Capability structure in version 2 */ 982 bridge->pcie_conf.cap = cpu_to_le16(2); 983 984 /* Indicates supports for Completion Retry Status */ 985 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); 986 987 bridge->has_pcie = true; 988 bridge->data = pcie; 989 bridge->ops = &advk_pci_bridge_emul_ops; 990 991 return pci_bridge_emul_init(bridge, 0); 992 } 993 994 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 995 int devfn) 996 { 997 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) 998 return false; 999 1000 /* 1001 * If the link goes down after we check for link-up, we have a problem: 1002 * if a PIO request is executed while link-down, the whole controller 1003 * gets stuck in a non-functional state, and even after link comes up 1004 * again, PIO requests won't work anymore, and a reset of the whole PCIe 1005 * controller is needed. Therefore we need to prevent sending PIO 1006 * requests while the link is down. 1007 */ 1008 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) 1009 return false; 1010 1011 return true; 1012 } 1013 1014 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) 1015 { 1016 struct device *dev = &pcie->pdev->dev; 1017 1018 /* 1019 * Trying to start a new PIO transfer when previous has not completed 1020 * cause External Abort on CPU which results in kernel panic: 1021 * 1022 * SError Interrupt on CPU0, code 0xbf000002 -- SError 1023 * Kernel panic - not syncing: Asynchronous SError Interrupt 1024 * 1025 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected 1026 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent 1027 * concurrent calls at the same time. But because PIO transfer may take 1028 * about 1.5s when link is down or card is disconnected, it means that 1029 * advk_pcie_wait_pio() does not always have to wait for completion. 1030 * 1031 * Some versions of ARM Trusted Firmware handles this External Abort at 1032 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: 1033 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 1034 */ 1035 if (advk_readl(pcie, PIO_START)) { 1036 dev_err(dev, "Previous PIO read/write transfer is still running\n"); 1037 return true; 1038 } 1039 1040 return false; 1041 } 1042 1043 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 1044 int where, int size, u32 *val) 1045 { 1046 struct advk_pcie *pcie = bus->sysdata; 1047 int retry_count; 1048 bool allow_crs; 1049 u32 reg; 1050 int ret; 1051 1052 if (!advk_pcie_valid_device(pcie, bus, devfn)) 1053 return PCIBIOS_DEVICE_NOT_FOUND; 1054 1055 if (pci_is_root_bus(bus)) 1056 return pci_bridge_emul_conf_read(&pcie->bridge, where, 1057 size, val); 1058 1059 /* 1060 * Completion Retry Status is possible to return only when reading all 1061 * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and 1062 * CRSSVE flag on Root Bridge is enabled. 1063 */ 1064 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && 1065 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & 1066 PCI_EXP_RTCTL_CRSSVE); 1067 1068 if (advk_pcie_pio_is_running(pcie)) 1069 goto try_crs; 1070 1071 /* Program the control register */ 1072 reg = advk_readl(pcie, PIO_CTRL); 1073 reg &= ~PIO_CTRL_TYPE_MASK; 1074 if (pci_is_root_bus(bus->parent)) 1075 reg |= PCIE_CONFIG_RD_TYPE0; 1076 else 1077 reg |= PCIE_CONFIG_RD_TYPE1; 1078 advk_writel(pcie, reg, PIO_CTRL); 1079 1080 /* Program the address registers */ 1081 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1082 advk_writel(pcie, reg, PIO_ADDR_LS); 1083 advk_writel(pcie, 0, PIO_ADDR_MS); 1084 1085 /* Program the data strobe */ 1086 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 1087 1088 retry_count = 0; 1089 do { 1090 /* Clear PIO DONE ISR and start the transfer */ 1091 advk_writel(pcie, 1, PIO_ISR); 1092 advk_writel(pcie, 1, PIO_START); 1093 1094 ret = advk_pcie_wait_pio(pcie); 1095 if (ret < 0) 1096 goto try_crs; 1097 1098 retry_count += ret; 1099 1100 /* Check PIO status and get the read result */ 1101 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); 1102 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1103 1104 if (ret < 0) 1105 goto fail; 1106 1107 if (size == 1) 1108 *val = (*val >> (8 * (where & 3))) & 0xff; 1109 else if (size == 2) 1110 *val = (*val >> (8 * (where & 3))) & 0xffff; 1111 1112 return PCIBIOS_SUCCESSFUL; 1113 1114 try_crs: 1115 /* 1116 * If it is possible, return Completion Retry Status so that caller 1117 * tries to issue the request again instead of failing. 1118 */ 1119 if (allow_crs) { 1120 *val = CFG_RD_CRS_VAL; 1121 return PCIBIOS_SUCCESSFUL; 1122 } 1123 1124 fail: 1125 *val = 0xffffffff; 1126 return PCIBIOS_SET_FAILED; 1127 } 1128 1129 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 1130 int where, int size, u32 val) 1131 { 1132 struct advk_pcie *pcie = bus->sysdata; 1133 u32 reg; 1134 u32 data_strobe = 0x0; 1135 int retry_count; 1136 int offset; 1137 int ret; 1138 1139 if (!advk_pcie_valid_device(pcie, bus, devfn)) 1140 return PCIBIOS_DEVICE_NOT_FOUND; 1141 1142 if (pci_is_root_bus(bus)) 1143 return pci_bridge_emul_conf_write(&pcie->bridge, where, 1144 size, val); 1145 1146 if (where % size) 1147 return PCIBIOS_SET_FAILED; 1148 1149 if (advk_pcie_pio_is_running(pcie)) 1150 return PCIBIOS_SET_FAILED; 1151 1152 /* Program the control register */ 1153 reg = advk_readl(pcie, PIO_CTRL); 1154 reg &= ~PIO_CTRL_TYPE_MASK; 1155 if (pci_is_root_bus(bus->parent)) 1156 reg |= PCIE_CONFIG_WR_TYPE0; 1157 else 1158 reg |= PCIE_CONFIG_WR_TYPE1; 1159 advk_writel(pcie, reg, PIO_CTRL); 1160 1161 /* Program the address registers */ 1162 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1163 advk_writel(pcie, reg, PIO_ADDR_LS); 1164 advk_writel(pcie, 0, PIO_ADDR_MS); 1165 1166 /* Calculate the write strobe */ 1167 offset = where & 0x3; 1168 reg = val << (8 * offset); 1169 data_strobe = GENMASK(size - 1, 0) << offset; 1170 1171 /* Program the data register */ 1172 advk_writel(pcie, reg, PIO_WR_DATA); 1173 1174 /* Program the data strobe */ 1175 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 1176 1177 retry_count = 0; 1178 do { 1179 /* Clear PIO DONE ISR and start the transfer */ 1180 advk_writel(pcie, 1, PIO_ISR); 1181 advk_writel(pcie, 1, PIO_START); 1182 1183 ret = advk_pcie_wait_pio(pcie); 1184 if (ret < 0) 1185 return PCIBIOS_SET_FAILED; 1186 1187 retry_count += ret; 1188 1189 ret = advk_pcie_check_pio_status(pcie, false, NULL); 1190 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1191 1192 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; 1193 } 1194 1195 static struct pci_ops advk_pcie_ops = { 1196 .read = advk_pcie_rd_conf, 1197 .write = advk_pcie_wr_conf, 1198 }; 1199 1200 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 1201 struct msi_msg *msg) 1202 { 1203 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 1204 phys_addr_t msi_addr = virt_to_phys(pcie); 1205 1206 msg->address_lo = lower_32_bits(msi_addr); 1207 msg->address_hi = upper_32_bits(msi_addr); 1208 msg->data = data->hwirq; 1209 } 1210 1211 static int advk_msi_set_affinity(struct irq_data *irq_data, 1212 const struct cpumask *mask, bool force) 1213 { 1214 return -EINVAL; 1215 } 1216 1217 static void advk_msi_irq_mask(struct irq_data *d) 1218 { 1219 struct advk_pcie *pcie = d->domain->host_data; 1220 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1221 unsigned long flags; 1222 u32 mask; 1223 1224 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); 1225 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1226 mask |= BIT(hwirq); 1227 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); 1228 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); 1229 } 1230 1231 static void advk_msi_irq_unmask(struct irq_data *d) 1232 { 1233 struct advk_pcie *pcie = d->domain->host_data; 1234 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1235 unsigned long flags; 1236 u32 mask; 1237 1238 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); 1239 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1240 mask &= ~BIT(hwirq); 1241 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); 1242 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); 1243 } 1244 1245 static void advk_msi_top_irq_mask(struct irq_data *d) 1246 { 1247 pci_msi_mask_irq(d); 1248 irq_chip_mask_parent(d); 1249 } 1250 1251 static void advk_msi_top_irq_unmask(struct irq_data *d) 1252 { 1253 pci_msi_unmask_irq(d); 1254 irq_chip_unmask_parent(d); 1255 } 1256 1257 static struct irq_chip advk_msi_bottom_irq_chip = { 1258 .name = "MSI", 1259 .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, 1260 .irq_set_affinity = advk_msi_set_affinity, 1261 .irq_mask = advk_msi_irq_mask, 1262 .irq_unmask = advk_msi_irq_unmask, 1263 }; 1264 1265 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 1266 unsigned int virq, 1267 unsigned int nr_irqs, void *args) 1268 { 1269 struct advk_pcie *pcie = domain->host_data; 1270 int hwirq, i; 1271 1272 mutex_lock(&pcie->msi_used_lock); 1273 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, 1274 order_base_2(nr_irqs)); 1275 mutex_unlock(&pcie->msi_used_lock); 1276 if (hwirq < 0) 1277 return -ENOSPC; 1278 1279 for (i = 0; i < nr_irqs; i++) 1280 irq_domain_set_info(domain, virq + i, hwirq + i, 1281 &advk_msi_bottom_irq_chip, 1282 domain->host_data, handle_simple_irq, 1283 NULL, NULL); 1284 1285 return 0; 1286 } 1287 1288 static void advk_msi_irq_domain_free(struct irq_domain *domain, 1289 unsigned int virq, unsigned int nr_irqs) 1290 { 1291 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1292 struct advk_pcie *pcie = domain->host_data; 1293 1294 mutex_lock(&pcie->msi_used_lock); 1295 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); 1296 mutex_unlock(&pcie->msi_used_lock); 1297 } 1298 1299 static const struct irq_domain_ops advk_msi_domain_ops = { 1300 .alloc = advk_msi_irq_domain_alloc, 1301 .free = advk_msi_irq_domain_free, 1302 }; 1303 1304 static void advk_pcie_irq_mask(struct irq_data *d) 1305 { 1306 struct advk_pcie *pcie = d->domain->host_data; 1307 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1308 unsigned long flags; 1309 u32 mask; 1310 1311 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1312 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1313 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 1314 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1315 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1316 } 1317 1318 static void advk_pcie_irq_unmask(struct irq_data *d) 1319 { 1320 struct advk_pcie *pcie = d->domain->host_data; 1321 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1322 unsigned long flags; 1323 u32 mask; 1324 1325 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1326 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1327 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 1328 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1329 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1330 } 1331 1332 static int advk_pcie_irq_map(struct irq_domain *h, 1333 unsigned int virq, irq_hw_number_t hwirq) 1334 { 1335 struct advk_pcie *pcie = h->host_data; 1336 1337 irq_set_status_flags(virq, IRQ_LEVEL); 1338 irq_set_chip_and_handler(virq, &pcie->irq_chip, 1339 handle_level_irq); 1340 irq_set_chip_data(virq, pcie); 1341 1342 return 0; 1343 } 1344 1345 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 1346 .map = advk_pcie_irq_map, 1347 .xlate = irq_domain_xlate_onecell, 1348 }; 1349 1350 static struct irq_chip advk_msi_irq_chip = { 1351 .name = "advk-MSI", 1352 .irq_mask = advk_msi_top_irq_mask, 1353 .irq_unmask = advk_msi_top_irq_unmask, 1354 }; 1355 1356 static struct msi_domain_info advk_msi_domain_info = { 1357 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1358 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 1359 .chip = &advk_msi_irq_chip, 1360 }; 1361 1362 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 1363 { 1364 struct device *dev = &pcie->pdev->dev; 1365 1366 raw_spin_lock_init(&pcie->msi_irq_lock); 1367 mutex_init(&pcie->msi_used_lock); 1368 1369 pcie->msi_inner_domain = 1370 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 1371 &advk_msi_domain_ops, pcie); 1372 if (!pcie->msi_inner_domain) 1373 return -ENOMEM; 1374 1375 pcie->msi_domain = 1376 pci_msi_create_irq_domain(dev_fwnode(dev), 1377 &advk_msi_domain_info, 1378 pcie->msi_inner_domain); 1379 if (!pcie->msi_domain) { 1380 irq_domain_remove(pcie->msi_inner_domain); 1381 return -ENOMEM; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 1388 { 1389 irq_domain_remove(pcie->msi_domain); 1390 irq_domain_remove(pcie->msi_inner_domain); 1391 } 1392 1393 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 1394 { 1395 struct device *dev = &pcie->pdev->dev; 1396 struct device_node *node = dev->of_node; 1397 struct device_node *pcie_intc_node; 1398 struct irq_chip *irq_chip; 1399 int ret = 0; 1400 1401 raw_spin_lock_init(&pcie->irq_lock); 1402 1403 pcie_intc_node = of_get_next_child(node, NULL); 1404 if (!pcie_intc_node) { 1405 dev_err(dev, "No PCIe Intc node found\n"); 1406 return -ENODEV; 1407 } 1408 1409 irq_chip = &pcie->irq_chip; 1410 1411 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 1412 dev_name(dev)); 1413 if (!irq_chip->name) { 1414 ret = -ENOMEM; 1415 goto out_put_node; 1416 } 1417 1418 irq_chip->irq_mask = advk_pcie_irq_mask; 1419 irq_chip->irq_unmask = advk_pcie_irq_unmask; 1420 1421 pcie->irq_domain = 1422 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 1423 &advk_pcie_irq_domain_ops, pcie); 1424 if (!pcie->irq_domain) { 1425 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 1426 ret = -ENOMEM; 1427 goto out_put_node; 1428 } 1429 1430 out_put_node: 1431 of_node_put(pcie_intc_node); 1432 return ret; 1433 } 1434 1435 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 1436 { 1437 irq_domain_remove(pcie->irq_domain); 1438 } 1439 1440 static struct irq_chip advk_rp_irq_chip = { 1441 .name = "advk-RP", 1442 }; 1443 1444 static int advk_pcie_rp_irq_map(struct irq_domain *h, 1445 unsigned int virq, irq_hw_number_t hwirq) 1446 { 1447 struct advk_pcie *pcie = h->host_data; 1448 1449 irq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq); 1450 irq_set_chip_data(virq, pcie); 1451 1452 return 0; 1453 } 1454 1455 static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = { 1456 .map = advk_pcie_rp_irq_map, 1457 .xlate = irq_domain_xlate_onecell, 1458 }; 1459 1460 static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) 1461 { 1462 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, 1463 &advk_pcie_rp_irq_domain_ops, 1464 pcie); 1465 if (!pcie->rp_irq_domain) { 1466 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); 1467 return -ENOMEM; 1468 } 1469 1470 return 0; 1471 } 1472 1473 static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) 1474 { 1475 irq_domain_remove(pcie->rp_irq_domain); 1476 } 1477 1478 static void advk_pcie_handle_pme(struct advk_pcie *pcie) 1479 { 1480 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; 1481 1482 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); 1483 1484 /* 1485 * PCIE_MSG_LOG_REG contains the last inbound message, so store 1486 * the requester ID only when PME was not asserted yet. 1487 * Also do not trigger PME interrupt when PME is still asserted. 1488 */ 1489 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { 1490 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); 1491 1492 /* 1493 * Trigger PME interrupt only if PMEIE bit in Root Control is set. 1494 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. 1495 */ 1496 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) 1497 return; 1498 1499 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) 1500 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); 1501 } 1502 } 1503 1504 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 1505 { 1506 u32 msi_val, msi_mask, msi_status, msi_idx; 1507 1508 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1509 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 1510 msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK); 1511 1512 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 1513 if (!(BIT(msi_idx) & msi_status)) 1514 continue; 1515 1516 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 1517 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) 1518 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); 1519 } 1520 1521 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 1522 PCIE_ISR0_REG); 1523 } 1524 1525 static void advk_pcie_handle_int(struct advk_pcie *pcie) 1526 { 1527 u32 isr0_val, isr0_mask, isr0_status; 1528 u32 isr1_val, isr1_mask, isr1_status; 1529 int i; 1530 1531 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 1532 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 1533 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 1534 1535 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 1536 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1537 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 1538 1539 /* Process PME interrupt as the first one to do not miss PME requester id */ 1540 if (isr0_status & PCIE_MSG_PM_PME_MASK) 1541 advk_pcie_handle_pme(pcie); 1542 1543 /* Process ERR interrupt */ 1544 if (isr0_status & PCIE_ISR0_ERR_MASK) { 1545 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); 1546 1547 /* 1548 * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use 1549 * PCIe interrupt 0 1550 */ 1551 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) 1552 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); 1553 } 1554 1555 /* Process MSI interrupts */ 1556 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 1557 advk_pcie_handle_msi(pcie); 1558 1559 /* Process legacy interrupts */ 1560 for (i = 0; i < PCI_NUM_INTX; i++) { 1561 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 1562 continue; 1563 1564 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 1565 PCIE_ISR1_REG); 1566 1567 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) 1568 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", 1569 (char)i + 'A'); 1570 } 1571 } 1572 1573 static void advk_pcie_irq_handler(struct irq_desc *desc) 1574 { 1575 struct advk_pcie *pcie = irq_desc_get_handler_data(desc); 1576 struct irq_chip *chip = irq_desc_get_chip(desc); 1577 u32 val, mask, status; 1578 1579 chained_irq_enter(chip, desc); 1580 1581 val = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 1582 mask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG); 1583 status = val & ((~mask) & PCIE_IRQ_ALL_MASK); 1584 1585 if (status & PCIE_IRQ_CORE_INT) { 1586 advk_pcie_handle_int(pcie); 1587 1588 /* Clear interrupt */ 1589 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 1590 } 1591 1592 chained_irq_exit(chip, desc); 1593 } 1594 1595 static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1596 { 1597 struct advk_pcie *pcie = dev->bus->sysdata; 1598 1599 /* 1600 * Emulated root bridge has its own emulated irq chip and irq domain. 1601 * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and 1602 * hwirq for irq_create_mapping() is indexed from zero. 1603 */ 1604 if (pci_is_root_bus(dev->bus)) 1605 return irq_create_mapping(pcie->rp_irq_domain, pin - 1); 1606 else 1607 return of_irq_parse_and_map_pci(dev, slot, pin); 1608 } 1609 1610 static void advk_pcie_disable_phy(struct advk_pcie *pcie) 1611 { 1612 phy_power_off(pcie->phy); 1613 phy_exit(pcie->phy); 1614 } 1615 1616 static int advk_pcie_enable_phy(struct advk_pcie *pcie) 1617 { 1618 int ret; 1619 1620 if (!pcie->phy) 1621 return 0; 1622 1623 ret = phy_init(pcie->phy); 1624 if (ret) 1625 return ret; 1626 1627 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); 1628 if (ret) { 1629 phy_exit(pcie->phy); 1630 return ret; 1631 } 1632 1633 ret = phy_power_on(pcie->phy); 1634 if (ret) { 1635 phy_exit(pcie->phy); 1636 return ret; 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int advk_pcie_setup_phy(struct advk_pcie *pcie) 1643 { 1644 struct device *dev = &pcie->pdev->dev; 1645 struct device_node *node = dev->of_node; 1646 int ret = 0; 1647 1648 pcie->phy = devm_of_phy_get(dev, node, NULL); 1649 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) 1650 return PTR_ERR(pcie->phy); 1651 1652 /* Old bindings miss the PHY handle */ 1653 if (IS_ERR(pcie->phy)) { 1654 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); 1655 pcie->phy = NULL; 1656 return 0; 1657 } 1658 1659 ret = advk_pcie_enable_phy(pcie); 1660 if (ret) 1661 dev_err(dev, "Failed to initialize PHY (%d)\n", ret); 1662 1663 return ret; 1664 } 1665 1666 static int advk_pcie_probe(struct platform_device *pdev) 1667 { 1668 struct device *dev = &pdev->dev; 1669 struct advk_pcie *pcie; 1670 struct pci_host_bridge *bridge; 1671 struct resource_entry *entry; 1672 int ret; 1673 1674 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 1675 if (!bridge) 1676 return -ENOMEM; 1677 1678 pcie = pci_host_bridge_priv(bridge); 1679 pcie->pdev = pdev; 1680 platform_set_drvdata(pdev, pcie); 1681 1682 resource_list_for_each_entry(entry, &bridge->windows) { 1683 resource_size_t start = entry->res->start; 1684 resource_size_t size = resource_size(entry->res); 1685 unsigned long type = resource_type(entry->res); 1686 u64 win_size; 1687 1688 /* 1689 * Aardvark hardware allows to configure also PCIe window 1690 * for config type 0 and type 1 mapping, but driver uses 1691 * only PIO for issuing configuration transfers which does 1692 * not use PCIe window configuration. 1693 */ 1694 if (type != IORESOURCE_MEM && type != IORESOURCE_IO) 1695 continue; 1696 1697 /* 1698 * Skip transparent memory resources. Default outbound access 1699 * configuration is set to transparent memory access so it 1700 * does not need window configuration. 1701 */ 1702 if (type == IORESOURCE_MEM && entry->offset == 0) 1703 continue; 1704 1705 /* 1706 * The n-th PCIe window is configured by tuple (match, remap, mask) 1707 * and an access to address A uses this window if A matches the 1708 * match with given mask. 1709 * So every PCIe window size must be a power of two and every start 1710 * address must be aligned to window size. Minimal size is 64 KiB 1711 * because lower 16 bits of mask must be zero. Remapped address 1712 * may have set only bits from the mask. 1713 */ 1714 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { 1715 /* Calculate the largest aligned window size */ 1716 win_size = (1ULL << (fls64(size)-1)) | 1717 (start ? (1ULL << __ffs64(start)) : 0); 1718 win_size = 1ULL << __ffs64(win_size); 1719 if (win_size < 0x10000) 1720 break; 1721 1722 dev_dbg(dev, 1723 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", 1724 pcie->wins_count, (unsigned long long)start, 1725 (unsigned long long)start + win_size, type); 1726 1727 if (type == IORESOURCE_IO) { 1728 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; 1729 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); 1730 } else { 1731 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; 1732 pcie->wins[pcie->wins_count].match = start; 1733 } 1734 pcie->wins[pcie->wins_count].remap = start - entry->offset; 1735 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); 1736 1737 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) 1738 break; 1739 1740 start += win_size; 1741 size -= win_size; 1742 pcie->wins_count++; 1743 } 1744 1745 if (size > 0) { 1746 dev_err(&pcie->pdev->dev, 1747 "Invalid PCIe region [0x%llx-0x%llx]\n", 1748 (unsigned long long)entry->res->start, 1749 (unsigned long long)entry->res->end + 1); 1750 return -EINVAL; 1751 } 1752 } 1753 1754 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1755 if (IS_ERR(pcie->base)) 1756 return PTR_ERR(pcie->base); 1757 1758 pcie->irq = platform_get_irq(pdev, 0); 1759 if (pcie->irq < 0) 1760 return pcie->irq; 1761 1762 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, 1763 "reset-gpios", 0, 1764 GPIOD_OUT_LOW, 1765 "pcie1-reset"); 1766 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); 1767 if (ret) { 1768 if (ret == -ENOENT) { 1769 pcie->reset_gpio = NULL; 1770 } else { 1771 if (ret != -EPROBE_DEFER) 1772 dev_err(dev, "Failed to get reset-gpio: %i\n", 1773 ret); 1774 return ret; 1775 } 1776 } 1777 1778 ret = of_pci_get_max_link_speed(dev->of_node); 1779 if (ret <= 0 || ret > 3) 1780 pcie->link_gen = 3; 1781 else 1782 pcie->link_gen = ret; 1783 1784 ret = advk_pcie_setup_phy(pcie); 1785 if (ret) 1786 return ret; 1787 1788 advk_pcie_setup_hw(pcie); 1789 1790 ret = advk_sw_pci_bridge_init(pcie); 1791 if (ret) { 1792 dev_err(dev, "Failed to register emulated root PCI bridge\n"); 1793 return ret; 1794 } 1795 1796 ret = advk_pcie_init_irq_domain(pcie); 1797 if (ret) { 1798 dev_err(dev, "Failed to initialize irq\n"); 1799 return ret; 1800 } 1801 1802 ret = advk_pcie_init_msi_irq_domain(pcie); 1803 if (ret) { 1804 dev_err(dev, "Failed to initialize irq\n"); 1805 advk_pcie_remove_irq_domain(pcie); 1806 return ret; 1807 } 1808 1809 ret = advk_pcie_init_rp_irq_domain(pcie); 1810 if (ret) { 1811 dev_err(dev, "Failed to initialize irq\n"); 1812 advk_pcie_remove_msi_irq_domain(pcie); 1813 advk_pcie_remove_irq_domain(pcie); 1814 return ret; 1815 } 1816 1817 irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie); 1818 1819 bridge->sysdata = pcie; 1820 bridge->ops = &advk_pcie_ops; 1821 bridge->map_irq = advk_pcie_map_irq; 1822 1823 ret = pci_host_probe(bridge); 1824 if (ret < 0) { 1825 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); 1826 advk_pcie_remove_rp_irq_domain(pcie); 1827 advk_pcie_remove_msi_irq_domain(pcie); 1828 advk_pcie_remove_irq_domain(pcie); 1829 return ret; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int advk_pcie_remove(struct platform_device *pdev) 1836 { 1837 struct advk_pcie *pcie = platform_get_drvdata(pdev); 1838 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1839 u32 val; 1840 int i; 1841 1842 /* Remove PCI bus with all devices */ 1843 pci_lock_rescan_remove(); 1844 pci_stop_root_bus(bridge->bus); 1845 pci_remove_root_bus(bridge->bus); 1846 pci_unlock_rescan_remove(); 1847 1848 /* Disable Root Bridge I/O space, memory space and bus mastering */ 1849 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 1850 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 1851 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); 1852 1853 /* Disable MSI */ 1854 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 1855 val &= ~PCIE_CORE_CTRL2_MSI_ENABLE; 1856 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); 1857 1858 /* Clear MSI address */ 1859 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); 1860 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); 1861 1862 /* Mask all interrupts */ 1863 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); 1864 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); 1865 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 1866 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); 1867 1868 /* Clear all interrupts */ 1869 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); 1870 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 1871 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 1872 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 1873 1874 /* Remove IRQ handler */ 1875 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); 1876 1877 /* Remove IRQ domains */ 1878 advk_pcie_remove_rp_irq_domain(pcie); 1879 advk_pcie_remove_msi_irq_domain(pcie); 1880 advk_pcie_remove_irq_domain(pcie); 1881 1882 /* Free config space for emulated root bridge */ 1883 pci_bridge_emul_cleanup(&pcie->bridge); 1884 1885 /* Assert PERST# signal which prepares PCIe card for power down */ 1886 if (pcie->reset_gpio) 1887 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 1888 1889 /* Disable link training */ 1890 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 1891 val &= ~LINK_TRAINING_EN; 1892 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); 1893 1894 /* Disable outbound address windows mapping */ 1895 for (i = 0; i < OB_WIN_COUNT; i++) 1896 advk_pcie_disable_ob_win(pcie, i); 1897 1898 /* Disable phy */ 1899 advk_pcie_disable_phy(pcie); 1900 1901 return 0; 1902 } 1903 1904 static const struct of_device_id advk_pcie_of_match_table[] = { 1905 { .compatible = "marvell,armada-3700-pcie", }, 1906 {}, 1907 }; 1908 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table); 1909 1910 static struct platform_driver advk_pcie_driver = { 1911 .driver = { 1912 .name = "advk-pcie", 1913 .of_match_table = advk_pcie_of_match_table, 1914 }, 1915 .probe = advk_pcie_probe, 1916 .remove = advk_pcie_remove, 1917 }; 1918 module_platform_driver(advk_pcie_driver); 1919 1920 MODULE_DESCRIPTION("Aardvark PCIe controller"); 1921 MODULE_LICENSE("GPL v2"); 1922