1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 22 #include "../pci.h" 23 24 /* PCIe core registers */ 25 #define PCIE_CORE_CMD_STATUS_REG 0x4 26 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 27 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 28 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 29 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 30 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) 31 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 32 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) 33 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 35 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 36 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) 37 #define PCIE_CORE_LINK_TRAINING BIT(5) 38 #define PCIE_CORE_LINK_WIDTH_SHIFT 20 39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 44 45 /* PIO registers base address and register offsets */ 46 #define PIO_BASE_ADDR 0x4000 47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 50 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 51 #define PIO_COMPLETION_STATUS_SHIFT 7 52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 53 #define PIO_COMPLETION_STATUS_OK 0 54 #define PIO_COMPLETION_STATUS_UR 1 55 #define PIO_COMPLETION_STATUS_CRS 2 56 #define PIO_COMPLETION_STATUS_CA 4 57 #define PIO_NON_POSTED_REQ BIT(0) 58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 63 #define PIO_START (PIO_BASE_ADDR + 0x1c) 64 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 66 67 /* Aardvark Control registers */ 68 #define CONTROL_BASE_ADDR 0x4800 69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 70 #define PCIE_GEN_SEL_MSK 0x3 71 #define PCIE_GEN_SEL_SHIFT 0x0 72 #define SPEED_GEN_1 0 73 #define SPEED_GEN_2 1 74 #define SPEED_GEN_3 2 75 #define IS_RC_MSK 1 76 #define IS_RC_SHIFT 2 77 #define LANE_CNT_MSK 0x18 78 #define LANE_CNT_SHIFT 0x3 79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 83 #define LINK_TRAINING_EN BIT(6) 84 #define LEGACY_INTA BIT(28) 85 #define LEGACY_INTB BIT(29) 86 #define LEGACY_INTC BIT(30) 87 #define LEGACY_INTD BIT(31) 88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 89 #define HOT_RESET_GEN BIT(0) 90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 91 #define PCIE_CORE_CTRL2_RESERVED 0x7 92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 96 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 97 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 98 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 99 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 100 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 101 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 102 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 103 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 104 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 105 #define PCIE_ISR1_FLUSH BIT(5) 106 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 107 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 108 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 109 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 110 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 111 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 112 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 113 114 /* LMI registers base address and register offsets */ 115 #define LMI_BASE_ADDR 0x6000 116 #define CFG_REG (LMI_BASE_ADDR + 0x0) 117 #define LTSSM_SHIFT 24 118 #define LTSSM_MASK 0x3f 119 #define LTSSM_L0 0x10 120 #define RC_BAR_CONFIG 0x300 121 122 /* PCIe core controller registers */ 123 #define CTRL_CORE_BASE_ADDR 0x18000 124 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 125 #define CTRL_MODE_SHIFT 0x0 126 #define CTRL_MODE_MASK 0x1 127 #define PCIE_CORE_MODE_DIRECT 0x0 128 #define PCIE_CORE_MODE_COMMAND 0x1 129 130 /* PCIe Central Interrupts Registers */ 131 #define CENTRAL_INT_BASE_ADDR 0x1b000 132 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 133 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 134 #define PCIE_IRQ_CMDQ_INT BIT(0) 135 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 136 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 137 #define PCIE_IRQ_DMA_INT BIT(4) 138 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 139 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 140 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 141 #define PCIE_IRQ_COMPQ_INT BIT(12) 142 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 143 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 144 #define PCIE_IRQ_CORE_INT BIT(16) 145 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 146 #define PCIE_IRQ_DPMU_INT BIT(18) 147 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 148 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 149 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 150 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 151 #define PCIE_IRQ_EP_STATUS BIT(23) 152 #define PCIE_IRQ_ALL_MASK 0xfff0fb 153 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 154 155 /* Transaction types */ 156 #define PCIE_CONFIG_RD_TYPE0 0x8 157 #define PCIE_CONFIG_RD_TYPE1 0x9 158 #define PCIE_CONFIG_WR_TYPE0 0xa 159 #define PCIE_CONFIG_WR_TYPE1 0xb 160 161 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 162 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 163 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 164 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 165 #define PCIE_CONF_ADDR(bus, devfn, where) \ 166 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 167 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 168 169 #define PIO_TIMEOUT_MS 1 170 171 #define LINK_WAIT_MAX_RETRIES 10 172 #define LINK_WAIT_USLEEP_MIN 90000 173 #define LINK_WAIT_USLEEP_MAX 100000 174 175 #define MSI_IRQ_NUM 32 176 177 struct advk_pcie { 178 struct platform_device *pdev; 179 void __iomem *base; 180 struct list_head resources; 181 struct irq_domain *irq_domain; 182 struct irq_chip irq_chip; 183 struct irq_domain *msi_domain; 184 struct irq_domain *msi_inner_domain; 185 struct irq_chip msi_bottom_irq_chip; 186 struct irq_chip msi_irq_chip; 187 struct msi_domain_info msi_domain_info; 188 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 189 struct mutex msi_used_lock; 190 u16 msi_msg; 191 int root_bus_nr; 192 }; 193 194 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 195 { 196 writel(val, pcie->base + reg); 197 } 198 199 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 200 { 201 return readl(pcie->base + reg); 202 } 203 204 static int advk_pcie_link_up(struct advk_pcie *pcie) 205 { 206 u32 val, ltssm_state; 207 208 val = advk_readl(pcie, CFG_REG); 209 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 210 return ltssm_state >= LTSSM_L0; 211 } 212 213 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 214 { 215 struct device *dev = &pcie->pdev->dev; 216 int retries; 217 218 /* check if the link is up or not */ 219 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 220 if (advk_pcie_link_up(pcie)) { 221 dev_info(dev, "link up\n"); 222 return 0; 223 } 224 225 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 226 } 227 228 dev_err(dev, "link never came up\n"); 229 return -ETIMEDOUT; 230 } 231 232 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 233 { 234 u32 reg; 235 236 /* Set to Direct mode */ 237 reg = advk_readl(pcie, CTRL_CONFIG_REG); 238 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 239 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 240 advk_writel(pcie, reg, CTRL_CONFIG_REG); 241 242 /* Set PCI global control register to RC mode */ 243 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 244 reg |= (IS_RC_MSK << IS_RC_SHIFT); 245 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 246 247 /* Set Advanced Error Capabilities and Control PF0 register */ 248 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 249 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 250 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 251 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 252 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 253 254 /* Set PCIe Device Control and Status 1 PF0 register */ 255 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | 256 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | 257 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | 258 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << 259 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); 260 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); 261 262 /* Program PCIe Control 2 to disable strict ordering */ 263 reg = PCIE_CORE_CTRL2_RESERVED | 264 PCIE_CORE_CTRL2_TD_ENABLE; 265 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 266 267 /* Set GEN2 */ 268 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 269 reg &= ~PCIE_GEN_SEL_MSK; 270 reg |= SPEED_GEN_2; 271 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 272 273 /* Set lane X1 */ 274 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 275 reg &= ~LANE_CNT_MSK; 276 reg |= LANE_COUNT_1; 277 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 278 279 /* Enable link training */ 280 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 281 reg |= LINK_TRAINING_EN; 282 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 283 284 /* Enable MSI */ 285 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 286 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 287 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 288 289 /* Clear all interrupts */ 290 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 291 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 292 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 293 294 /* Disable All ISR0/1 Sources */ 295 reg = PCIE_ISR0_ALL_MASK; 296 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 297 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 298 299 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 300 301 /* Unmask all MSI's */ 302 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 303 304 /* Enable summary interrupt for GIC SPI source */ 305 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 306 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 307 308 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 309 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 310 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 311 312 /* Bypass the address window mapping for PIO */ 313 reg = advk_readl(pcie, PIO_CTRL); 314 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 315 advk_writel(pcie, reg, PIO_CTRL); 316 317 /* Start link training */ 318 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); 319 reg |= PCIE_CORE_LINK_TRAINING; 320 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 321 322 advk_pcie_wait_for_link(pcie); 323 324 reg = PCIE_CORE_LINK_L0S_ENTRY | 325 (1 << PCIE_CORE_LINK_WIDTH_SHIFT); 326 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 327 328 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 329 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 330 PCIE_CORE_CMD_IO_ACCESS_EN | 331 PCIE_CORE_CMD_MEM_IO_REQ_EN; 332 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 333 } 334 335 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 336 { 337 struct device *dev = &pcie->pdev->dev; 338 u32 reg; 339 unsigned int status; 340 char *strcomp_status, *str_posted; 341 342 reg = advk_readl(pcie, PIO_STAT); 343 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 344 PIO_COMPLETION_STATUS_SHIFT; 345 346 if (!status) 347 return; 348 349 switch (status) { 350 case PIO_COMPLETION_STATUS_UR: 351 strcomp_status = "UR"; 352 break; 353 case PIO_COMPLETION_STATUS_CRS: 354 strcomp_status = "CRS"; 355 break; 356 case PIO_COMPLETION_STATUS_CA: 357 strcomp_status = "CA"; 358 break; 359 default: 360 strcomp_status = "Unknown"; 361 break; 362 } 363 364 if (reg & PIO_NON_POSTED_REQ) 365 str_posted = "Non-posted"; 366 else 367 str_posted = "Posted"; 368 369 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 370 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 371 } 372 373 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 374 { 375 struct device *dev = &pcie->pdev->dev; 376 unsigned long timeout; 377 378 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS); 379 380 while (time_before(jiffies, timeout)) { 381 u32 start, isr; 382 383 start = advk_readl(pcie, PIO_START); 384 isr = advk_readl(pcie, PIO_ISR); 385 if (!start && isr) 386 return 0; 387 } 388 389 dev_err(dev, "config read/write timed out\n"); 390 return -ETIMEDOUT; 391 } 392 393 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 394 int devfn) 395 { 396 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 397 return false; 398 399 return true; 400 } 401 402 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 403 int where, int size, u32 *val) 404 { 405 struct advk_pcie *pcie = bus->sysdata; 406 u32 reg; 407 int ret; 408 409 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 410 *val = 0xffffffff; 411 return PCIBIOS_DEVICE_NOT_FOUND; 412 } 413 414 /* Start PIO */ 415 advk_writel(pcie, 0, PIO_START); 416 advk_writel(pcie, 1, PIO_ISR); 417 418 /* Program the control register */ 419 reg = advk_readl(pcie, PIO_CTRL); 420 reg &= ~PIO_CTRL_TYPE_MASK; 421 if (bus->number == pcie->root_bus_nr) 422 reg |= PCIE_CONFIG_RD_TYPE0; 423 else 424 reg |= PCIE_CONFIG_RD_TYPE1; 425 advk_writel(pcie, reg, PIO_CTRL); 426 427 /* Program the address registers */ 428 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 429 advk_writel(pcie, reg, PIO_ADDR_LS); 430 advk_writel(pcie, 0, PIO_ADDR_MS); 431 432 /* Program the data strobe */ 433 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 434 435 /* Start the transfer */ 436 advk_writel(pcie, 1, PIO_START); 437 438 ret = advk_pcie_wait_pio(pcie); 439 if (ret < 0) 440 return PCIBIOS_SET_FAILED; 441 442 advk_pcie_check_pio_status(pcie); 443 444 /* Get the read result */ 445 *val = advk_readl(pcie, PIO_RD_DATA); 446 if (size == 1) 447 *val = (*val >> (8 * (where & 3))) & 0xff; 448 else if (size == 2) 449 *val = (*val >> (8 * (where & 3))) & 0xffff; 450 451 return PCIBIOS_SUCCESSFUL; 452 } 453 454 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 455 int where, int size, u32 val) 456 { 457 struct advk_pcie *pcie = bus->sysdata; 458 u32 reg; 459 u32 data_strobe = 0x0; 460 int offset; 461 int ret; 462 463 if (!advk_pcie_valid_device(pcie, bus, devfn)) 464 return PCIBIOS_DEVICE_NOT_FOUND; 465 466 if (where % size) 467 return PCIBIOS_SET_FAILED; 468 469 /* Start PIO */ 470 advk_writel(pcie, 0, PIO_START); 471 advk_writel(pcie, 1, PIO_ISR); 472 473 /* Program the control register */ 474 reg = advk_readl(pcie, PIO_CTRL); 475 reg &= ~PIO_CTRL_TYPE_MASK; 476 if (bus->number == pcie->root_bus_nr) 477 reg |= PCIE_CONFIG_WR_TYPE0; 478 else 479 reg |= PCIE_CONFIG_WR_TYPE1; 480 advk_writel(pcie, reg, PIO_CTRL); 481 482 /* Program the address registers */ 483 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 484 advk_writel(pcie, reg, PIO_ADDR_LS); 485 advk_writel(pcie, 0, PIO_ADDR_MS); 486 487 /* Calculate the write strobe */ 488 offset = where & 0x3; 489 reg = val << (8 * offset); 490 data_strobe = GENMASK(size - 1, 0) << offset; 491 492 /* Program the data register */ 493 advk_writel(pcie, reg, PIO_WR_DATA); 494 495 /* Program the data strobe */ 496 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 497 498 /* Start the transfer */ 499 advk_writel(pcie, 1, PIO_START); 500 501 ret = advk_pcie_wait_pio(pcie); 502 if (ret < 0) 503 return PCIBIOS_SET_FAILED; 504 505 advk_pcie_check_pio_status(pcie); 506 507 return PCIBIOS_SUCCESSFUL; 508 } 509 510 static struct pci_ops advk_pcie_ops = { 511 .read = advk_pcie_rd_conf, 512 .write = advk_pcie_wr_conf, 513 }; 514 515 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 516 struct msi_msg *msg) 517 { 518 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 519 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 520 521 msg->address_lo = lower_32_bits(msi_msg); 522 msg->address_hi = upper_32_bits(msi_msg); 523 msg->data = data->irq; 524 } 525 526 static int advk_msi_set_affinity(struct irq_data *irq_data, 527 const struct cpumask *mask, bool force) 528 { 529 return -EINVAL; 530 } 531 532 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 533 unsigned int virq, 534 unsigned int nr_irqs, void *args) 535 { 536 struct advk_pcie *pcie = domain->host_data; 537 int hwirq, i; 538 539 mutex_lock(&pcie->msi_used_lock); 540 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 541 0, nr_irqs, 0); 542 if (hwirq >= MSI_IRQ_NUM) { 543 mutex_unlock(&pcie->msi_used_lock); 544 return -ENOSPC; 545 } 546 547 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 548 mutex_unlock(&pcie->msi_used_lock); 549 550 for (i = 0; i < nr_irqs; i++) 551 irq_domain_set_info(domain, virq + i, hwirq + i, 552 &pcie->msi_bottom_irq_chip, 553 domain->host_data, handle_simple_irq, 554 NULL, NULL); 555 556 return hwirq; 557 } 558 559 static void advk_msi_irq_domain_free(struct irq_domain *domain, 560 unsigned int virq, unsigned int nr_irqs) 561 { 562 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 563 struct advk_pcie *pcie = domain->host_data; 564 565 mutex_lock(&pcie->msi_used_lock); 566 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 567 mutex_unlock(&pcie->msi_used_lock); 568 } 569 570 static const struct irq_domain_ops advk_msi_domain_ops = { 571 .alloc = advk_msi_irq_domain_alloc, 572 .free = advk_msi_irq_domain_free, 573 }; 574 575 static void advk_pcie_irq_mask(struct irq_data *d) 576 { 577 struct advk_pcie *pcie = d->domain->host_data; 578 irq_hw_number_t hwirq = irqd_to_hwirq(d); 579 u32 mask; 580 581 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 582 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 583 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 584 } 585 586 static void advk_pcie_irq_unmask(struct irq_data *d) 587 { 588 struct advk_pcie *pcie = d->domain->host_data; 589 irq_hw_number_t hwirq = irqd_to_hwirq(d); 590 u32 mask; 591 592 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 593 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 594 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 595 } 596 597 static int advk_pcie_irq_map(struct irq_domain *h, 598 unsigned int virq, irq_hw_number_t hwirq) 599 { 600 struct advk_pcie *pcie = h->host_data; 601 602 advk_pcie_irq_mask(irq_get_irq_data(virq)); 603 irq_set_status_flags(virq, IRQ_LEVEL); 604 irq_set_chip_and_handler(virq, &pcie->irq_chip, 605 handle_level_irq); 606 irq_set_chip_data(virq, pcie); 607 608 return 0; 609 } 610 611 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 612 .map = advk_pcie_irq_map, 613 .xlate = irq_domain_xlate_onecell, 614 }; 615 616 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 617 { 618 struct device *dev = &pcie->pdev->dev; 619 struct device_node *node = dev->of_node; 620 struct irq_chip *bottom_ic, *msi_ic; 621 struct msi_domain_info *msi_di; 622 phys_addr_t msi_msg_phys; 623 624 mutex_init(&pcie->msi_used_lock); 625 626 bottom_ic = &pcie->msi_bottom_irq_chip; 627 628 bottom_ic->name = "MSI"; 629 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 630 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 631 632 msi_ic = &pcie->msi_irq_chip; 633 msi_ic->name = "advk-MSI"; 634 635 msi_di = &pcie->msi_domain_info; 636 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 637 MSI_FLAG_MULTI_PCI_MSI; 638 msi_di->chip = msi_ic; 639 640 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 641 642 advk_writel(pcie, lower_32_bits(msi_msg_phys), 643 PCIE_MSI_ADDR_LOW_REG); 644 advk_writel(pcie, upper_32_bits(msi_msg_phys), 645 PCIE_MSI_ADDR_HIGH_REG); 646 647 pcie->msi_inner_domain = 648 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 649 &advk_msi_domain_ops, pcie); 650 if (!pcie->msi_inner_domain) 651 return -ENOMEM; 652 653 pcie->msi_domain = 654 pci_msi_create_irq_domain(of_node_to_fwnode(node), 655 msi_di, pcie->msi_inner_domain); 656 if (!pcie->msi_domain) { 657 irq_domain_remove(pcie->msi_inner_domain); 658 return -ENOMEM; 659 } 660 661 return 0; 662 } 663 664 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 665 { 666 irq_domain_remove(pcie->msi_domain); 667 irq_domain_remove(pcie->msi_inner_domain); 668 } 669 670 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 671 { 672 struct device *dev = &pcie->pdev->dev; 673 struct device_node *node = dev->of_node; 674 struct device_node *pcie_intc_node; 675 struct irq_chip *irq_chip; 676 677 pcie_intc_node = of_get_next_child(node, NULL); 678 if (!pcie_intc_node) { 679 dev_err(dev, "No PCIe Intc node found\n"); 680 return -ENODEV; 681 } 682 683 irq_chip = &pcie->irq_chip; 684 685 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 686 dev_name(dev)); 687 if (!irq_chip->name) { 688 of_node_put(pcie_intc_node); 689 return -ENOMEM; 690 } 691 692 irq_chip->irq_mask = advk_pcie_irq_mask; 693 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 694 irq_chip->irq_unmask = advk_pcie_irq_unmask; 695 696 pcie->irq_domain = 697 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 698 &advk_pcie_irq_domain_ops, pcie); 699 if (!pcie->irq_domain) { 700 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 701 of_node_put(pcie_intc_node); 702 return -ENOMEM; 703 } 704 705 return 0; 706 } 707 708 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 709 { 710 irq_domain_remove(pcie->irq_domain); 711 } 712 713 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 714 { 715 u32 msi_val, msi_mask, msi_status, msi_idx; 716 u16 msi_data; 717 718 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 719 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 720 msi_status = msi_val & ~msi_mask; 721 722 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 723 if (!(BIT(msi_idx) & msi_status)) 724 continue; 725 726 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 727 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 728 generic_handle_irq(msi_data); 729 } 730 731 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 732 PCIE_ISR0_REG); 733 } 734 735 static void advk_pcie_handle_int(struct advk_pcie *pcie) 736 { 737 u32 isr0_val, isr0_mask, isr0_status; 738 u32 isr1_val, isr1_mask, isr1_status; 739 int i, virq; 740 741 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 742 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 743 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 744 745 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 746 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 747 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 748 749 if (!isr0_status && !isr1_status) { 750 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 751 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 752 return; 753 } 754 755 /* Process MSI interrupts */ 756 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 757 advk_pcie_handle_msi(pcie); 758 759 /* Process legacy interrupts */ 760 for (i = 0; i < PCI_NUM_INTX; i++) { 761 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 762 continue; 763 764 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 765 PCIE_ISR1_REG); 766 767 virq = irq_find_mapping(pcie->irq_domain, i); 768 generic_handle_irq(virq); 769 } 770 } 771 772 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 773 { 774 struct advk_pcie *pcie = arg; 775 u32 status; 776 777 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 778 if (!(status & PCIE_IRQ_CORE_INT)) 779 return IRQ_NONE; 780 781 advk_pcie_handle_int(pcie); 782 783 /* Clear interrupt */ 784 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 785 786 return IRQ_HANDLED; 787 } 788 789 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) 790 { 791 int err, res_valid = 0; 792 struct device *dev = &pcie->pdev->dev; 793 struct resource_entry *win, *tmp; 794 resource_size_t iobase; 795 796 INIT_LIST_HEAD(&pcie->resources); 797 798 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 799 &pcie->resources, &iobase); 800 if (err) 801 return err; 802 803 err = devm_request_pci_bus_resources(dev, &pcie->resources); 804 if (err) 805 goto out_release_res; 806 807 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { 808 struct resource *res = win->res; 809 810 switch (resource_type(res)) { 811 case IORESOURCE_IO: 812 err = devm_pci_remap_iospace(dev, res, iobase); 813 if (err) { 814 dev_warn(dev, "error %d: failed to map resource %pR\n", 815 err, res); 816 resource_list_destroy_entry(win); 817 } 818 break; 819 case IORESOURCE_MEM: 820 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 821 break; 822 case IORESOURCE_BUS: 823 pcie->root_bus_nr = res->start; 824 break; 825 } 826 } 827 828 if (!res_valid) { 829 dev_err(dev, "non-prefetchable memory resource required\n"); 830 err = -EINVAL; 831 goto out_release_res; 832 } 833 834 return 0; 835 836 out_release_res: 837 pci_free_resource_list(&pcie->resources); 838 return err; 839 } 840 841 static int advk_pcie_probe(struct platform_device *pdev) 842 { 843 struct device *dev = &pdev->dev; 844 struct advk_pcie *pcie; 845 struct resource *res; 846 struct pci_host_bridge *bridge; 847 int ret, irq; 848 849 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 850 if (!bridge) 851 return -ENOMEM; 852 853 pcie = pci_host_bridge_priv(bridge); 854 pcie->pdev = pdev; 855 856 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 857 pcie->base = devm_ioremap_resource(dev, res); 858 if (IS_ERR(pcie->base)) 859 return PTR_ERR(pcie->base); 860 861 irq = platform_get_irq(pdev, 0); 862 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 863 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 864 pcie); 865 if (ret) { 866 dev_err(dev, "Failed to register interrupt\n"); 867 return ret; 868 } 869 870 ret = advk_pcie_parse_request_of_pci_ranges(pcie); 871 if (ret) { 872 dev_err(dev, "Failed to parse resources\n"); 873 return ret; 874 } 875 876 advk_pcie_setup_hw(pcie); 877 878 ret = advk_pcie_init_irq_domain(pcie); 879 if (ret) { 880 dev_err(dev, "Failed to initialize irq\n"); 881 return ret; 882 } 883 884 ret = advk_pcie_init_msi_irq_domain(pcie); 885 if (ret) { 886 dev_err(dev, "Failed to initialize irq\n"); 887 advk_pcie_remove_irq_domain(pcie); 888 return ret; 889 } 890 891 list_splice_init(&pcie->resources, &bridge->windows); 892 bridge->dev.parent = dev; 893 bridge->sysdata = pcie; 894 bridge->busnr = 0; 895 bridge->ops = &advk_pcie_ops; 896 bridge->map_irq = of_irq_parse_and_map_pci; 897 bridge->swizzle_irq = pci_common_swizzle; 898 899 ret = pci_host_probe(bridge); 900 if (ret < 0) { 901 advk_pcie_remove_msi_irq_domain(pcie); 902 advk_pcie_remove_irq_domain(pcie); 903 return ret; 904 } 905 906 return 0; 907 } 908 909 static const struct of_device_id advk_pcie_of_match_table[] = { 910 { .compatible = "marvell,armada-3700-pcie", }, 911 {}, 912 }; 913 914 static struct platform_driver advk_pcie_driver = { 915 .driver = { 916 .name = "advk-pcie", 917 .of_match_table = advk_pcie_of_match_table, 918 /* Driver unloading/unbinding currently not supported */ 919 .suppress_bind_attrs = true, 920 }, 921 .probe = advk_pcie_probe, 922 }; 923 builtin_platform_driver(advk_pcie_driver); 924