1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/init.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/msi.h> 24 #include <linux/of_address.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_pci.h> 27 28 #include "../pci.h" 29 #include "../pci-bridge-emul.h" 30 31 /* PCIe core registers */ 32 #define PCIE_CORE_DEV_ID_REG 0x0 33 #define PCIE_CORE_CMD_STATUS_REG 0x4 34 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 35 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 36 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 37 #define PCIE_CORE_DEV_REV_REG 0x8 38 #define PCIE_CORE_PCIEXP_CAP 0xc0 39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 44 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1 45 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2 46 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3 47 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4 48 /* PIO registers base address and register offsets */ 49 #define PIO_BASE_ADDR 0x4000 50 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 51 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 52 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 53 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 54 #define PIO_COMPLETION_STATUS_SHIFT 7 55 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 56 #define PIO_COMPLETION_STATUS_OK 0 57 #define PIO_COMPLETION_STATUS_UR 1 58 #define PIO_COMPLETION_STATUS_CRS 2 59 #define PIO_COMPLETION_STATUS_CA 4 60 #define PIO_NON_POSTED_REQ BIT(0) 61 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 62 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 63 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 64 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 65 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 66 #define PIO_START (PIO_BASE_ADDR + 0x1c) 67 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 68 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 69 70 /* Aardvark Control registers */ 71 #define CONTROL_BASE_ADDR 0x4800 72 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 73 #define PCIE_GEN_SEL_MSK 0x3 74 #define PCIE_GEN_SEL_SHIFT 0x0 75 #define SPEED_GEN_1 0 76 #define SPEED_GEN_2 1 77 #define SPEED_GEN_3 2 78 #define IS_RC_MSK 1 79 #define IS_RC_SHIFT 2 80 #define LANE_CNT_MSK 0x18 81 #define LANE_CNT_SHIFT 0x3 82 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 83 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 84 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 85 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 86 #define LINK_TRAINING_EN BIT(6) 87 #define LEGACY_INTA BIT(28) 88 #define LEGACY_INTB BIT(29) 89 #define LEGACY_INTC BIT(30) 90 #define LEGACY_INTD BIT(31) 91 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 92 #define HOT_RESET_GEN BIT(0) 93 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 94 #define PCIE_CORE_CTRL2_RESERVED 0x7 95 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 96 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 97 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 98 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 99 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) 100 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) 101 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 102 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 103 #define PCIE_MSG_PM_PME_MASK BIT(7) 104 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 105 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 106 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 107 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 108 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 109 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 110 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 111 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 112 #define PCIE_ISR1_FLUSH BIT(5) 113 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 114 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 115 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 116 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 117 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 118 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 119 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 120 121 /* LMI registers base address and register offsets */ 122 #define LMI_BASE_ADDR 0x6000 123 #define CFG_REG (LMI_BASE_ADDR + 0x0) 124 #define LTSSM_SHIFT 24 125 #define LTSSM_MASK 0x3f 126 #define LTSSM_L0 0x10 127 #define RC_BAR_CONFIG 0x300 128 129 /* PCIe core controller registers */ 130 #define CTRL_CORE_BASE_ADDR 0x18000 131 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 132 #define CTRL_MODE_SHIFT 0x0 133 #define CTRL_MODE_MASK 0x1 134 #define PCIE_CORE_MODE_DIRECT 0x0 135 #define PCIE_CORE_MODE_COMMAND 0x1 136 137 /* PCIe Central Interrupts Registers */ 138 #define CENTRAL_INT_BASE_ADDR 0x1b000 139 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 140 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 141 #define PCIE_IRQ_CMDQ_INT BIT(0) 142 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 143 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 144 #define PCIE_IRQ_DMA_INT BIT(4) 145 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 146 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 147 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 148 #define PCIE_IRQ_COMPQ_INT BIT(12) 149 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 150 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 151 #define PCIE_IRQ_CORE_INT BIT(16) 152 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 153 #define PCIE_IRQ_DPMU_INT BIT(18) 154 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 155 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 156 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 157 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 158 #define PCIE_IRQ_EP_STATUS BIT(23) 159 #define PCIE_IRQ_ALL_MASK 0xfff0fb 160 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 161 162 /* Transaction types */ 163 #define PCIE_CONFIG_RD_TYPE0 0x8 164 #define PCIE_CONFIG_RD_TYPE1 0x9 165 #define PCIE_CONFIG_WR_TYPE0 0xa 166 #define PCIE_CONFIG_WR_TYPE1 0xb 167 168 #define PIO_RETRY_CNT 500 169 #define PIO_RETRY_DELAY 2 /* 2 us*/ 170 171 #define LINK_WAIT_MAX_RETRIES 10 172 #define LINK_WAIT_USLEEP_MIN 90000 173 #define LINK_WAIT_USLEEP_MAX 100000 174 #define RETRAIN_WAIT_MAX_RETRIES 10 175 #define RETRAIN_WAIT_USLEEP_US 2000 176 177 #define MSI_IRQ_NUM 32 178 179 struct advk_pcie { 180 struct platform_device *pdev; 181 void __iomem *base; 182 struct irq_domain *irq_domain; 183 struct irq_chip irq_chip; 184 struct irq_domain *msi_domain; 185 struct irq_domain *msi_inner_domain; 186 struct irq_chip msi_bottom_irq_chip; 187 struct irq_chip msi_irq_chip; 188 struct msi_domain_info msi_domain_info; 189 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 190 struct mutex msi_used_lock; 191 u16 msi_msg; 192 int link_gen; 193 struct pci_bridge_emul bridge; 194 struct gpio_desc *reset_gpio; 195 struct phy *phy; 196 }; 197 198 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 199 { 200 writel(val, pcie->base + reg); 201 } 202 203 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 204 { 205 return readl(pcie->base + reg); 206 } 207 208 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) 209 { 210 return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); 211 } 212 213 static int advk_pcie_link_up(struct advk_pcie *pcie) 214 { 215 u32 val, ltssm_state; 216 217 val = advk_readl(pcie, CFG_REG); 218 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 219 return ltssm_state >= LTSSM_L0; 220 } 221 222 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 223 { 224 int retries; 225 226 /* check if the link is up or not */ 227 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 228 if (advk_pcie_link_up(pcie)) 229 return 0; 230 231 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 232 } 233 234 return -ETIMEDOUT; 235 } 236 237 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 238 { 239 size_t retries; 240 241 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 242 if (!advk_pcie_link_up(pcie)) 243 break; 244 udelay(RETRAIN_WAIT_USLEEP_US); 245 } 246 } 247 248 static void advk_pcie_issue_perst(struct advk_pcie *pcie) 249 { 250 u32 reg; 251 252 if (!pcie->reset_gpio) 253 return; 254 255 /* 256 * As required by PCI Express spec (PCI Express Base Specification, REV. 257 * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay 258 * for at least 100ms after de-asserting PERST# signal is needed before 259 * link training is enabled. So ensure that link training is disabled 260 * prior de-asserting PERST# signal to fulfill that PCI Express spec 261 * requirement. 262 */ 263 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 264 reg &= ~LINK_TRAINING_EN; 265 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 266 267 /* 10ms delay is needed for some cards */ 268 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); 269 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 270 usleep_range(10000, 11000); 271 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 272 } 273 274 static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) 275 { 276 int ret, neg_gen; 277 u32 reg; 278 279 /* Setup link speed */ 280 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 281 reg &= ~PCIE_GEN_SEL_MSK; 282 if (gen == 3) 283 reg |= SPEED_GEN_3; 284 else if (gen == 2) 285 reg |= SPEED_GEN_2; 286 else 287 reg |= SPEED_GEN_1; 288 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 289 290 /* 291 * Enable link training. This is not needed in every call to this 292 * function, just once suffices, but it does not break anything either. 293 */ 294 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 295 reg |= LINK_TRAINING_EN; 296 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 297 298 /* 299 * Start link training immediately after enabling it. 300 * This solves problems for some buggy cards. 301 */ 302 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); 303 reg |= PCI_EXP_LNKCTL_RL; 304 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); 305 306 ret = advk_pcie_wait_for_link(pcie); 307 if (ret) 308 return ret; 309 310 reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); 311 neg_gen = reg & PCI_EXP_LNKSTA_CLS; 312 313 return neg_gen; 314 } 315 316 static void advk_pcie_train_link(struct advk_pcie *pcie) 317 { 318 struct device *dev = &pcie->pdev->dev; 319 int neg_gen = -1, gen; 320 321 /* 322 * Reset PCIe card via PERST# signal. Some cards are not detected 323 * during link training when they are in some non-initial state. 324 */ 325 advk_pcie_issue_perst(pcie); 326 327 /* 328 * PERST# signal could have been asserted by pinctrl subsystem before 329 * probe() callback has been called or issued explicitly by reset gpio 330 * function advk_pcie_issue_perst(), making the endpoint going into 331 * fundamental reset. As required by PCI Express spec a delay for at 332 * least 100ms after such a reset before link training is needed. 333 */ 334 msleep(PCI_PM_D3COLD_WAIT); 335 336 /* 337 * Try link training at link gen specified by device tree property 338 * 'max-link-speed'. If this fails, iteratively train at lower gen. 339 */ 340 for (gen = pcie->link_gen; gen > 0; --gen) { 341 neg_gen = advk_pcie_train_at_gen(pcie, gen); 342 if (neg_gen > 0) 343 break; 344 } 345 346 if (neg_gen < 0) 347 goto err; 348 349 /* 350 * After successful training if negotiated gen is lower than requested, 351 * train again on negotiated gen. This solves some stability issues for 352 * some buggy gen1 cards. 353 */ 354 if (neg_gen < gen) { 355 gen = neg_gen; 356 neg_gen = advk_pcie_train_at_gen(pcie, gen); 357 } 358 359 if (neg_gen == gen) { 360 dev_info(dev, "link up at gen %i\n", gen); 361 return; 362 } 363 364 err: 365 dev_err(dev, "link never came up\n"); 366 } 367 368 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 369 { 370 u32 reg; 371 372 /* Enable TX */ 373 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); 374 reg |= PCIE_CORE_REF_CLK_TX_ENABLE; 375 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); 376 377 /* Set to Direct mode */ 378 reg = advk_readl(pcie, CTRL_CONFIG_REG); 379 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 380 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 381 advk_writel(pcie, reg, CTRL_CONFIG_REG); 382 383 /* Set PCI global control register to RC mode */ 384 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 385 reg |= (IS_RC_MSK << IS_RC_SHIFT); 386 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 387 388 /* Set Advanced Error Capabilities and Control PF0 register */ 389 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 390 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 391 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 392 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 393 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 394 395 /* Set PCIe Device Control register */ 396 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 397 reg &= ~PCI_EXP_DEVCTL_RELAX_EN; 398 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 399 reg &= ~PCI_EXP_DEVCTL_READRQ; 400 reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ 401 reg |= PCI_EXP_DEVCTL_READRQ_512B; 402 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 403 404 /* Program PCIe Control 2 to disable strict ordering */ 405 reg = PCIE_CORE_CTRL2_RESERVED | 406 PCIE_CORE_CTRL2_TD_ENABLE; 407 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 408 409 /* Set lane X1 */ 410 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 411 reg &= ~LANE_CNT_MSK; 412 reg |= LANE_COUNT_1; 413 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 414 415 /* Enable MSI */ 416 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 417 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 418 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 419 420 /* Clear all interrupts */ 421 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 422 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 423 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 424 425 /* Disable All ISR0/1 Sources */ 426 reg = PCIE_ISR0_ALL_MASK; 427 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 428 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 429 430 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 431 432 /* Unmask all MSIs */ 433 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 434 435 /* Enable summary interrupt for GIC SPI source */ 436 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 437 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 438 439 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 440 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 441 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 442 443 /* Bypass the address window mapping for PIO */ 444 reg = advk_readl(pcie, PIO_CTRL); 445 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 446 advk_writel(pcie, reg, PIO_CTRL); 447 448 advk_pcie_train_link(pcie); 449 450 /* 451 * FIXME: The following register update is suspicious. This register is 452 * applicable only when the PCI controller is configured for Endpoint 453 * mode, not as a Root Complex. But apparently when this code is 454 * removed, some cards stop working. This should be investigated and 455 * a comment explaining this should be put here. 456 */ 457 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 458 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 459 PCIE_CORE_CMD_IO_ACCESS_EN | 460 PCIE_CORE_CMD_MEM_IO_REQ_EN; 461 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 462 } 463 464 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 465 { 466 struct device *dev = &pcie->pdev->dev; 467 u32 reg; 468 unsigned int status; 469 char *strcomp_status, *str_posted; 470 471 reg = advk_readl(pcie, PIO_STAT); 472 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 473 PIO_COMPLETION_STATUS_SHIFT; 474 475 if (!status) 476 return; 477 478 switch (status) { 479 case PIO_COMPLETION_STATUS_UR: 480 strcomp_status = "UR"; 481 break; 482 case PIO_COMPLETION_STATUS_CRS: 483 strcomp_status = "CRS"; 484 break; 485 case PIO_COMPLETION_STATUS_CA: 486 strcomp_status = "CA"; 487 break; 488 default: 489 strcomp_status = "Unknown"; 490 break; 491 } 492 493 if (reg & PIO_NON_POSTED_REQ) 494 str_posted = "Non-posted"; 495 else 496 str_posted = "Posted"; 497 498 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 499 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 500 } 501 502 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 503 { 504 struct device *dev = &pcie->pdev->dev; 505 int i; 506 507 for (i = 0; i < PIO_RETRY_CNT; i++) { 508 u32 start, isr; 509 510 start = advk_readl(pcie, PIO_START); 511 isr = advk_readl(pcie, PIO_ISR); 512 if (!start && isr) 513 return 0; 514 udelay(PIO_RETRY_DELAY); 515 } 516 517 dev_err(dev, "config read/write timed out\n"); 518 return -ETIMEDOUT; 519 } 520 521 522 static pci_bridge_emul_read_status_t 523 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 524 int reg, u32 *value) 525 { 526 struct advk_pcie *pcie = bridge->data; 527 528 529 switch (reg) { 530 case PCI_EXP_SLTCTL: 531 *value = PCI_EXP_SLTSTA_PDS << 16; 532 return PCI_BRIDGE_EMUL_HANDLED; 533 534 case PCI_EXP_RTCTL: { 535 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 536 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; 537 return PCI_BRIDGE_EMUL_HANDLED; 538 } 539 540 case PCI_EXP_RTSTA: { 541 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); 542 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); 543 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16); 544 return PCI_BRIDGE_EMUL_HANDLED; 545 } 546 547 case PCI_EXP_LNKCTL: { 548 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 549 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 550 ~(PCI_EXP_LNKSTA_LT << 16); 551 if (!advk_pcie_link_up(pcie)) 552 val |= (PCI_EXP_LNKSTA_LT << 16); 553 *value = val; 554 return PCI_BRIDGE_EMUL_HANDLED; 555 } 556 557 case PCI_CAP_LIST_ID: 558 case PCI_EXP_DEVCAP: 559 case PCI_EXP_DEVCTL: 560 case PCI_EXP_LNKCAP: 561 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 562 return PCI_BRIDGE_EMUL_HANDLED; 563 default: 564 return PCI_BRIDGE_EMUL_NOT_HANDLED; 565 } 566 567 } 568 569 static void 570 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 571 int reg, u32 old, u32 new, u32 mask) 572 { 573 struct advk_pcie *pcie = bridge->data; 574 575 switch (reg) { 576 case PCI_EXP_DEVCTL: 577 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 578 break; 579 580 case PCI_EXP_LNKCTL: 581 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 582 if (new & PCI_EXP_LNKCTL_RL) 583 advk_pcie_wait_for_retrain(pcie); 584 break; 585 586 case PCI_EXP_RTCTL: { 587 /* Only mask/unmask PME interrupt */ 588 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & 589 ~PCIE_MSG_PM_PME_MASK; 590 if ((new & PCI_EXP_RTCTL_PMEIE) == 0) 591 val |= PCIE_MSG_PM_PME_MASK; 592 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 593 break; 594 } 595 596 case PCI_EXP_RTSTA: 597 new = (new & PCI_EXP_RTSTA_PME) >> 9; 598 advk_writel(pcie, new, PCIE_ISR0_REG); 599 break; 600 601 default: 602 break; 603 } 604 } 605 606 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 607 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 608 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 609 }; 610 611 /* 612 * Initialize the configuration space of the PCI-to-PCI bridge 613 * associated with the given PCIe interface. 614 */ 615 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 616 { 617 struct pci_bridge_emul *bridge = &pcie->bridge; 618 619 bridge->conf.vendor = 620 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 621 bridge->conf.device = 622 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 623 bridge->conf.class_revision = 624 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 625 626 /* Support 32 bits I/O addressing */ 627 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 628 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 629 630 /* Support 64 bits memory pref */ 631 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 632 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 633 634 /* Support interrupt A for MSI feature */ 635 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; 636 637 bridge->has_pcie = true; 638 bridge->data = pcie; 639 bridge->ops = &advk_pci_bridge_emul_ops; 640 641 return pci_bridge_emul_init(bridge, 0); 642 } 643 644 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 645 int devfn) 646 { 647 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) 648 return false; 649 650 /* 651 * If the link goes down after we check for link-up, nothing bad 652 * happens but the config access times out. 653 */ 654 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) 655 return false; 656 657 return true; 658 } 659 660 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 661 int where, int size, u32 *val) 662 { 663 struct advk_pcie *pcie = bus->sysdata; 664 u32 reg; 665 int ret; 666 667 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 668 *val = 0xffffffff; 669 return PCIBIOS_DEVICE_NOT_FOUND; 670 } 671 672 if (pci_is_root_bus(bus)) 673 return pci_bridge_emul_conf_read(&pcie->bridge, where, 674 size, val); 675 676 /* Start PIO */ 677 advk_writel(pcie, 0, PIO_START); 678 advk_writel(pcie, 1, PIO_ISR); 679 680 /* Program the control register */ 681 reg = advk_readl(pcie, PIO_CTRL); 682 reg &= ~PIO_CTRL_TYPE_MASK; 683 if (pci_is_root_bus(bus->parent)) 684 reg |= PCIE_CONFIG_RD_TYPE0; 685 else 686 reg |= PCIE_CONFIG_RD_TYPE1; 687 advk_writel(pcie, reg, PIO_CTRL); 688 689 /* Program the address registers */ 690 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 691 advk_writel(pcie, reg, PIO_ADDR_LS); 692 advk_writel(pcie, 0, PIO_ADDR_MS); 693 694 /* Program the data strobe */ 695 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 696 697 /* Start the transfer */ 698 advk_writel(pcie, 1, PIO_START); 699 700 ret = advk_pcie_wait_pio(pcie); 701 if (ret < 0) { 702 *val = 0xffffffff; 703 return PCIBIOS_SET_FAILED; 704 } 705 706 advk_pcie_check_pio_status(pcie); 707 708 /* Get the read result */ 709 *val = advk_readl(pcie, PIO_RD_DATA); 710 if (size == 1) 711 *val = (*val >> (8 * (where & 3))) & 0xff; 712 else if (size == 2) 713 *val = (*val >> (8 * (where & 3))) & 0xffff; 714 715 return PCIBIOS_SUCCESSFUL; 716 } 717 718 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 719 int where, int size, u32 val) 720 { 721 struct advk_pcie *pcie = bus->sysdata; 722 u32 reg; 723 u32 data_strobe = 0x0; 724 int offset; 725 int ret; 726 727 if (!advk_pcie_valid_device(pcie, bus, devfn)) 728 return PCIBIOS_DEVICE_NOT_FOUND; 729 730 if (pci_is_root_bus(bus)) 731 return pci_bridge_emul_conf_write(&pcie->bridge, where, 732 size, val); 733 734 if (where % size) 735 return PCIBIOS_SET_FAILED; 736 737 /* Start PIO */ 738 advk_writel(pcie, 0, PIO_START); 739 advk_writel(pcie, 1, PIO_ISR); 740 741 /* Program the control register */ 742 reg = advk_readl(pcie, PIO_CTRL); 743 reg &= ~PIO_CTRL_TYPE_MASK; 744 if (pci_is_root_bus(bus->parent)) 745 reg |= PCIE_CONFIG_WR_TYPE0; 746 else 747 reg |= PCIE_CONFIG_WR_TYPE1; 748 advk_writel(pcie, reg, PIO_CTRL); 749 750 /* Program the address registers */ 751 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 752 advk_writel(pcie, reg, PIO_ADDR_LS); 753 advk_writel(pcie, 0, PIO_ADDR_MS); 754 755 /* Calculate the write strobe */ 756 offset = where & 0x3; 757 reg = val << (8 * offset); 758 data_strobe = GENMASK(size - 1, 0) << offset; 759 760 /* Program the data register */ 761 advk_writel(pcie, reg, PIO_WR_DATA); 762 763 /* Program the data strobe */ 764 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 765 766 /* Start the transfer */ 767 advk_writel(pcie, 1, PIO_START); 768 769 ret = advk_pcie_wait_pio(pcie); 770 if (ret < 0) 771 return PCIBIOS_SET_FAILED; 772 773 advk_pcie_check_pio_status(pcie); 774 775 return PCIBIOS_SUCCESSFUL; 776 } 777 778 static struct pci_ops advk_pcie_ops = { 779 .read = advk_pcie_rd_conf, 780 .write = advk_pcie_wr_conf, 781 }; 782 783 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 784 struct msi_msg *msg) 785 { 786 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 787 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 788 789 msg->address_lo = lower_32_bits(msi_msg); 790 msg->address_hi = upper_32_bits(msi_msg); 791 msg->data = data->irq; 792 } 793 794 static int advk_msi_set_affinity(struct irq_data *irq_data, 795 const struct cpumask *mask, bool force) 796 { 797 return -EINVAL; 798 } 799 800 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 801 unsigned int virq, 802 unsigned int nr_irqs, void *args) 803 { 804 struct advk_pcie *pcie = domain->host_data; 805 int hwirq, i; 806 807 mutex_lock(&pcie->msi_used_lock); 808 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 809 0, nr_irqs, 0); 810 if (hwirq >= MSI_IRQ_NUM) { 811 mutex_unlock(&pcie->msi_used_lock); 812 return -ENOSPC; 813 } 814 815 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 816 mutex_unlock(&pcie->msi_used_lock); 817 818 for (i = 0; i < nr_irqs; i++) 819 irq_domain_set_info(domain, virq + i, hwirq + i, 820 &pcie->msi_bottom_irq_chip, 821 domain->host_data, handle_simple_irq, 822 NULL, NULL); 823 824 return hwirq; 825 } 826 827 static void advk_msi_irq_domain_free(struct irq_domain *domain, 828 unsigned int virq, unsigned int nr_irqs) 829 { 830 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 831 struct advk_pcie *pcie = domain->host_data; 832 833 mutex_lock(&pcie->msi_used_lock); 834 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 835 mutex_unlock(&pcie->msi_used_lock); 836 } 837 838 static const struct irq_domain_ops advk_msi_domain_ops = { 839 .alloc = advk_msi_irq_domain_alloc, 840 .free = advk_msi_irq_domain_free, 841 }; 842 843 static void advk_pcie_irq_mask(struct irq_data *d) 844 { 845 struct advk_pcie *pcie = d->domain->host_data; 846 irq_hw_number_t hwirq = irqd_to_hwirq(d); 847 u32 mask; 848 849 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 850 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 851 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 852 } 853 854 static void advk_pcie_irq_unmask(struct irq_data *d) 855 { 856 struct advk_pcie *pcie = d->domain->host_data; 857 irq_hw_number_t hwirq = irqd_to_hwirq(d); 858 u32 mask; 859 860 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 861 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 862 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 863 } 864 865 static int advk_pcie_irq_map(struct irq_domain *h, 866 unsigned int virq, irq_hw_number_t hwirq) 867 { 868 struct advk_pcie *pcie = h->host_data; 869 870 advk_pcie_irq_mask(irq_get_irq_data(virq)); 871 irq_set_status_flags(virq, IRQ_LEVEL); 872 irq_set_chip_and_handler(virq, &pcie->irq_chip, 873 handle_level_irq); 874 irq_set_chip_data(virq, pcie); 875 876 return 0; 877 } 878 879 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 880 .map = advk_pcie_irq_map, 881 .xlate = irq_domain_xlate_onecell, 882 }; 883 884 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 885 { 886 struct device *dev = &pcie->pdev->dev; 887 struct device_node *node = dev->of_node; 888 struct irq_chip *bottom_ic, *msi_ic; 889 struct msi_domain_info *msi_di; 890 phys_addr_t msi_msg_phys; 891 892 mutex_init(&pcie->msi_used_lock); 893 894 bottom_ic = &pcie->msi_bottom_irq_chip; 895 896 bottom_ic->name = "MSI"; 897 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 898 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 899 900 msi_ic = &pcie->msi_irq_chip; 901 msi_ic->name = "advk-MSI"; 902 903 msi_di = &pcie->msi_domain_info; 904 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 905 MSI_FLAG_MULTI_PCI_MSI; 906 msi_di->chip = msi_ic; 907 908 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 909 910 advk_writel(pcie, lower_32_bits(msi_msg_phys), 911 PCIE_MSI_ADDR_LOW_REG); 912 advk_writel(pcie, upper_32_bits(msi_msg_phys), 913 PCIE_MSI_ADDR_HIGH_REG); 914 915 pcie->msi_inner_domain = 916 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 917 &advk_msi_domain_ops, pcie); 918 if (!pcie->msi_inner_domain) 919 return -ENOMEM; 920 921 pcie->msi_domain = 922 pci_msi_create_irq_domain(of_node_to_fwnode(node), 923 msi_di, pcie->msi_inner_domain); 924 if (!pcie->msi_domain) { 925 irq_domain_remove(pcie->msi_inner_domain); 926 return -ENOMEM; 927 } 928 929 return 0; 930 } 931 932 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 933 { 934 irq_domain_remove(pcie->msi_domain); 935 irq_domain_remove(pcie->msi_inner_domain); 936 } 937 938 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 939 { 940 struct device *dev = &pcie->pdev->dev; 941 struct device_node *node = dev->of_node; 942 struct device_node *pcie_intc_node; 943 struct irq_chip *irq_chip; 944 int ret = 0; 945 946 pcie_intc_node = of_get_next_child(node, NULL); 947 if (!pcie_intc_node) { 948 dev_err(dev, "No PCIe Intc node found\n"); 949 return -ENODEV; 950 } 951 952 irq_chip = &pcie->irq_chip; 953 954 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 955 dev_name(dev)); 956 if (!irq_chip->name) { 957 ret = -ENOMEM; 958 goto out_put_node; 959 } 960 961 irq_chip->irq_mask = advk_pcie_irq_mask; 962 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 963 irq_chip->irq_unmask = advk_pcie_irq_unmask; 964 965 pcie->irq_domain = 966 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 967 &advk_pcie_irq_domain_ops, pcie); 968 if (!pcie->irq_domain) { 969 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 970 ret = -ENOMEM; 971 goto out_put_node; 972 } 973 974 out_put_node: 975 of_node_put(pcie_intc_node); 976 return ret; 977 } 978 979 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 980 { 981 irq_domain_remove(pcie->irq_domain); 982 } 983 984 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 985 { 986 u32 msi_val, msi_mask, msi_status, msi_idx; 987 u16 msi_data; 988 989 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 990 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 991 msi_status = msi_val & ~msi_mask; 992 993 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 994 if (!(BIT(msi_idx) & msi_status)) 995 continue; 996 997 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 998 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 999 generic_handle_irq(msi_data); 1000 } 1001 1002 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 1003 PCIE_ISR0_REG); 1004 } 1005 1006 static void advk_pcie_handle_int(struct advk_pcie *pcie) 1007 { 1008 u32 isr0_val, isr0_mask, isr0_status; 1009 u32 isr1_val, isr1_mask, isr1_status; 1010 int i, virq; 1011 1012 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 1013 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 1014 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 1015 1016 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 1017 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1018 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 1019 1020 if (!isr0_status && !isr1_status) { 1021 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 1022 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 1023 return; 1024 } 1025 1026 /* Process MSI interrupts */ 1027 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 1028 advk_pcie_handle_msi(pcie); 1029 1030 /* Process legacy interrupts */ 1031 for (i = 0; i < PCI_NUM_INTX; i++) { 1032 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 1033 continue; 1034 1035 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 1036 PCIE_ISR1_REG); 1037 1038 virq = irq_find_mapping(pcie->irq_domain, i); 1039 generic_handle_irq(virq); 1040 } 1041 } 1042 1043 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 1044 { 1045 struct advk_pcie *pcie = arg; 1046 u32 status; 1047 1048 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 1049 if (!(status & PCIE_IRQ_CORE_INT)) 1050 return IRQ_NONE; 1051 1052 advk_pcie_handle_int(pcie); 1053 1054 /* Clear interrupt */ 1055 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 1056 1057 return IRQ_HANDLED; 1058 } 1059 1060 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) 1061 { 1062 phy_power_off(pcie->phy); 1063 phy_exit(pcie->phy); 1064 } 1065 1066 static int advk_pcie_enable_phy(struct advk_pcie *pcie) 1067 { 1068 int ret; 1069 1070 if (!pcie->phy) 1071 return 0; 1072 1073 ret = phy_init(pcie->phy); 1074 if (ret) 1075 return ret; 1076 1077 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); 1078 if (ret) { 1079 phy_exit(pcie->phy); 1080 return ret; 1081 } 1082 1083 ret = phy_power_on(pcie->phy); 1084 if (ret == -EOPNOTSUPP) { 1085 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); 1086 } else if (ret) { 1087 phy_exit(pcie->phy); 1088 return ret; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static int advk_pcie_setup_phy(struct advk_pcie *pcie) 1095 { 1096 struct device *dev = &pcie->pdev->dev; 1097 struct device_node *node = dev->of_node; 1098 int ret = 0; 1099 1100 pcie->phy = devm_of_phy_get(dev, node, NULL); 1101 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) 1102 return PTR_ERR(pcie->phy); 1103 1104 /* Old bindings miss the PHY handle */ 1105 if (IS_ERR(pcie->phy)) { 1106 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); 1107 pcie->phy = NULL; 1108 return 0; 1109 } 1110 1111 ret = advk_pcie_enable_phy(pcie); 1112 if (ret) 1113 dev_err(dev, "Failed to initialize PHY (%d)\n", ret); 1114 1115 return ret; 1116 } 1117 1118 static int advk_pcie_probe(struct platform_device *pdev) 1119 { 1120 struct device *dev = &pdev->dev; 1121 struct advk_pcie *pcie; 1122 struct pci_host_bridge *bridge; 1123 int ret, irq; 1124 1125 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 1126 if (!bridge) 1127 return -ENOMEM; 1128 1129 pcie = pci_host_bridge_priv(bridge); 1130 pcie->pdev = pdev; 1131 platform_set_drvdata(pdev, pcie); 1132 1133 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1134 if (IS_ERR(pcie->base)) 1135 return PTR_ERR(pcie->base); 1136 1137 irq = platform_get_irq(pdev, 0); 1138 if (irq < 0) 1139 return irq; 1140 1141 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 1142 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 1143 pcie); 1144 if (ret) { 1145 dev_err(dev, "Failed to register interrupt\n"); 1146 return ret; 1147 } 1148 1149 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, 1150 "reset-gpios", 0, 1151 GPIOD_OUT_LOW, 1152 "pcie1-reset"); 1153 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); 1154 if (ret) { 1155 if (ret == -ENOENT) { 1156 pcie->reset_gpio = NULL; 1157 } else { 1158 if (ret != -EPROBE_DEFER) 1159 dev_err(dev, "Failed to get reset-gpio: %i\n", 1160 ret); 1161 return ret; 1162 } 1163 } 1164 1165 ret = of_pci_get_max_link_speed(dev->of_node); 1166 if (ret <= 0 || ret > 3) 1167 pcie->link_gen = 3; 1168 else 1169 pcie->link_gen = ret; 1170 1171 ret = advk_pcie_setup_phy(pcie); 1172 if (ret) 1173 return ret; 1174 1175 advk_pcie_setup_hw(pcie); 1176 1177 ret = advk_sw_pci_bridge_init(pcie); 1178 if (ret) { 1179 dev_err(dev, "Failed to register emulated root PCI bridge\n"); 1180 return ret; 1181 } 1182 1183 ret = advk_pcie_init_irq_domain(pcie); 1184 if (ret) { 1185 dev_err(dev, "Failed to initialize irq\n"); 1186 return ret; 1187 } 1188 1189 ret = advk_pcie_init_msi_irq_domain(pcie); 1190 if (ret) { 1191 dev_err(dev, "Failed to initialize irq\n"); 1192 advk_pcie_remove_irq_domain(pcie); 1193 return ret; 1194 } 1195 1196 bridge->sysdata = pcie; 1197 bridge->ops = &advk_pcie_ops; 1198 1199 ret = pci_host_probe(bridge); 1200 if (ret < 0) { 1201 advk_pcie_remove_msi_irq_domain(pcie); 1202 advk_pcie_remove_irq_domain(pcie); 1203 return ret; 1204 } 1205 1206 return 0; 1207 } 1208 1209 static int advk_pcie_remove(struct platform_device *pdev) 1210 { 1211 struct advk_pcie *pcie = platform_get_drvdata(pdev); 1212 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1213 1214 pci_lock_rescan_remove(); 1215 pci_stop_root_bus(bridge->bus); 1216 pci_remove_root_bus(bridge->bus); 1217 pci_unlock_rescan_remove(); 1218 1219 advk_pcie_remove_msi_irq_domain(pcie); 1220 advk_pcie_remove_irq_domain(pcie); 1221 1222 return 0; 1223 } 1224 1225 static const struct of_device_id advk_pcie_of_match_table[] = { 1226 { .compatible = "marvell,armada-3700-pcie", }, 1227 {}, 1228 }; 1229 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table); 1230 1231 static struct platform_driver advk_pcie_driver = { 1232 .driver = { 1233 .name = "advk-pcie", 1234 .of_match_table = advk_pcie_of_match_table, 1235 }, 1236 .probe = advk_pcie_probe, 1237 .remove = advk_pcie_remove, 1238 }; 1239 module_platform_driver(advk_pcie_driver); 1240 1241 MODULE_DESCRIPTION("Aardvark PCIe controller"); 1242 MODULE_LICENSE("GPL v2"); 1243