1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/init.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/msi.h> 24 #include <linux/of_address.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_pci.h> 27 28 #include "../pci.h" 29 #include "../pci-bridge-emul.h" 30 31 /* PCIe core registers */ 32 #define PCIE_CORE_DEV_ID_REG 0x0 33 #define PCIE_CORE_CMD_STATUS_REG 0x4 34 #define PCIE_CORE_DEV_REV_REG 0x8 35 #define PCIE_CORE_PCIEXP_CAP 0xc0 36 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 41 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1 42 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2 43 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3 44 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4 45 /* PIO registers base address and register offsets */ 46 #define PIO_BASE_ADDR 0x4000 47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 50 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 51 #define PIO_COMPLETION_STATUS_SHIFT 7 52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 53 #define PIO_COMPLETION_STATUS_OK 0 54 #define PIO_COMPLETION_STATUS_UR 1 55 #define PIO_COMPLETION_STATUS_CRS 2 56 #define PIO_COMPLETION_STATUS_CA 4 57 #define PIO_NON_POSTED_REQ BIT(10) 58 #define PIO_ERR_STATUS BIT(11) 59 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 60 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 61 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 62 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 63 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 64 #define PIO_START (PIO_BASE_ADDR + 0x1c) 65 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 66 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 67 68 /* Aardvark Control registers */ 69 #define CONTROL_BASE_ADDR 0x4800 70 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 71 #define PCIE_GEN_SEL_MSK 0x3 72 #define PCIE_GEN_SEL_SHIFT 0x0 73 #define SPEED_GEN_1 0 74 #define SPEED_GEN_2 1 75 #define SPEED_GEN_3 2 76 #define IS_RC_MSK 1 77 #define IS_RC_SHIFT 2 78 #define LANE_CNT_MSK 0x18 79 #define LANE_CNT_SHIFT 0x3 80 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 81 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 82 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 83 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 84 #define LINK_TRAINING_EN BIT(6) 85 #define LEGACY_INTA BIT(28) 86 #define LEGACY_INTB BIT(29) 87 #define LEGACY_INTC BIT(30) 88 #define LEGACY_INTD BIT(31) 89 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 90 #define HOT_RESET_GEN BIT(0) 91 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 92 #define PCIE_CORE_CTRL2_RESERVED 0x7 93 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 94 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 95 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 96 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 97 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) 98 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) 99 #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2) 100 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 101 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 102 #define PCIE_MSG_PM_PME_MASK BIT(7) 103 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 104 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 105 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 106 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 107 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) 108 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 109 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 110 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 111 #define PCIE_ISR1_FLUSH BIT(5) 112 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 113 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0) 114 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 115 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 116 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 117 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 118 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 119 #define PCIE_MSI_DATA_MASK GENMASK(15, 0) 120 121 /* PCIe window configuration */ 122 #define OB_WIN_BASE_ADDR 0x4c00 123 #define OB_WIN_BLOCK_SIZE 0x20 124 #define OB_WIN_COUNT 8 125 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ 126 OB_WIN_BLOCK_SIZE * (win) + \ 127 (offset)) 128 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) 129 #define OB_WIN_ENABLE BIT(0) 130 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) 131 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) 132 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) 133 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) 134 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) 135 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) 136 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) 137 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) 138 #define OB_WIN_FUNC_NUM_SHIFT 24 139 #define OB_WIN_FUNC_NUM_ENABLE BIT(23) 140 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) 141 #define OB_WIN_BUS_NUM_BITS_SHIFT 20 142 #define OB_WIN_MSG_CODE_ENABLE BIT(22) 143 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) 144 #define OB_WIN_MSG_CODE_SHIFT 14 145 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12) 146 #define OB_WIN_ATTR_ENABLE BIT(11) 147 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) 148 #define OB_WIN_ATTR_TC_SHIFT 8 149 #define OB_WIN_ATTR_RELAXED BIT(7) 150 #define OB_WIN_ATTR_NOSNOOP BIT(6) 151 #define OB_WIN_ATTR_POISON BIT(5) 152 #define OB_WIN_ATTR_IDO BIT(4) 153 #define OB_WIN_TYPE_MASK GENMASK(3, 0) 154 #define OB_WIN_TYPE_SHIFT 0 155 #define OB_WIN_TYPE_MEM 0x0 156 #define OB_WIN_TYPE_IO 0x4 157 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8 158 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9 159 #define OB_WIN_TYPE_MSG 0xc 160 161 /* LMI registers base address and register offsets */ 162 #define LMI_BASE_ADDR 0x6000 163 #define CFG_REG (LMI_BASE_ADDR + 0x0) 164 #define LTSSM_SHIFT 24 165 #define LTSSM_MASK 0x3f 166 #define RC_BAR_CONFIG 0x300 167 168 /* LTSSM values in CFG_REG */ 169 enum { 170 LTSSM_DETECT_QUIET = 0x0, 171 LTSSM_DETECT_ACTIVE = 0x1, 172 LTSSM_POLLING_ACTIVE = 0x2, 173 LTSSM_POLLING_COMPLIANCE = 0x3, 174 LTSSM_POLLING_CONFIGURATION = 0x4, 175 LTSSM_CONFIG_LINKWIDTH_START = 0x5, 176 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6, 177 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7, 178 LTSSM_CONFIG_LANENUM_WAIT = 0x8, 179 LTSSM_CONFIG_COMPLETE = 0x9, 180 LTSSM_CONFIG_IDLE = 0xa, 181 LTSSM_RECOVERY_RCVR_LOCK = 0xb, 182 LTSSM_RECOVERY_SPEED = 0xc, 183 LTSSM_RECOVERY_RCVR_CFG = 0xd, 184 LTSSM_RECOVERY_IDLE = 0xe, 185 LTSSM_L0 = 0x10, 186 LTSSM_RX_L0S_ENTRY = 0x11, 187 LTSSM_RX_L0S_IDLE = 0x12, 188 LTSSM_RX_L0S_FTS = 0x13, 189 LTSSM_TX_L0S_ENTRY = 0x14, 190 LTSSM_TX_L0S_IDLE = 0x15, 191 LTSSM_TX_L0S_FTS = 0x16, 192 LTSSM_L1_ENTRY = 0x17, 193 LTSSM_L1_IDLE = 0x18, 194 LTSSM_L2_IDLE = 0x19, 195 LTSSM_L2_TRANSMIT_WAKE = 0x1a, 196 LTSSM_DISABLED = 0x20, 197 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21, 198 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22, 199 LTSSM_LOOPBACK_EXIT_MASTER = 0x23, 200 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24, 201 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25, 202 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26, 203 LTSSM_HOT_RESET = 0x27, 204 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28, 205 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29, 206 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a, 207 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b, 208 }; 209 210 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) 211 212 /* PCIe core controller registers */ 213 #define CTRL_CORE_BASE_ADDR 0x18000 214 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 215 #define CTRL_MODE_SHIFT 0x0 216 #define CTRL_MODE_MASK 0x1 217 #define PCIE_CORE_MODE_DIRECT 0x0 218 #define PCIE_CORE_MODE_COMMAND 0x1 219 220 /* PCIe Central Interrupts Registers */ 221 #define CENTRAL_INT_BASE_ADDR 0x1b000 222 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 223 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 224 #define PCIE_IRQ_CMDQ_INT BIT(0) 225 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 226 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 227 #define PCIE_IRQ_DMA_INT BIT(4) 228 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 229 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 230 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 231 #define PCIE_IRQ_COMPQ_INT BIT(12) 232 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 233 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 234 #define PCIE_IRQ_CORE_INT BIT(16) 235 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 236 #define PCIE_IRQ_DPMU_INT BIT(18) 237 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 238 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 239 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 240 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 241 #define PCIE_IRQ_EP_STATUS BIT(23) 242 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0) 243 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 244 245 /* Transaction types */ 246 #define PCIE_CONFIG_RD_TYPE0 0x8 247 #define PCIE_CONFIG_RD_TYPE1 0x9 248 #define PCIE_CONFIG_WR_TYPE0 0xa 249 #define PCIE_CONFIG_WR_TYPE1 0xb 250 251 #define PIO_RETRY_CNT 750000 /* 1.5 s */ 252 #define PIO_RETRY_DELAY 2 /* 2 us*/ 253 254 #define LINK_WAIT_MAX_RETRIES 10 255 #define LINK_WAIT_USLEEP_MIN 90000 256 #define LINK_WAIT_USLEEP_MAX 100000 257 #define RETRAIN_WAIT_MAX_RETRIES 10 258 #define RETRAIN_WAIT_USLEEP_US 2000 259 260 #define MSI_IRQ_NUM 32 261 262 #define CFG_RD_CRS_VAL 0xffff0001 263 264 struct advk_pcie { 265 struct platform_device *pdev; 266 void __iomem *base; 267 struct { 268 phys_addr_t match; 269 phys_addr_t remap; 270 phys_addr_t mask; 271 u32 actions; 272 } wins[OB_WIN_COUNT]; 273 u8 wins_count; 274 struct irq_domain *irq_domain; 275 struct irq_chip irq_chip; 276 raw_spinlock_t irq_lock; 277 struct irq_domain *msi_domain; 278 struct irq_domain *msi_inner_domain; 279 struct irq_chip msi_bottom_irq_chip; 280 struct irq_chip msi_irq_chip; 281 struct msi_domain_info msi_domain_info; 282 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 283 struct mutex msi_used_lock; 284 u16 msi_msg; 285 int link_gen; 286 struct pci_bridge_emul bridge; 287 struct gpio_desc *reset_gpio; 288 struct phy *phy; 289 }; 290 291 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 292 { 293 writel(val, pcie->base + reg); 294 } 295 296 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 297 { 298 return readl(pcie->base + reg); 299 } 300 301 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) 302 { 303 u32 val; 304 u8 ltssm_state; 305 306 val = advk_readl(pcie, CFG_REG); 307 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 308 return ltssm_state; 309 } 310 311 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) 312 { 313 /* check if LTSSM is in normal operation - some L* state */ 314 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 315 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; 316 } 317 318 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) 319 { 320 /* 321 * According to PCIe Base specification 3.0, Table 4-14: Link 322 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle 323 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, 324 * L0s, L1 and L2 states. And according to 3.2.1. Data Link 325 * Control and Management State Machine Rules is DL Up status 326 * reported in DL Active state. 327 */ 328 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 329 return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED; 330 } 331 332 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) 333 { 334 /* 335 * According to PCIe Base specification 3.0, Table 4-14: Link 336 * Status Mapped to the LTSSM is Link Training mapped to LTSSM 337 * Configuration and Recovery states. 338 */ 339 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 340 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START && 341 ltssm_state < LTSSM_L0) || 342 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 && 343 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3)); 344 } 345 346 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 347 { 348 int retries; 349 350 /* check if the link is up or not */ 351 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 352 if (advk_pcie_link_up(pcie)) 353 return 0; 354 355 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 356 } 357 358 return -ETIMEDOUT; 359 } 360 361 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 362 { 363 size_t retries; 364 365 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 366 if (advk_pcie_link_training(pcie)) 367 break; 368 udelay(RETRAIN_WAIT_USLEEP_US); 369 } 370 } 371 372 static void advk_pcie_issue_perst(struct advk_pcie *pcie) 373 { 374 if (!pcie->reset_gpio) 375 return; 376 377 /* 10ms delay is needed for some cards */ 378 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); 379 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 380 usleep_range(10000, 11000); 381 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 382 } 383 384 static void advk_pcie_train_link(struct advk_pcie *pcie) 385 { 386 struct device *dev = &pcie->pdev->dev; 387 u32 reg; 388 int ret; 389 390 /* 391 * Setup PCIe rev / gen compliance based on device tree property 392 * 'max-link-speed' which also forces maximal link speed. 393 */ 394 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 395 reg &= ~PCIE_GEN_SEL_MSK; 396 if (pcie->link_gen == 3) 397 reg |= SPEED_GEN_3; 398 else if (pcie->link_gen == 2) 399 reg |= SPEED_GEN_2; 400 else 401 reg |= SPEED_GEN_1; 402 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 403 404 /* 405 * Set maximal link speed value also into PCIe Link Control 2 register. 406 * Armada 3700 Functional Specification says that default value is based 407 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s. 408 */ 409 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 410 reg &= ~PCI_EXP_LNKCTL2_TLS; 411 if (pcie->link_gen == 3) 412 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT; 413 else if (pcie->link_gen == 2) 414 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT; 415 else 416 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT; 417 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 418 419 /* Enable link training after selecting PCIe generation */ 420 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 421 reg |= LINK_TRAINING_EN; 422 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 423 424 /* 425 * Reset PCIe card via PERST# signal. Some cards are not detected 426 * during link training when they are in some non-initial state. 427 */ 428 advk_pcie_issue_perst(pcie); 429 430 /* 431 * PERST# signal could have been asserted by pinctrl subsystem before 432 * probe() callback has been called or issued explicitly by reset gpio 433 * function advk_pcie_issue_perst(), making the endpoint going into 434 * fundamental reset. As required by PCI Express spec (PCI Express 435 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1 436 * Conventional Reset) a delay for at least 100ms after such a reset 437 * before sending a Configuration Request to the device is needed. 438 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() 439 * waits for link at least 900ms. 440 */ 441 ret = advk_pcie_wait_for_link(pcie); 442 if (ret < 0) 443 dev_err(dev, "link never came up\n"); 444 else 445 dev_info(dev, "link up\n"); 446 } 447 448 /* 449 * Set PCIe address window register which could be used for memory 450 * mapping. 451 */ 452 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, 453 phys_addr_t match, phys_addr_t remap, 454 phys_addr_t mask, u32 actions) 455 { 456 advk_writel(pcie, OB_WIN_ENABLE | 457 lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); 458 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); 459 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); 460 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); 461 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); 462 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); 463 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); 464 } 465 466 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) 467 { 468 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); 469 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); 470 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); 471 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); 472 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); 473 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); 474 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); 475 } 476 477 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 478 { 479 u32 reg; 480 int i; 481 482 /* 483 * Configure PCIe Reference clock. Direction is from the PCIe 484 * controller to the endpoint card, so enable transmitting of 485 * Reference clock differential signal off-chip and disable 486 * receiving off-chip differential signal. 487 */ 488 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); 489 reg |= PCIE_CORE_REF_CLK_TX_ENABLE; 490 reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE; 491 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); 492 493 /* Set to Direct mode */ 494 reg = advk_readl(pcie, CTRL_CONFIG_REG); 495 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 496 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 497 advk_writel(pcie, reg, CTRL_CONFIG_REG); 498 499 /* Set PCI global control register to RC mode */ 500 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 501 reg |= (IS_RC_MSK << IS_RC_SHIFT); 502 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 503 504 /* 505 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. 506 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor 507 * id in high 16 bits. Updating this register changes readback value of 508 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround 509 * for erratum 4.1: "The value of device and vendor ID is incorrect". 510 */ 511 reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; 512 advk_writel(pcie, reg, VENDOR_ID_REG); 513 514 /* 515 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), 516 * because the default value is Mass storage controller (0x010400). 517 * 518 * Note that this Aardvark PCI Bridge does not have compliant Type 1 519 * Configuration Space and it even cannot be accessed via Aardvark's 520 * PCI config space access method. Something like config space is 521 * available in internal Aardvark registers starting at offset 0x0 522 * and is reported as Type 0. In range 0x10 - 0x34 it has totally 523 * different registers. 524 * 525 * Therefore driver uses emulation of PCI Bridge which emulates 526 * access to configuration space via internal Aardvark registers or 527 * emulated configuration buffer. 528 */ 529 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); 530 reg &= ~0xffffff00; 531 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; 532 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); 533 534 /* Disable Root Bridge I/O space, memory space and bus mastering */ 535 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 536 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 537 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 538 539 /* Set Advanced Error Capabilities and Control PF0 register */ 540 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 541 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 542 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 543 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 544 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 545 546 /* Set PCIe Device Control register */ 547 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 548 reg &= ~PCI_EXP_DEVCTL_RELAX_EN; 549 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 550 reg &= ~PCI_EXP_DEVCTL_PAYLOAD; 551 reg &= ~PCI_EXP_DEVCTL_READRQ; 552 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; 553 reg |= PCI_EXP_DEVCTL_READRQ_512B; 554 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 555 556 /* Program PCIe Control 2 to disable strict ordering */ 557 reg = PCIE_CORE_CTRL2_RESERVED | 558 PCIE_CORE_CTRL2_TD_ENABLE; 559 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 560 561 /* Set lane X1 */ 562 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 563 reg &= ~LANE_CNT_MSK; 564 reg |= LANE_COUNT_1; 565 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 566 567 /* Enable MSI */ 568 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 569 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 570 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 571 572 /* Clear all interrupts */ 573 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 574 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 575 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 576 577 /* Disable All ISR0/1 Sources */ 578 reg = PCIE_ISR0_ALL_MASK; 579 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 580 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 581 582 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 583 584 /* Unmask all MSIs */ 585 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 586 587 /* Enable summary interrupt for GIC SPI source */ 588 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 589 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 590 591 /* 592 * Enable AXI address window location generation: 593 * When it is enabled, the default outbound window 594 * configurations (Default User Field: 0xD0074CFC) 595 * are used to transparent address translation for 596 * the outbound transactions. Thus, PCIe address 597 * windows are not required for transparent memory 598 * access when default outbound window configuration 599 * is set for memory access. 600 */ 601 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 602 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 603 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 604 605 /* 606 * Set memory access in Default User Field so it 607 * is not required to configure PCIe address for 608 * transparent memory access. 609 */ 610 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); 611 612 /* 613 * Bypass the address window mapping for PIO: 614 * Since PIO access already contains all required 615 * info over AXI interface by PIO registers, the 616 * address window is not required. 617 */ 618 reg = advk_readl(pcie, PIO_CTRL); 619 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 620 advk_writel(pcie, reg, PIO_CTRL); 621 622 /* 623 * Configure PCIe address windows for non-memory or 624 * non-transparent access as by default PCIe uses 625 * transparent memory access. 626 */ 627 for (i = 0; i < pcie->wins_count; i++) 628 advk_pcie_set_ob_win(pcie, i, 629 pcie->wins[i].match, pcie->wins[i].remap, 630 pcie->wins[i].mask, pcie->wins[i].actions); 631 632 /* Disable remaining PCIe outbound windows */ 633 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) 634 advk_pcie_disable_ob_win(pcie, i); 635 636 advk_pcie_train_link(pcie); 637 } 638 639 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) 640 { 641 struct device *dev = &pcie->pdev->dev; 642 u32 reg; 643 unsigned int status; 644 char *strcomp_status, *str_posted; 645 int ret; 646 647 reg = advk_readl(pcie, PIO_STAT); 648 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 649 PIO_COMPLETION_STATUS_SHIFT; 650 651 /* 652 * According to HW spec, the PIO status check sequence as below: 653 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, 654 * it still needs to check Error Status(bit11), only when this bit 655 * indicates no error happen, the operation is successful. 656 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only 657 * means a PIO write error, and for PIO read it is successful with 658 * a read value of 0xFFFFFFFF. 659 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) 660 * only means a PIO write error, and for PIO read it is successful 661 * with a read value of 0xFFFF0001. 662 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means 663 * error for both PIO read and PIO write operation. 664 * 5) other errors are indicated as 'unknown'. 665 */ 666 switch (status) { 667 case PIO_COMPLETION_STATUS_OK: 668 if (reg & PIO_ERR_STATUS) { 669 strcomp_status = "COMP_ERR"; 670 ret = -EFAULT; 671 break; 672 } 673 /* Get the read result */ 674 if (val) 675 *val = advk_readl(pcie, PIO_RD_DATA); 676 /* No error */ 677 strcomp_status = NULL; 678 ret = 0; 679 break; 680 case PIO_COMPLETION_STATUS_UR: 681 strcomp_status = "UR"; 682 ret = -EOPNOTSUPP; 683 break; 684 case PIO_COMPLETION_STATUS_CRS: 685 if (allow_crs && val) { 686 /* PCIe r4.0, sec 2.3.2, says: 687 * If CRS Software Visibility is enabled: 688 * For a Configuration Read Request that includes both 689 * bytes of the Vendor ID field of a device Function's 690 * Configuration Space Header, the Root Complex must 691 * complete the Request to the host by returning a 692 * read-data value of 0001h for the Vendor ID field and 693 * all '1's for any additional bytes included in the 694 * request. 695 * 696 * So CRS in this case is not an error status. 697 */ 698 *val = CFG_RD_CRS_VAL; 699 strcomp_status = NULL; 700 ret = 0; 701 break; 702 } 703 /* PCIe r4.0, sec 2.3.2, says: 704 * If CRS Software Visibility is not enabled, the Root Complex 705 * must re-issue the Configuration Request as a new Request. 706 * If CRS Software Visibility is enabled: For a Configuration 707 * Write Request or for any other Configuration Read Request, 708 * the Root Complex must re-issue the Configuration Request as 709 * a new Request. 710 * A Root Complex implementation may choose to limit the number 711 * of Configuration Request/CRS Completion Status loops before 712 * determining that something is wrong with the target of the 713 * Request and taking appropriate action, e.g., complete the 714 * Request to the host as a failed transaction. 715 * 716 * So return -EAGAIN and caller (pci-aardvark.c driver) will 717 * re-issue request again up to the PIO_RETRY_CNT retries. 718 */ 719 strcomp_status = "CRS"; 720 ret = -EAGAIN; 721 break; 722 case PIO_COMPLETION_STATUS_CA: 723 strcomp_status = "CA"; 724 ret = -ECANCELED; 725 break; 726 default: 727 strcomp_status = "Unknown"; 728 ret = -EINVAL; 729 break; 730 } 731 732 if (!strcomp_status) 733 return ret; 734 735 if (reg & PIO_NON_POSTED_REQ) 736 str_posted = "Non-posted"; 737 else 738 str_posted = "Posted"; 739 740 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 741 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 742 743 return ret; 744 } 745 746 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 747 { 748 struct device *dev = &pcie->pdev->dev; 749 int i; 750 751 for (i = 1; i <= PIO_RETRY_CNT; i++) { 752 u32 start, isr; 753 754 start = advk_readl(pcie, PIO_START); 755 isr = advk_readl(pcie, PIO_ISR); 756 if (!start && isr) 757 return i; 758 udelay(PIO_RETRY_DELAY); 759 } 760 761 dev_err(dev, "PIO read/write transfer time out\n"); 762 return -ETIMEDOUT; 763 } 764 765 static pci_bridge_emul_read_status_t 766 advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 767 int reg, u32 *value) 768 { 769 struct advk_pcie *pcie = bridge->data; 770 771 switch (reg) { 772 case PCI_COMMAND: 773 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 774 return PCI_BRIDGE_EMUL_HANDLED; 775 776 case PCI_INTERRUPT_LINE: { 777 /* 778 * From the whole 32bit register we support reading from HW only 779 * one bit: PCI_BRIDGE_CTL_BUS_RESET. 780 * Other bits are retrieved only from emulated config buffer. 781 */ 782 __le32 *cfgspace = (__le32 *)&bridge->conf; 783 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); 784 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) 785 val |= PCI_BRIDGE_CTL_BUS_RESET << 16; 786 else 787 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); 788 *value = val; 789 return PCI_BRIDGE_EMUL_HANDLED; 790 } 791 792 default: 793 return PCI_BRIDGE_EMUL_NOT_HANDLED; 794 } 795 } 796 797 static void 798 advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 799 int reg, u32 old, u32 new, u32 mask) 800 { 801 struct advk_pcie *pcie = bridge->data; 802 803 switch (reg) { 804 case PCI_COMMAND: 805 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); 806 break; 807 808 case PCI_INTERRUPT_LINE: 809 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { 810 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); 811 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) 812 val |= HOT_RESET_GEN; 813 else 814 val &= ~HOT_RESET_GEN; 815 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); 816 } 817 break; 818 819 default: 820 break; 821 } 822 } 823 824 static pci_bridge_emul_read_status_t 825 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 826 int reg, u32 *value) 827 { 828 struct advk_pcie *pcie = bridge->data; 829 830 831 switch (reg) { 832 case PCI_EXP_SLTCTL: 833 *value = PCI_EXP_SLTSTA_PDS << 16; 834 return PCI_BRIDGE_EMUL_HANDLED; 835 836 case PCI_EXP_RTCTL: { 837 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 838 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; 839 *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE; 840 *value |= PCI_EXP_RTCAP_CRSVIS << 16; 841 return PCI_BRIDGE_EMUL_HANDLED; 842 } 843 844 case PCI_EXP_RTSTA: { 845 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); 846 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); 847 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16); 848 return PCI_BRIDGE_EMUL_HANDLED; 849 } 850 851 case PCI_EXP_LNKCAP: { 852 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 853 /* 854 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. 855 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm 856 * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag. 857 */ 858 val |= PCI_EXP_LNKCAP_DLLLARC; 859 *value = val; 860 return PCI_BRIDGE_EMUL_HANDLED; 861 } 862 863 case PCI_EXP_LNKCTL: { 864 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 865 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 866 ~(PCI_EXP_LNKSTA_LT << 16); 867 if (advk_pcie_link_training(pcie)) 868 val |= (PCI_EXP_LNKSTA_LT << 16); 869 if (advk_pcie_link_active(pcie)) 870 val |= (PCI_EXP_LNKSTA_DLLLA << 16); 871 *value = val; 872 return PCI_BRIDGE_EMUL_HANDLED; 873 } 874 875 case PCI_CAP_LIST_ID: 876 case PCI_EXP_DEVCAP: 877 case PCI_EXP_DEVCTL: 878 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 879 return PCI_BRIDGE_EMUL_HANDLED; 880 default: 881 return PCI_BRIDGE_EMUL_NOT_HANDLED; 882 } 883 884 } 885 886 static void 887 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 888 int reg, u32 old, u32 new, u32 mask) 889 { 890 struct advk_pcie *pcie = bridge->data; 891 892 switch (reg) { 893 case PCI_EXP_DEVCTL: 894 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 895 break; 896 897 case PCI_EXP_LNKCTL: 898 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 899 if (new & PCI_EXP_LNKCTL_RL) 900 advk_pcie_wait_for_retrain(pcie); 901 break; 902 903 case PCI_EXP_RTCTL: { 904 /* Only mask/unmask PME interrupt */ 905 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & 906 ~PCIE_MSG_PM_PME_MASK; 907 if ((new & PCI_EXP_RTCTL_PMEIE) == 0) 908 val |= PCIE_MSG_PM_PME_MASK; 909 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 910 break; 911 } 912 913 case PCI_EXP_RTSTA: 914 new = (new & PCI_EXP_RTSTA_PME) >> 9; 915 advk_writel(pcie, new, PCIE_ISR0_REG); 916 break; 917 918 default: 919 break; 920 } 921 } 922 923 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 924 .read_base = advk_pci_bridge_emul_base_conf_read, 925 .write_base = advk_pci_bridge_emul_base_conf_write, 926 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 927 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 928 }; 929 930 /* 931 * Initialize the configuration space of the PCI-to-PCI bridge 932 * associated with the given PCIe interface. 933 */ 934 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 935 { 936 struct pci_bridge_emul *bridge = &pcie->bridge; 937 938 bridge->conf.vendor = 939 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 940 bridge->conf.device = 941 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 942 bridge->conf.class_revision = 943 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 944 945 /* Support 32 bits I/O addressing */ 946 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 947 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 948 949 /* Support 64 bits memory pref */ 950 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 951 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 952 953 /* Support interrupt A for MSI feature */ 954 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; 955 956 /* Indicates supports for Completion Retry Status */ 957 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); 958 959 bridge->has_pcie = true; 960 bridge->data = pcie; 961 bridge->ops = &advk_pci_bridge_emul_ops; 962 963 return pci_bridge_emul_init(bridge, 0); 964 } 965 966 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 967 int devfn) 968 { 969 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) 970 return false; 971 972 /* 973 * If the link goes down after we check for link-up, nothing bad 974 * happens but the config access times out. 975 */ 976 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) 977 return false; 978 979 return true; 980 } 981 982 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) 983 { 984 struct device *dev = &pcie->pdev->dev; 985 986 /* 987 * Trying to start a new PIO transfer when previous has not completed 988 * cause External Abort on CPU which results in kernel panic: 989 * 990 * SError Interrupt on CPU0, code 0xbf000002 -- SError 991 * Kernel panic - not syncing: Asynchronous SError Interrupt 992 * 993 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected 994 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent 995 * concurrent calls at the same time. But because PIO transfer may take 996 * about 1.5s when link is down or card is disconnected, it means that 997 * advk_pcie_wait_pio() does not always have to wait for completion. 998 * 999 * Some versions of ARM Trusted Firmware handles this External Abort at 1000 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: 1001 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 1002 */ 1003 if (advk_readl(pcie, PIO_START)) { 1004 dev_err(dev, "Previous PIO read/write transfer is still running\n"); 1005 return true; 1006 } 1007 1008 return false; 1009 } 1010 1011 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 1012 int where, int size, u32 *val) 1013 { 1014 struct advk_pcie *pcie = bus->sysdata; 1015 int retry_count; 1016 bool allow_crs; 1017 u32 reg; 1018 int ret; 1019 1020 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 1021 *val = 0xffffffff; 1022 return PCIBIOS_DEVICE_NOT_FOUND; 1023 } 1024 1025 if (pci_is_root_bus(bus)) 1026 return pci_bridge_emul_conf_read(&pcie->bridge, where, 1027 size, val); 1028 1029 /* 1030 * Completion Retry Status is possible to return only when reading all 1031 * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and 1032 * CRSSVE flag on Root Bridge is enabled. 1033 */ 1034 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && 1035 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & 1036 PCI_EXP_RTCTL_CRSSVE); 1037 1038 if (advk_pcie_pio_is_running(pcie)) 1039 goto try_crs; 1040 1041 /* Program the control register */ 1042 reg = advk_readl(pcie, PIO_CTRL); 1043 reg &= ~PIO_CTRL_TYPE_MASK; 1044 if (pci_is_root_bus(bus->parent)) 1045 reg |= PCIE_CONFIG_RD_TYPE0; 1046 else 1047 reg |= PCIE_CONFIG_RD_TYPE1; 1048 advk_writel(pcie, reg, PIO_CTRL); 1049 1050 /* Program the address registers */ 1051 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1052 advk_writel(pcie, reg, PIO_ADDR_LS); 1053 advk_writel(pcie, 0, PIO_ADDR_MS); 1054 1055 /* Program the data strobe */ 1056 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 1057 1058 retry_count = 0; 1059 do { 1060 /* Clear PIO DONE ISR and start the transfer */ 1061 advk_writel(pcie, 1, PIO_ISR); 1062 advk_writel(pcie, 1, PIO_START); 1063 1064 ret = advk_pcie_wait_pio(pcie); 1065 if (ret < 0) 1066 goto try_crs; 1067 1068 retry_count += ret; 1069 1070 /* Check PIO status and get the read result */ 1071 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); 1072 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1073 1074 if (ret < 0) 1075 goto fail; 1076 1077 if (size == 1) 1078 *val = (*val >> (8 * (where & 3))) & 0xff; 1079 else if (size == 2) 1080 *val = (*val >> (8 * (where & 3))) & 0xffff; 1081 1082 return PCIBIOS_SUCCESSFUL; 1083 1084 try_crs: 1085 /* 1086 * If it is possible, return Completion Retry Status so that caller 1087 * tries to issue the request again instead of failing. 1088 */ 1089 if (allow_crs) { 1090 *val = CFG_RD_CRS_VAL; 1091 return PCIBIOS_SUCCESSFUL; 1092 } 1093 1094 fail: 1095 *val = 0xffffffff; 1096 return PCIBIOS_SET_FAILED; 1097 } 1098 1099 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 1100 int where, int size, u32 val) 1101 { 1102 struct advk_pcie *pcie = bus->sysdata; 1103 u32 reg; 1104 u32 data_strobe = 0x0; 1105 int retry_count; 1106 int offset; 1107 int ret; 1108 1109 if (!advk_pcie_valid_device(pcie, bus, devfn)) 1110 return PCIBIOS_DEVICE_NOT_FOUND; 1111 1112 if (pci_is_root_bus(bus)) 1113 return pci_bridge_emul_conf_write(&pcie->bridge, where, 1114 size, val); 1115 1116 if (where % size) 1117 return PCIBIOS_SET_FAILED; 1118 1119 if (advk_pcie_pio_is_running(pcie)) 1120 return PCIBIOS_SET_FAILED; 1121 1122 /* Program the control register */ 1123 reg = advk_readl(pcie, PIO_CTRL); 1124 reg &= ~PIO_CTRL_TYPE_MASK; 1125 if (pci_is_root_bus(bus->parent)) 1126 reg |= PCIE_CONFIG_WR_TYPE0; 1127 else 1128 reg |= PCIE_CONFIG_WR_TYPE1; 1129 advk_writel(pcie, reg, PIO_CTRL); 1130 1131 /* Program the address registers */ 1132 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1133 advk_writel(pcie, reg, PIO_ADDR_LS); 1134 advk_writel(pcie, 0, PIO_ADDR_MS); 1135 1136 /* Calculate the write strobe */ 1137 offset = where & 0x3; 1138 reg = val << (8 * offset); 1139 data_strobe = GENMASK(size - 1, 0) << offset; 1140 1141 /* Program the data register */ 1142 advk_writel(pcie, reg, PIO_WR_DATA); 1143 1144 /* Program the data strobe */ 1145 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 1146 1147 retry_count = 0; 1148 do { 1149 /* Clear PIO DONE ISR and start the transfer */ 1150 advk_writel(pcie, 1, PIO_ISR); 1151 advk_writel(pcie, 1, PIO_START); 1152 1153 ret = advk_pcie_wait_pio(pcie); 1154 if (ret < 0) 1155 return PCIBIOS_SET_FAILED; 1156 1157 retry_count += ret; 1158 1159 ret = advk_pcie_check_pio_status(pcie, false, NULL); 1160 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1161 1162 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; 1163 } 1164 1165 static struct pci_ops advk_pcie_ops = { 1166 .read = advk_pcie_rd_conf, 1167 .write = advk_pcie_wr_conf, 1168 }; 1169 1170 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 1171 struct msi_msg *msg) 1172 { 1173 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 1174 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 1175 1176 msg->address_lo = lower_32_bits(msi_msg); 1177 msg->address_hi = upper_32_bits(msi_msg); 1178 msg->data = data->irq; 1179 } 1180 1181 static int advk_msi_set_affinity(struct irq_data *irq_data, 1182 const struct cpumask *mask, bool force) 1183 { 1184 return -EINVAL; 1185 } 1186 1187 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 1188 unsigned int virq, 1189 unsigned int nr_irqs, void *args) 1190 { 1191 struct advk_pcie *pcie = domain->host_data; 1192 int hwirq, i; 1193 1194 mutex_lock(&pcie->msi_used_lock); 1195 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 1196 0, nr_irqs, 0); 1197 if (hwirq >= MSI_IRQ_NUM) { 1198 mutex_unlock(&pcie->msi_used_lock); 1199 return -ENOSPC; 1200 } 1201 1202 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 1203 mutex_unlock(&pcie->msi_used_lock); 1204 1205 for (i = 0; i < nr_irqs; i++) 1206 irq_domain_set_info(domain, virq + i, hwirq + i, 1207 &pcie->msi_bottom_irq_chip, 1208 domain->host_data, handle_simple_irq, 1209 NULL, NULL); 1210 1211 return 0; 1212 } 1213 1214 static void advk_msi_irq_domain_free(struct irq_domain *domain, 1215 unsigned int virq, unsigned int nr_irqs) 1216 { 1217 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1218 struct advk_pcie *pcie = domain->host_data; 1219 1220 mutex_lock(&pcie->msi_used_lock); 1221 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 1222 mutex_unlock(&pcie->msi_used_lock); 1223 } 1224 1225 static const struct irq_domain_ops advk_msi_domain_ops = { 1226 .alloc = advk_msi_irq_domain_alloc, 1227 .free = advk_msi_irq_domain_free, 1228 }; 1229 1230 static void advk_pcie_irq_mask(struct irq_data *d) 1231 { 1232 struct advk_pcie *pcie = d->domain->host_data; 1233 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1234 unsigned long flags; 1235 u32 mask; 1236 1237 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1238 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1239 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 1240 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1241 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1242 } 1243 1244 static void advk_pcie_irq_unmask(struct irq_data *d) 1245 { 1246 struct advk_pcie *pcie = d->domain->host_data; 1247 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1248 unsigned long flags; 1249 u32 mask; 1250 1251 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1252 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1253 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 1254 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1255 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1256 } 1257 1258 static int advk_pcie_irq_map(struct irq_domain *h, 1259 unsigned int virq, irq_hw_number_t hwirq) 1260 { 1261 struct advk_pcie *pcie = h->host_data; 1262 1263 advk_pcie_irq_mask(irq_get_irq_data(virq)); 1264 irq_set_status_flags(virq, IRQ_LEVEL); 1265 irq_set_chip_and_handler(virq, &pcie->irq_chip, 1266 handle_level_irq); 1267 irq_set_chip_data(virq, pcie); 1268 1269 return 0; 1270 } 1271 1272 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 1273 .map = advk_pcie_irq_map, 1274 .xlate = irq_domain_xlate_onecell, 1275 }; 1276 1277 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 1278 { 1279 struct device *dev = &pcie->pdev->dev; 1280 struct device_node *node = dev->of_node; 1281 struct irq_chip *bottom_ic, *msi_ic; 1282 struct msi_domain_info *msi_di; 1283 phys_addr_t msi_msg_phys; 1284 1285 mutex_init(&pcie->msi_used_lock); 1286 1287 bottom_ic = &pcie->msi_bottom_irq_chip; 1288 1289 bottom_ic->name = "MSI"; 1290 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 1291 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 1292 1293 msi_ic = &pcie->msi_irq_chip; 1294 msi_ic->name = "advk-MSI"; 1295 1296 msi_di = &pcie->msi_domain_info; 1297 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1298 MSI_FLAG_MULTI_PCI_MSI; 1299 msi_di->chip = msi_ic; 1300 1301 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 1302 1303 advk_writel(pcie, lower_32_bits(msi_msg_phys), 1304 PCIE_MSI_ADDR_LOW_REG); 1305 advk_writel(pcie, upper_32_bits(msi_msg_phys), 1306 PCIE_MSI_ADDR_HIGH_REG); 1307 1308 pcie->msi_inner_domain = 1309 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 1310 &advk_msi_domain_ops, pcie); 1311 if (!pcie->msi_inner_domain) 1312 return -ENOMEM; 1313 1314 pcie->msi_domain = 1315 pci_msi_create_irq_domain(of_node_to_fwnode(node), 1316 msi_di, pcie->msi_inner_domain); 1317 if (!pcie->msi_domain) { 1318 irq_domain_remove(pcie->msi_inner_domain); 1319 return -ENOMEM; 1320 } 1321 1322 return 0; 1323 } 1324 1325 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 1326 { 1327 irq_domain_remove(pcie->msi_domain); 1328 irq_domain_remove(pcie->msi_inner_domain); 1329 } 1330 1331 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 1332 { 1333 struct device *dev = &pcie->pdev->dev; 1334 struct device_node *node = dev->of_node; 1335 struct device_node *pcie_intc_node; 1336 struct irq_chip *irq_chip; 1337 int ret = 0; 1338 1339 raw_spin_lock_init(&pcie->irq_lock); 1340 1341 pcie_intc_node = of_get_next_child(node, NULL); 1342 if (!pcie_intc_node) { 1343 dev_err(dev, "No PCIe Intc node found\n"); 1344 return -ENODEV; 1345 } 1346 1347 irq_chip = &pcie->irq_chip; 1348 1349 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 1350 dev_name(dev)); 1351 if (!irq_chip->name) { 1352 ret = -ENOMEM; 1353 goto out_put_node; 1354 } 1355 1356 irq_chip->irq_mask = advk_pcie_irq_mask; 1357 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 1358 irq_chip->irq_unmask = advk_pcie_irq_unmask; 1359 1360 pcie->irq_domain = 1361 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 1362 &advk_pcie_irq_domain_ops, pcie); 1363 if (!pcie->irq_domain) { 1364 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 1365 ret = -ENOMEM; 1366 goto out_put_node; 1367 } 1368 1369 out_put_node: 1370 of_node_put(pcie_intc_node); 1371 return ret; 1372 } 1373 1374 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 1375 { 1376 irq_domain_remove(pcie->irq_domain); 1377 } 1378 1379 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 1380 { 1381 u32 msi_val, msi_mask, msi_status, msi_idx; 1382 u16 msi_data; 1383 1384 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1385 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 1386 msi_status = msi_val & ~msi_mask; 1387 1388 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 1389 if (!(BIT(msi_idx) & msi_status)) 1390 continue; 1391 1392 /* 1393 * msi_idx contains bits [4:0] of the msi_data and msi_data 1394 * contains 16bit MSI interrupt number 1395 */ 1396 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 1397 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; 1398 generic_handle_irq(msi_data); 1399 } 1400 1401 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 1402 PCIE_ISR0_REG); 1403 } 1404 1405 static void advk_pcie_handle_int(struct advk_pcie *pcie) 1406 { 1407 u32 isr0_val, isr0_mask, isr0_status; 1408 u32 isr1_val, isr1_mask, isr1_status; 1409 int i; 1410 1411 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 1412 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 1413 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 1414 1415 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 1416 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1417 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 1418 1419 /* Process MSI interrupts */ 1420 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 1421 advk_pcie_handle_msi(pcie); 1422 1423 /* Process legacy interrupts */ 1424 for (i = 0; i < PCI_NUM_INTX; i++) { 1425 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 1426 continue; 1427 1428 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 1429 PCIE_ISR1_REG); 1430 1431 generic_handle_domain_irq(pcie->irq_domain, i); 1432 } 1433 } 1434 1435 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 1436 { 1437 struct advk_pcie *pcie = arg; 1438 u32 status; 1439 1440 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 1441 if (!(status & PCIE_IRQ_CORE_INT)) 1442 return IRQ_NONE; 1443 1444 advk_pcie_handle_int(pcie); 1445 1446 /* Clear interrupt */ 1447 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 1448 1449 return IRQ_HANDLED; 1450 } 1451 1452 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) 1453 { 1454 phy_power_off(pcie->phy); 1455 phy_exit(pcie->phy); 1456 } 1457 1458 static int advk_pcie_enable_phy(struct advk_pcie *pcie) 1459 { 1460 int ret; 1461 1462 if (!pcie->phy) 1463 return 0; 1464 1465 ret = phy_init(pcie->phy); 1466 if (ret) 1467 return ret; 1468 1469 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); 1470 if (ret) { 1471 phy_exit(pcie->phy); 1472 return ret; 1473 } 1474 1475 ret = phy_power_on(pcie->phy); 1476 if (ret == -EOPNOTSUPP) { 1477 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); 1478 } else if (ret) { 1479 phy_exit(pcie->phy); 1480 return ret; 1481 } 1482 1483 return 0; 1484 } 1485 1486 static int advk_pcie_setup_phy(struct advk_pcie *pcie) 1487 { 1488 struct device *dev = &pcie->pdev->dev; 1489 struct device_node *node = dev->of_node; 1490 int ret = 0; 1491 1492 pcie->phy = devm_of_phy_get(dev, node, NULL); 1493 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) 1494 return PTR_ERR(pcie->phy); 1495 1496 /* Old bindings miss the PHY handle */ 1497 if (IS_ERR(pcie->phy)) { 1498 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); 1499 pcie->phy = NULL; 1500 return 0; 1501 } 1502 1503 ret = advk_pcie_enable_phy(pcie); 1504 if (ret) 1505 dev_err(dev, "Failed to initialize PHY (%d)\n", ret); 1506 1507 return ret; 1508 } 1509 1510 static int advk_pcie_probe(struct platform_device *pdev) 1511 { 1512 struct device *dev = &pdev->dev; 1513 struct advk_pcie *pcie; 1514 struct pci_host_bridge *bridge; 1515 struct resource_entry *entry; 1516 int ret, irq; 1517 1518 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 1519 if (!bridge) 1520 return -ENOMEM; 1521 1522 pcie = pci_host_bridge_priv(bridge); 1523 pcie->pdev = pdev; 1524 platform_set_drvdata(pdev, pcie); 1525 1526 resource_list_for_each_entry(entry, &bridge->windows) { 1527 resource_size_t start = entry->res->start; 1528 resource_size_t size = resource_size(entry->res); 1529 unsigned long type = resource_type(entry->res); 1530 u64 win_size; 1531 1532 /* 1533 * Aardvark hardware allows to configure also PCIe window 1534 * for config type 0 and type 1 mapping, but driver uses 1535 * only PIO for issuing configuration transfers which does 1536 * not use PCIe window configuration. 1537 */ 1538 if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 && 1539 type != IORESOURCE_IO) 1540 continue; 1541 1542 /* 1543 * Skip transparent memory resources. Default outbound access 1544 * configuration is set to transparent memory access so it 1545 * does not need window configuration. 1546 */ 1547 if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) && 1548 entry->offset == 0) 1549 continue; 1550 1551 /* 1552 * The n-th PCIe window is configured by tuple (match, remap, mask) 1553 * and an access to address A uses this window if A matches the 1554 * match with given mask. 1555 * So every PCIe window size must be a power of two and every start 1556 * address must be aligned to window size. Minimal size is 64 KiB 1557 * because lower 16 bits of mask must be zero. Remapped address 1558 * may have set only bits from the mask. 1559 */ 1560 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { 1561 /* Calculate the largest aligned window size */ 1562 win_size = (1ULL << (fls64(size)-1)) | 1563 (start ? (1ULL << __ffs64(start)) : 0); 1564 win_size = 1ULL << __ffs64(win_size); 1565 if (win_size < 0x10000) 1566 break; 1567 1568 dev_dbg(dev, 1569 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", 1570 pcie->wins_count, (unsigned long long)start, 1571 (unsigned long long)start + win_size, type); 1572 1573 if (type == IORESOURCE_IO) { 1574 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; 1575 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); 1576 } else { 1577 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; 1578 pcie->wins[pcie->wins_count].match = start; 1579 } 1580 pcie->wins[pcie->wins_count].remap = start - entry->offset; 1581 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); 1582 1583 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) 1584 break; 1585 1586 start += win_size; 1587 size -= win_size; 1588 pcie->wins_count++; 1589 } 1590 1591 if (size > 0) { 1592 dev_err(&pcie->pdev->dev, 1593 "Invalid PCIe region [0x%llx-0x%llx]\n", 1594 (unsigned long long)entry->res->start, 1595 (unsigned long long)entry->res->end + 1); 1596 return -EINVAL; 1597 } 1598 } 1599 1600 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1601 if (IS_ERR(pcie->base)) 1602 return PTR_ERR(pcie->base); 1603 1604 irq = platform_get_irq(pdev, 0); 1605 if (irq < 0) 1606 return irq; 1607 1608 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 1609 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 1610 pcie); 1611 if (ret) { 1612 dev_err(dev, "Failed to register interrupt\n"); 1613 return ret; 1614 } 1615 1616 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, 1617 "reset-gpios", 0, 1618 GPIOD_OUT_LOW, 1619 "pcie1-reset"); 1620 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); 1621 if (ret) { 1622 if (ret == -ENOENT) { 1623 pcie->reset_gpio = NULL; 1624 } else { 1625 if (ret != -EPROBE_DEFER) 1626 dev_err(dev, "Failed to get reset-gpio: %i\n", 1627 ret); 1628 return ret; 1629 } 1630 } 1631 1632 ret = of_pci_get_max_link_speed(dev->of_node); 1633 if (ret <= 0 || ret > 3) 1634 pcie->link_gen = 3; 1635 else 1636 pcie->link_gen = ret; 1637 1638 ret = advk_pcie_setup_phy(pcie); 1639 if (ret) 1640 return ret; 1641 1642 advk_pcie_setup_hw(pcie); 1643 1644 ret = advk_sw_pci_bridge_init(pcie); 1645 if (ret) { 1646 dev_err(dev, "Failed to register emulated root PCI bridge\n"); 1647 return ret; 1648 } 1649 1650 ret = advk_pcie_init_irq_domain(pcie); 1651 if (ret) { 1652 dev_err(dev, "Failed to initialize irq\n"); 1653 return ret; 1654 } 1655 1656 ret = advk_pcie_init_msi_irq_domain(pcie); 1657 if (ret) { 1658 dev_err(dev, "Failed to initialize irq\n"); 1659 advk_pcie_remove_irq_domain(pcie); 1660 return ret; 1661 } 1662 1663 bridge->sysdata = pcie; 1664 bridge->ops = &advk_pcie_ops; 1665 1666 ret = pci_host_probe(bridge); 1667 if (ret < 0) { 1668 advk_pcie_remove_msi_irq_domain(pcie); 1669 advk_pcie_remove_irq_domain(pcie); 1670 return ret; 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int advk_pcie_remove(struct platform_device *pdev) 1677 { 1678 struct advk_pcie *pcie = platform_get_drvdata(pdev); 1679 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1680 int i; 1681 1682 pci_lock_rescan_remove(); 1683 pci_stop_root_bus(bridge->bus); 1684 pci_remove_root_bus(bridge->bus); 1685 pci_unlock_rescan_remove(); 1686 1687 advk_pcie_remove_msi_irq_domain(pcie); 1688 advk_pcie_remove_irq_domain(pcie); 1689 1690 /* Disable outbound address windows mapping */ 1691 for (i = 0; i < OB_WIN_COUNT; i++) 1692 advk_pcie_disable_ob_win(pcie, i); 1693 1694 return 0; 1695 } 1696 1697 static const struct of_device_id advk_pcie_of_match_table[] = { 1698 { .compatible = "marvell,armada-3700-pcie", }, 1699 {}, 1700 }; 1701 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table); 1702 1703 static struct platform_driver advk_pcie_driver = { 1704 .driver = { 1705 .name = "advk-pcie", 1706 .of_match_table = advk_pcie_of_match_table, 1707 }, 1708 .probe = advk_pcie_probe, 1709 .remove = advk_pcie_remove, 1710 }; 1711 module_platform_driver(advk_pcie_driver); 1712 1713 MODULE_DESCRIPTION("Aardvark PCIe controller"); 1714 MODULE_LICENSE("GPL v2"); 1715