1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 22 #include "../pci.h" 23 24 /* PCIe core registers */ 25 #define PCIE_CORE_CMD_STATUS_REG 0x4 26 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 27 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 28 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 29 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 30 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) 31 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 32 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) 33 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 35 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 36 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) 37 #define PCIE_CORE_LINK_TRAINING BIT(5) 38 #define PCIE_CORE_LINK_WIDTH_SHIFT 20 39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 44 45 /* PIO registers base address and register offsets */ 46 #define PIO_BASE_ADDR 0x4000 47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 50 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 51 #define PIO_COMPLETION_STATUS_SHIFT 7 52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 53 #define PIO_COMPLETION_STATUS_OK 0 54 #define PIO_COMPLETION_STATUS_UR 1 55 #define PIO_COMPLETION_STATUS_CRS 2 56 #define PIO_COMPLETION_STATUS_CA 4 57 #define PIO_NON_POSTED_REQ BIT(0) 58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 63 #define PIO_START (PIO_BASE_ADDR + 0x1c) 64 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 66 67 /* Aardvark Control registers */ 68 #define CONTROL_BASE_ADDR 0x4800 69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 70 #define PCIE_GEN_SEL_MSK 0x3 71 #define PCIE_GEN_SEL_SHIFT 0x0 72 #define SPEED_GEN_1 0 73 #define SPEED_GEN_2 1 74 #define SPEED_GEN_3 2 75 #define IS_RC_MSK 1 76 #define IS_RC_SHIFT 2 77 #define LANE_CNT_MSK 0x18 78 #define LANE_CNT_SHIFT 0x3 79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 83 #define LINK_TRAINING_EN BIT(6) 84 #define LEGACY_INTA BIT(28) 85 #define LEGACY_INTB BIT(29) 86 #define LEGACY_INTC BIT(30) 87 #define LEGACY_INTD BIT(31) 88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 89 #define HOT_RESET_GEN BIT(0) 90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 91 #define PCIE_CORE_CTRL2_RESERVED 0x7 92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 96 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 97 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 98 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 99 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 100 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 101 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 102 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 103 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 104 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 105 #define PCIE_ISR1_FLUSH BIT(5) 106 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 107 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 108 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 109 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 110 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 111 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 112 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 113 114 /* PCIe window configuration */ 115 #define OB_WIN_BASE_ADDR 0x4c00 116 #define OB_WIN_BLOCK_SIZE 0x20 117 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ 118 OB_WIN_BLOCK_SIZE * (win) + \ 119 (offset)) 120 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) 121 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) 122 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) 123 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) 124 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) 125 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) 126 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) 127 128 /* PCIe window types */ 129 #define OB_PCIE_MEM 0x0 130 #define OB_PCIE_IO 0x4 131 132 /* LMI registers base address and register offsets */ 133 #define LMI_BASE_ADDR 0x6000 134 #define CFG_REG (LMI_BASE_ADDR + 0x0) 135 #define LTSSM_SHIFT 24 136 #define LTSSM_MASK 0x3f 137 #define LTSSM_L0 0x10 138 #define RC_BAR_CONFIG 0x300 139 140 /* PCIe core controller registers */ 141 #define CTRL_CORE_BASE_ADDR 0x18000 142 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 143 #define CTRL_MODE_SHIFT 0x0 144 #define CTRL_MODE_MASK 0x1 145 #define PCIE_CORE_MODE_DIRECT 0x0 146 #define PCIE_CORE_MODE_COMMAND 0x1 147 148 /* PCIe Central Interrupts Registers */ 149 #define CENTRAL_INT_BASE_ADDR 0x1b000 150 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 151 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 152 #define PCIE_IRQ_CMDQ_INT BIT(0) 153 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 154 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 155 #define PCIE_IRQ_DMA_INT BIT(4) 156 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 157 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 158 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 159 #define PCIE_IRQ_COMPQ_INT BIT(12) 160 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 161 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 162 #define PCIE_IRQ_CORE_INT BIT(16) 163 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 164 #define PCIE_IRQ_DPMU_INT BIT(18) 165 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 166 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 167 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 168 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 169 #define PCIE_IRQ_EP_STATUS BIT(23) 170 #define PCIE_IRQ_ALL_MASK 0xfff0fb 171 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 172 173 /* Transaction types */ 174 #define PCIE_CONFIG_RD_TYPE0 0x8 175 #define PCIE_CONFIG_RD_TYPE1 0x9 176 #define PCIE_CONFIG_WR_TYPE0 0xa 177 #define PCIE_CONFIG_WR_TYPE1 0xb 178 179 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 180 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 181 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 182 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 183 #define PCIE_CONF_ADDR(bus, devfn, where) \ 184 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 185 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 186 187 #define PIO_TIMEOUT_MS 1 188 189 #define LINK_WAIT_MAX_RETRIES 10 190 #define LINK_WAIT_USLEEP_MIN 90000 191 #define LINK_WAIT_USLEEP_MAX 100000 192 193 #define MSI_IRQ_NUM 32 194 195 struct advk_pcie { 196 struct platform_device *pdev; 197 void __iomem *base; 198 struct list_head resources; 199 struct irq_domain *irq_domain; 200 struct irq_chip irq_chip; 201 struct irq_domain *msi_domain; 202 struct irq_domain *msi_inner_domain; 203 struct irq_chip msi_bottom_irq_chip; 204 struct irq_chip msi_irq_chip; 205 struct msi_domain_info msi_domain_info; 206 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 207 struct mutex msi_used_lock; 208 u16 msi_msg; 209 int root_bus_nr; 210 }; 211 212 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 213 { 214 writel(val, pcie->base + reg); 215 } 216 217 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 218 { 219 return readl(pcie->base + reg); 220 } 221 222 static int advk_pcie_link_up(struct advk_pcie *pcie) 223 { 224 u32 val, ltssm_state; 225 226 val = advk_readl(pcie, CFG_REG); 227 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 228 return ltssm_state >= LTSSM_L0; 229 } 230 231 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 232 { 233 struct device *dev = &pcie->pdev->dev; 234 int retries; 235 236 /* check if the link is up or not */ 237 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 238 if (advk_pcie_link_up(pcie)) { 239 dev_info(dev, "link up\n"); 240 return 0; 241 } 242 243 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 244 } 245 246 dev_err(dev, "link never came up\n"); 247 return -ETIMEDOUT; 248 } 249 250 /* 251 * Set PCIe address window register which could be used for memory 252 * mapping. 253 */ 254 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, 255 u32 win_num, u32 match_ms, 256 u32 match_ls, u32 mask_ms, 257 u32 mask_ls, u32 remap_ms, 258 u32 remap_ls, u32 action) 259 { 260 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num)); 261 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num)); 262 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num)); 263 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num)); 264 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num)); 265 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num)); 266 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num)); 267 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num)); 268 } 269 270 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 271 { 272 u32 reg; 273 int i; 274 275 /* Point PCIe unit MBUS decode windows to DRAM space */ 276 for (i = 0; i < 8; i++) 277 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0); 278 279 /* Set to Direct mode */ 280 reg = advk_readl(pcie, CTRL_CONFIG_REG); 281 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 282 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 283 advk_writel(pcie, reg, CTRL_CONFIG_REG); 284 285 /* Set PCI global control register to RC mode */ 286 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 287 reg |= (IS_RC_MSK << IS_RC_SHIFT); 288 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 289 290 /* Set Advanced Error Capabilities and Control PF0 register */ 291 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 292 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 293 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 294 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 295 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 296 297 /* Set PCIe Device Control and Status 1 PF0 register */ 298 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | 299 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | 300 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | 301 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << 302 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); 303 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); 304 305 /* Program PCIe Control 2 to disable strict ordering */ 306 reg = PCIE_CORE_CTRL2_RESERVED | 307 PCIE_CORE_CTRL2_TD_ENABLE; 308 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 309 310 /* Set GEN2 */ 311 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 312 reg &= ~PCIE_GEN_SEL_MSK; 313 reg |= SPEED_GEN_2; 314 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 315 316 /* Set lane X1 */ 317 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 318 reg &= ~LANE_CNT_MSK; 319 reg |= LANE_COUNT_1; 320 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 321 322 /* Enable link training */ 323 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 324 reg |= LINK_TRAINING_EN; 325 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 326 327 /* Enable MSI */ 328 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 329 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 330 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 331 332 /* Clear all interrupts */ 333 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 334 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 335 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 336 337 /* Disable All ISR0/1 Sources */ 338 reg = PCIE_ISR0_ALL_MASK; 339 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 340 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 341 342 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 343 344 /* Unmask all MSI's */ 345 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 346 347 /* Enable summary interrupt for GIC SPI source */ 348 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 349 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 350 351 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 352 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 353 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 354 355 /* Bypass the address window mapping for PIO */ 356 reg = advk_readl(pcie, PIO_CTRL); 357 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 358 advk_writel(pcie, reg, PIO_CTRL); 359 360 /* Start link training */ 361 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); 362 reg |= PCIE_CORE_LINK_TRAINING; 363 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 364 365 advk_pcie_wait_for_link(pcie); 366 367 reg = PCIE_CORE_LINK_L0S_ENTRY | 368 (1 << PCIE_CORE_LINK_WIDTH_SHIFT); 369 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 370 371 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 372 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 373 PCIE_CORE_CMD_IO_ACCESS_EN | 374 PCIE_CORE_CMD_MEM_IO_REQ_EN; 375 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 376 } 377 378 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 379 { 380 struct device *dev = &pcie->pdev->dev; 381 u32 reg; 382 unsigned int status; 383 char *strcomp_status, *str_posted; 384 385 reg = advk_readl(pcie, PIO_STAT); 386 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 387 PIO_COMPLETION_STATUS_SHIFT; 388 389 if (!status) 390 return; 391 392 switch (status) { 393 case PIO_COMPLETION_STATUS_UR: 394 strcomp_status = "UR"; 395 break; 396 case PIO_COMPLETION_STATUS_CRS: 397 strcomp_status = "CRS"; 398 break; 399 case PIO_COMPLETION_STATUS_CA: 400 strcomp_status = "CA"; 401 break; 402 default: 403 strcomp_status = "Unknown"; 404 break; 405 } 406 407 if (reg & PIO_NON_POSTED_REQ) 408 str_posted = "Non-posted"; 409 else 410 str_posted = "Posted"; 411 412 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 413 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 414 } 415 416 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 417 { 418 struct device *dev = &pcie->pdev->dev; 419 unsigned long timeout; 420 421 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS); 422 423 while (time_before(jiffies, timeout)) { 424 u32 start, isr; 425 426 start = advk_readl(pcie, PIO_START); 427 isr = advk_readl(pcie, PIO_ISR); 428 if (!start && isr) 429 return 0; 430 } 431 432 dev_err(dev, "config read/write timed out\n"); 433 return -ETIMEDOUT; 434 } 435 436 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 437 int where, int size, u32 *val) 438 { 439 struct advk_pcie *pcie = bus->sysdata; 440 u32 reg; 441 int ret; 442 443 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) { 444 *val = 0xffffffff; 445 return PCIBIOS_DEVICE_NOT_FOUND; 446 } 447 448 /* Start PIO */ 449 advk_writel(pcie, 0, PIO_START); 450 advk_writel(pcie, 1, PIO_ISR); 451 452 /* Program the control register */ 453 reg = advk_readl(pcie, PIO_CTRL); 454 reg &= ~PIO_CTRL_TYPE_MASK; 455 if (bus->number == pcie->root_bus_nr) 456 reg |= PCIE_CONFIG_RD_TYPE0; 457 else 458 reg |= PCIE_CONFIG_RD_TYPE1; 459 advk_writel(pcie, reg, PIO_CTRL); 460 461 /* Program the address registers */ 462 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 463 advk_writel(pcie, reg, PIO_ADDR_LS); 464 advk_writel(pcie, 0, PIO_ADDR_MS); 465 466 /* Program the data strobe */ 467 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 468 469 /* Start the transfer */ 470 advk_writel(pcie, 1, PIO_START); 471 472 ret = advk_pcie_wait_pio(pcie); 473 if (ret < 0) 474 return PCIBIOS_SET_FAILED; 475 476 advk_pcie_check_pio_status(pcie); 477 478 /* Get the read result */ 479 *val = advk_readl(pcie, PIO_RD_DATA); 480 if (size == 1) 481 *val = (*val >> (8 * (where & 3))) & 0xff; 482 else if (size == 2) 483 *val = (*val >> (8 * (where & 3))) & 0xffff; 484 485 return PCIBIOS_SUCCESSFUL; 486 } 487 488 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 489 int where, int size, u32 val) 490 { 491 struct advk_pcie *pcie = bus->sysdata; 492 u32 reg; 493 u32 data_strobe = 0x0; 494 int offset; 495 int ret; 496 497 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 498 return PCIBIOS_DEVICE_NOT_FOUND; 499 500 if (where % size) 501 return PCIBIOS_SET_FAILED; 502 503 /* Start PIO */ 504 advk_writel(pcie, 0, PIO_START); 505 advk_writel(pcie, 1, PIO_ISR); 506 507 /* Program the control register */ 508 reg = advk_readl(pcie, PIO_CTRL); 509 reg &= ~PIO_CTRL_TYPE_MASK; 510 if (bus->number == pcie->root_bus_nr) 511 reg |= PCIE_CONFIG_WR_TYPE0; 512 else 513 reg |= PCIE_CONFIG_WR_TYPE1; 514 advk_writel(pcie, reg, PIO_CTRL); 515 516 /* Program the address registers */ 517 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 518 advk_writel(pcie, reg, PIO_ADDR_LS); 519 advk_writel(pcie, 0, PIO_ADDR_MS); 520 521 /* Calculate the write strobe */ 522 offset = where & 0x3; 523 reg = val << (8 * offset); 524 data_strobe = GENMASK(size - 1, 0) << offset; 525 526 /* Program the data register */ 527 advk_writel(pcie, reg, PIO_WR_DATA); 528 529 /* Program the data strobe */ 530 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 531 532 /* Start the transfer */ 533 advk_writel(pcie, 1, PIO_START); 534 535 ret = advk_pcie_wait_pio(pcie); 536 if (ret < 0) 537 return PCIBIOS_SET_FAILED; 538 539 advk_pcie_check_pio_status(pcie); 540 541 return PCIBIOS_SUCCESSFUL; 542 } 543 544 static struct pci_ops advk_pcie_ops = { 545 .read = advk_pcie_rd_conf, 546 .write = advk_pcie_wr_conf, 547 }; 548 549 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 550 struct msi_msg *msg) 551 { 552 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 553 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 554 555 msg->address_lo = lower_32_bits(msi_msg); 556 msg->address_hi = upper_32_bits(msi_msg); 557 msg->data = data->irq; 558 } 559 560 static int advk_msi_set_affinity(struct irq_data *irq_data, 561 const struct cpumask *mask, bool force) 562 { 563 return -EINVAL; 564 } 565 566 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 567 unsigned int virq, 568 unsigned int nr_irqs, void *args) 569 { 570 struct advk_pcie *pcie = domain->host_data; 571 int hwirq, i; 572 573 mutex_lock(&pcie->msi_used_lock); 574 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 575 0, nr_irqs, 0); 576 if (hwirq >= MSI_IRQ_NUM) { 577 mutex_unlock(&pcie->msi_used_lock); 578 return -ENOSPC; 579 } 580 581 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 582 mutex_unlock(&pcie->msi_used_lock); 583 584 for (i = 0; i < nr_irqs; i++) 585 irq_domain_set_info(domain, virq + i, hwirq + i, 586 &pcie->msi_bottom_irq_chip, 587 domain->host_data, handle_simple_irq, 588 NULL, NULL); 589 590 return hwirq; 591 } 592 593 static void advk_msi_irq_domain_free(struct irq_domain *domain, 594 unsigned int virq, unsigned int nr_irqs) 595 { 596 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 597 struct advk_pcie *pcie = domain->host_data; 598 599 mutex_lock(&pcie->msi_used_lock); 600 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 601 mutex_unlock(&pcie->msi_used_lock); 602 } 603 604 static const struct irq_domain_ops advk_msi_domain_ops = { 605 .alloc = advk_msi_irq_domain_alloc, 606 .free = advk_msi_irq_domain_free, 607 }; 608 609 static void advk_pcie_irq_mask(struct irq_data *d) 610 { 611 struct advk_pcie *pcie = d->domain->host_data; 612 irq_hw_number_t hwirq = irqd_to_hwirq(d); 613 u32 mask; 614 615 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 616 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 617 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 618 } 619 620 static void advk_pcie_irq_unmask(struct irq_data *d) 621 { 622 struct advk_pcie *pcie = d->domain->host_data; 623 irq_hw_number_t hwirq = irqd_to_hwirq(d); 624 u32 mask; 625 626 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 627 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 628 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 629 } 630 631 static int advk_pcie_irq_map(struct irq_domain *h, 632 unsigned int virq, irq_hw_number_t hwirq) 633 { 634 struct advk_pcie *pcie = h->host_data; 635 636 advk_pcie_irq_mask(irq_get_irq_data(virq)); 637 irq_set_status_flags(virq, IRQ_LEVEL); 638 irq_set_chip_and_handler(virq, &pcie->irq_chip, 639 handle_level_irq); 640 irq_set_chip_data(virq, pcie); 641 642 return 0; 643 } 644 645 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 646 .map = advk_pcie_irq_map, 647 .xlate = irq_domain_xlate_onecell, 648 }; 649 650 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 651 { 652 struct device *dev = &pcie->pdev->dev; 653 struct device_node *node = dev->of_node; 654 struct irq_chip *bottom_ic, *msi_ic; 655 struct msi_domain_info *msi_di; 656 phys_addr_t msi_msg_phys; 657 658 mutex_init(&pcie->msi_used_lock); 659 660 bottom_ic = &pcie->msi_bottom_irq_chip; 661 662 bottom_ic->name = "MSI"; 663 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 664 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 665 666 msi_ic = &pcie->msi_irq_chip; 667 msi_ic->name = "advk-MSI"; 668 669 msi_di = &pcie->msi_domain_info; 670 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 671 MSI_FLAG_MULTI_PCI_MSI; 672 msi_di->chip = msi_ic; 673 674 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 675 676 advk_writel(pcie, lower_32_bits(msi_msg_phys), 677 PCIE_MSI_ADDR_LOW_REG); 678 advk_writel(pcie, upper_32_bits(msi_msg_phys), 679 PCIE_MSI_ADDR_HIGH_REG); 680 681 pcie->msi_inner_domain = 682 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 683 &advk_msi_domain_ops, pcie); 684 if (!pcie->msi_inner_domain) 685 return -ENOMEM; 686 687 pcie->msi_domain = 688 pci_msi_create_irq_domain(of_node_to_fwnode(node), 689 msi_di, pcie->msi_inner_domain); 690 if (!pcie->msi_domain) { 691 irq_domain_remove(pcie->msi_inner_domain); 692 return -ENOMEM; 693 } 694 695 return 0; 696 } 697 698 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 699 { 700 irq_domain_remove(pcie->msi_domain); 701 irq_domain_remove(pcie->msi_inner_domain); 702 } 703 704 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 705 { 706 struct device *dev = &pcie->pdev->dev; 707 struct device_node *node = dev->of_node; 708 struct device_node *pcie_intc_node; 709 struct irq_chip *irq_chip; 710 711 pcie_intc_node = of_get_next_child(node, NULL); 712 if (!pcie_intc_node) { 713 dev_err(dev, "No PCIe Intc node found\n"); 714 return -ENODEV; 715 } 716 717 irq_chip = &pcie->irq_chip; 718 719 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 720 dev_name(dev)); 721 if (!irq_chip->name) { 722 of_node_put(pcie_intc_node); 723 return -ENOMEM; 724 } 725 726 irq_chip->irq_mask = advk_pcie_irq_mask; 727 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 728 irq_chip->irq_unmask = advk_pcie_irq_unmask; 729 730 pcie->irq_domain = 731 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 732 &advk_pcie_irq_domain_ops, pcie); 733 if (!pcie->irq_domain) { 734 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 735 of_node_put(pcie_intc_node); 736 return -ENOMEM; 737 } 738 739 return 0; 740 } 741 742 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 743 { 744 irq_domain_remove(pcie->irq_domain); 745 } 746 747 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 748 { 749 u32 msi_val, msi_mask, msi_status, msi_idx; 750 u16 msi_data; 751 752 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 753 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 754 msi_status = msi_val & ~msi_mask; 755 756 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 757 if (!(BIT(msi_idx) & msi_status)) 758 continue; 759 760 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 761 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 762 generic_handle_irq(msi_data); 763 } 764 765 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 766 PCIE_ISR0_REG); 767 } 768 769 static void advk_pcie_handle_int(struct advk_pcie *pcie) 770 { 771 u32 isr0_val, isr0_mask, isr0_status; 772 u32 isr1_val, isr1_mask, isr1_status; 773 int i, virq; 774 775 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 776 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 777 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 778 779 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 780 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 781 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 782 783 if (!isr0_status && !isr1_status) { 784 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 785 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 786 return; 787 } 788 789 /* Process MSI interrupts */ 790 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 791 advk_pcie_handle_msi(pcie); 792 793 /* Process legacy interrupts */ 794 for (i = 0; i < PCI_NUM_INTX; i++) { 795 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 796 continue; 797 798 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 799 PCIE_ISR1_REG); 800 801 virq = irq_find_mapping(pcie->irq_domain, i); 802 generic_handle_irq(virq); 803 } 804 } 805 806 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 807 { 808 struct advk_pcie *pcie = arg; 809 u32 status; 810 811 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 812 if (!(status & PCIE_IRQ_CORE_INT)) 813 return IRQ_NONE; 814 815 advk_pcie_handle_int(pcie); 816 817 /* Clear interrupt */ 818 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 819 820 return IRQ_HANDLED; 821 } 822 823 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) 824 { 825 int err, res_valid = 0; 826 struct device *dev = &pcie->pdev->dev; 827 struct resource_entry *win, *tmp; 828 resource_size_t iobase; 829 830 INIT_LIST_HEAD(&pcie->resources); 831 832 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 833 &pcie->resources, &iobase); 834 if (err) 835 return err; 836 837 err = devm_request_pci_bus_resources(dev, &pcie->resources); 838 if (err) 839 goto out_release_res; 840 841 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { 842 struct resource *res = win->res; 843 844 switch (resource_type(res)) { 845 case IORESOURCE_IO: 846 advk_pcie_set_ob_win(pcie, 1, 847 upper_32_bits(res->start), 848 lower_32_bits(res->start), 849 0, 0xF8000000, 0, 850 lower_32_bits(res->start), 851 OB_PCIE_IO); 852 err = pci_remap_iospace(res, iobase); 853 if (err) { 854 dev_warn(dev, "error %d: failed to map resource %pR\n", 855 err, res); 856 resource_list_destroy_entry(win); 857 } 858 break; 859 case IORESOURCE_MEM: 860 advk_pcie_set_ob_win(pcie, 0, 861 upper_32_bits(res->start), 862 lower_32_bits(res->start), 863 0x0, 0xF8000000, 0, 864 lower_32_bits(res->start), 865 (2 << 20) | OB_PCIE_MEM); 866 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 867 break; 868 case IORESOURCE_BUS: 869 pcie->root_bus_nr = res->start; 870 break; 871 } 872 } 873 874 if (!res_valid) { 875 dev_err(dev, "non-prefetchable memory resource required\n"); 876 err = -EINVAL; 877 goto out_release_res; 878 } 879 880 return 0; 881 882 out_release_res: 883 pci_free_resource_list(&pcie->resources); 884 return err; 885 } 886 887 static int advk_pcie_probe(struct platform_device *pdev) 888 { 889 struct device *dev = &pdev->dev; 890 struct advk_pcie *pcie; 891 struct resource *res; 892 struct pci_bus *bus, *child; 893 struct pci_host_bridge *bridge; 894 int ret, irq; 895 896 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 897 if (!bridge) 898 return -ENOMEM; 899 900 pcie = pci_host_bridge_priv(bridge); 901 pcie->pdev = pdev; 902 903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904 pcie->base = devm_ioremap_resource(dev, res); 905 if (IS_ERR(pcie->base)) 906 return PTR_ERR(pcie->base); 907 908 irq = platform_get_irq(pdev, 0); 909 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 910 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 911 pcie); 912 if (ret) { 913 dev_err(dev, "Failed to register interrupt\n"); 914 return ret; 915 } 916 917 ret = advk_pcie_parse_request_of_pci_ranges(pcie); 918 if (ret) { 919 dev_err(dev, "Failed to parse resources\n"); 920 return ret; 921 } 922 923 advk_pcie_setup_hw(pcie); 924 925 ret = advk_pcie_init_irq_domain(pcie); 926 if (ret) { 927 dev_err(dev, "Failed to initialize irq\n"); 928 return ret; 929 } 930 931 ret = advk_pcie_init_msi_irq_domain(pcie); 932 if (ret) { 933 dev_err(dev, "Failed to initialize irq\n"); 934 advk_pcie_remove_irq_domain(pcie); 935 return ret; 936 } 937 938 list_splice_init(&pcie->resources, &bridge->windows); 939 bridge->dev.parent = dev; 940 bridge->sysdata = pcie; 941 bridge->busnr = 0; 942 bridge->ops = &advk_pcie_ops; 943 bridge->map_irq = of_irq_parse_and_map_pci; 944 bridge->swizzle_irq = pci_common_swizzle; 945 946 ret = pci_scan_root_bus_bridge(bridge); 947 if (ret < 0) { 948 advk_pcie_remove_msi_irq_domain(pcie); 949 advk_pcie_remove_irq_domain(pcie); 950 return ret; 951 } 952 953 bus = bridge->bus; 954 955 pci_bus_assign_resources(bus); 956 957 list_for_each_entry(child, &bus->children, node) 958 pcie_bus_configure_settings(child); 959 960 pci_bus_add_devices(bus); 961 return 0; 962 } 963 964 static const struct of_device_id advk_pcie_of_match_table[] = { 965 { .compatible = "marvell,armada-3700-pcie", }, 966 {}, 967 }; 968 969 static struct platform_driver advk_pcie_driver = { 970 .driver = { 971 .name = "advk-pcie", 972 .of_match_table = advk_pcie_of_match_table, 973 /* Driver unloading/unbinding currently not supported */ 974 .suppress_bind_attrs = true, 975 }, 976 .probe = advk_pcie_probe, 977 }; 978 builtin_platform_driver(advk_pcie_driver); 979