1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/msi.h> 20 #include <linux/of_address.h> 21 #include <linux/of_pci.h> 22 23 #include "../pci.h" 24 #include "../pci-bridge-emul.h" 25 26 /* PCIe core registers */ 27 #define PCIE_CORE_DEV_ID_REG 0x0 28 #define PCIE_CORE_CMD_STATUS_REG 0x4 29 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 30 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 31 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 32 #define PCIE_CORE_DEV_REV_REG 0x8 33 #define PCIE_CORE_PCIEXP_CAP 0xc0 34 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 35 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) 36 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 37 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) 38 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 39 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 40 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 41 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) 42 #define PCIE_CORE_LINK_TRAINING BIT(5) 43 #define PCIE_CORE_LINK_WIDTH_SHIFT 20 44 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 45 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 47 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 48 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 49 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1 50 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2 51 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3 52 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4 53 /* PIO registers base address and register offsets */ 54 #define PIO_BASE_ADDR 0x4000 55 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 56 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 57 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 58 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 59 #define PIO_COMPLETION_STATUS_SHIFT 7 60 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 61 #define PIO_COMPLETION_STATUS_OK 0 62 #define PIO_COMPLETION_STATUS_UR 1 63 #define PIO_COMPLETION_STATUS_CRS 2 64 #define PIO_COMPLETION_STATUS_CA 4 65 #define PIO_NON_POSTED_REQ BIT(0) 66 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 67 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 68 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 69 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 70 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 71 #define PIO_START (PIO_BASE_ADDR + 0x1c) 72 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 73 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 74 75 /* Aardvark Control registers */ 76 #define CONTROL_BASE_ADDR 0x4800 77 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 78 #define PCIE_GEN_SEL_MSK 0x3 79 #define PCIE_GEN_SEL_SHIFT 0x0 80 #define SPEED_GEN_1 0 81 #define SPEED_GEN_2 1 82 #define SPEED_GEN_3 2 83 #define IS_RC_MSK 1 84 #define IS_RC_SHIFT 2 85 #define LANE_CNT_MSK 0x18 86 #define LANE_CNT_SHIFT 0x3 87 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 88 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 89 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 90 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 91 #define LINK_TRAINING_EN BIT(6) 92 #define LEGACY_INTA BIT(28) 93 #define LEGACY_INTB BIT(29) 94 #define LEGACY_INTC BIT(30) 95 #define LEGACY_INTD BIT(31) 96 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 97 #define HOT_RESET_GEN BIT(0) 98 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 99 #define PCIE_CORE_CTRL2_RESERVED 0x7 100 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 101 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 102 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 103 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 104 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 105 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 106 #define PCIE_MSG_PM_PME_MASK BIT(7) 107 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 108 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 109 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 110 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 111 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 112 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 113 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 114 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 115 #define PCIE_ISR1_FLUSH BIT(5) 116 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 117 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 118 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 119 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 120 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 121 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 122 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 123 124 /* LMI registers base address and register offsets */ 125 #define LMI_BASE_ADDR 0x6000 126 #define CFG_REG (LMI_BASE_ADDR + 0x0) 127 #define LTSSM_SHIFT 24 128 #define LTSSM_MASK 0x3f 129 #define LTSSM_L0 0x10 130 #define RC_BAR_CONFIG 0x300 131 132 /* PCIe core controller registers */ 133 #define CTRL_CORE_BASE_ADDR 0x18000 134 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 135 #define CTRL_MODE_SHIFT 0x0 136 #define CTRL_MODE_MASK 0x1 137 #define PCIE_CORE_MODE_DIRECT 0x0 138 #define PCIE_CORE_MODE_COMMAND 0x1 139 140 /* PCIe Central Interrupts Registers */ 141 #define CENTRAL_INT_BASE_ADDR 0x1b000 142 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 143 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 144 #define PCIE_IRQ_CMDQ_INT BIT(0) 145 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 146 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 147 #define PCIE_IRQ_DMA_INT BIT(4) 148 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 149 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 150 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 151 #define PCIE_IRQ_COMPQ_INT BIT(12) 152 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 153 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 154 #define PCIE_IRQ_CORE_INT BIT(16) 155 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 156 #define PCIE_IRQ_DPMU_INT BIT(18) 157 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 158 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 159 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 160 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 161 #define PCIE_IRQ_EP_STATUS BIT(23) 162 #define PCIE_IRQ_ALL_MASK 0xfff0fb 163 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 164 165 /* Transaction types */ 166 #define PCIE_CONFIG_RD_TYPE0 0x8 167 #define PCIE_CONFIG_RD_TYPE1 0x9 168 #define PCIE_CONFIG_WR_TYPE0 0xa 169 #define PCIE_CONFIG_WR_TYPE1 0xb 170 171 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 172 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 173 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 174 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 175 #define PCIE_CONF_ADDR(bus, devfn, where) \ 176 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 177 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 178 179 #define PIO_RETRY_CNT 500 180 #define PIO_RETRY_DELAY 2 /* 2 us*/ 181 182 #define LINK_WAIT_MAX_RETRIES 10 183 #define LINK_WAIT_USLEEP_MIN 90000 184 #define LINK_WAIT_USLEEP_MAX 100000 185 #define RETRAIN_WAIT_MAX_RETRIES 10 186 #define RETRAIN_WAIT_USLEEP_US 2000 187 188 #define MSI_IRQ_NUM 32 189 190 struct advk_pcie { 191 struct platform_device *pdev; 192 void __iomem *base; 193 struct irq_domain *irq_domain; 194 struct irq_chip irq_chip; 195 struct irq_domain *msi_domain; 196 struct irq_domain *msi_inner_domain; 197 struct irq_chip msi_bottom_irq_chip; 198 struct irq_chip msi_irq_chip; 199 struct msi_domain_info msi_domain_info; 200 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 201 struct mutex msi_used_lock; 202 u16 msi_msg; 203 int root_bus_nr; 204 struct pci_bridge_emul bridge; 205 }; 206 207 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 208 { 209 writel(val, pcie->base + reg); 210 } 211 212 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 213 { 214 return readl(pcie->base + reg); 215 } 216 217 static int advk_pcie_link_up(struct advk_pcie *pcie) 218 { 219 u32 val, ltssm_state; 220 221 val = advk_readl(pcie, CFG_REG); 222 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 223 return ltssm_state >= LTSSM_L0; 224 } 225 226 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 227 { 228 struct device *dev = &pcie->pdev->dev; 229 int retries; 230 231 /* check if the link is up or not */ 232 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 233 if (advk_pcie_link_up(pcie)) { 234 dev_info(dev, "link up\n"); 235 return 0; 236 } 237 238 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 239 } 240 241 dev_err(dev, "link never came up\n"); 242 return -ETIMEDOUT; 243 } 244 245 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 246 { 247 size_t retries; 248 249 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 250 if (!advk_pcie_link_up(pcie)) 251 break; 252 udelay(RETRAIN_WAIT_USLEEP_US); 253 } 254 } 255 256 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 257 { 258 u32 reg; 259 260 /* Set to Direct mode */ 261 reg = advk_readl(pcie, CTRL_CONFIG_REG); 262 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 263 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 264 advk_writel(pcie, reg, CTRL_CONFIG_REG); 265 266 /* Set PCI global control register to RC mode */ 267 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 268 reg |= (IS_RC_MSK << IS_RC_SHIFT); 269 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 270 271 /* Set Advanced Error Capabilities and Control PF0 register */ 272 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 273 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 274 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 275 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 276 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 277 278 /* Set PCIe Device Control and Status 1 PF0 register */ 279 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | 280 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | 281 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | 282 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << 283 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); 284 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); 285 286 /* Program PCIe Control 2 to disable strict ordering */ 287 reg = PCIE_CORE_CTRL2_RESERVED | 288 PCIE_CORE_CTRL2_TD_ENABLE; 289 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 290 291 /* Set GEN2 */ 292 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 293 reg &= ~PCIE_GEN_SEL_MSK; 294 reg |= SPEED_GEN_2; 295 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 296 297 /* Set lane X1 */ 298 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 299 reg &= ~LANE_CNT_MSK; 300 reg |= LANE_COUNT_1; 301 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 302 303 /* Enable link training */ 304 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 305 reg |= LINK_TRAINING_EN; 306 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 307 308 /* Enable MSI */ 309 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 310 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 311 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 312 313 /* Clear all interrupts */ 314 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 315 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 316 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 317 318 /* Disable All ISR0/1 Sources */ 319 reg = PCIE_ISR0_ALL_MASK; 320 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 321 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 322 323 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 324 325 /* Unmask all MSIs */ 326 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 327 328 /* Enable summary interrupt for GIC SPI source */ 329 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 330 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 331 332 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 333 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 334 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 335 336 /* Bypass the address window mapping for PIO */ 337 reg = advk_readl(pcie, PIO_CTRL); 338 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 339 advk_writel(pcie, reg, PIO_CTRL); 340 341 /* 342 * PERST# signal could have been asserted by pinctrl subsystem before 343 * probe() callback has been called, making the endpoint going into 344 * fundamental reset. As required by PCI Express spec a delay for at 345 * least 100ms after such a reset before link training is needed. 346 */ 347 msleep(PCI_PM_D3COLD_WAIT); 348 349 /* Start link training */ 350 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); 351 reg |= PCIE_CORE_LINK_TRAINING; 352 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 353 354 advk_pcie_wait_for_link(pcie); 355 356 reg = PCIE_CORE_LINK_L0S_ENTRY | 357 (1 << PCIE_CORE_LINK_WIDTH_SHIFT); 358 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 359 360 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 361 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 362 PCIE_CORE_CMD_IO_ACCESS_EN | 363 PCIE_CORE_CMD_MEM_IO_REQ_EN; 364 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 365 } 366 367 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 368 { 369 struct device *dev = &pcie->pdev->dev; 370 u32 reg; 371 unsigned int status; 372 char *strcomp_status, *str_posted; 373 374 reg = advk_readl(pcie, PIO_STAT); 375 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 376 PIO_COMPLETION_STATUS_SHIFT; 377 378 if (!status) 379 return; 380 381 switch (status) { 382 case PIO_COMPLETION_STATUS_UR: 383 strcomp_status = "UR"; 384 break; 385 case PIO_COMPLETION_STATUS_CRS: 386 strcomp_status = "CRS"; 387 break; 388 case PIO_COMPLETION_STATUS_CA: 389 strcomp_status = "CA"; 390 break; 391 default: 392 strcomp_status = "Unknown"; 393 break; 394 } 395 396 if (reg & PIO_NON_POSTED_REQ) 397 str_posted = "Non-posted"; 398 else 399 str_posted = "Posted"; 400 401 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 402 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 403 } 404 405 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 406 { 407 struct device *dev = &pcie->pdev->dev; 408 int i; 409 410 for (i = 0; i < PIO_RETRY_CNT; i++) { 411 u32 start, isr; 412 413 start = advk_readl(pcie, PIO_START); 414 isr = advk_readl(pcie, PIO_ISR); 415 if (!start && isr) 416 return 0; 417 udelay(PIO_RETRY_DELAY); 418 } 419 420 dev_err(dev, "config read/write timed out\n"); 421 return -ETIMEDOUT; 422 } 423 424 425 static pci_bridge_emul_read_status_t 426 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 427 int reg, u32 *value) 428 { 429 struct advk_pcie *pcie = bridge->data; 430 431 432 switch (reg) { 433 case PCI_EXP_SLTCTL: 434 *value = PCI_EXP_SLTSTA_PDS << 16; 435 return PCI_BRIDGE_EMUL_HANDLED; 436 437 case PCI_EXP_RTCTL: { 438 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 439 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; 440 return PCI_BRIDGE_EMUL_HANDLED; 441 } 442 443 case PCI_EXP_RTSTA: { 444 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); 445 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); 446 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16); 447 return PCI_BRIDGE_EMUL_HANDLED; 448 } 449 450 case PCI_EXP_LNKCTL: { 451 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 452 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 453 ~(PCI_EXP_LNKSTA_LT << 16); 454 if (!advk_pcie_link_up(pcie)) 455 val |= (PCI_EXP_LNKSTA_LT << 16); 456 *value = val; 457 return PCI_BRIDGE_EMUL_HANDLED; 458 } 459 460 case PCI_CAP_LIST_ID: 461 case PCI_EXP_DEVCAP: 462 case PCI_EXP_DEVCTL: 463 case PCI_EXP_LNKCAP: 464 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 465 return PCI_BRIDGE_EMUL_HANDLED; 466 default: 467 return PCI_BRIDGE_EMUL_NOT_HANDLED; 468 } 469 470 } 471 472 static void 473 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 474 int reg, u32 old, u32 new, u32 mask) 475 { 476 struct advk_pcie *pcie = bridge->data; 477 478 switch (reg) { 479 case PCI_EXP_DEVCTL: 480 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 481 break; 482 483 case PCI_EXP_LNKCTL: 484 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 485 if (new & PCI_EXP_LNKCTL_RL) 486 advk_pcie_wait_for_retrain(pcie); 487 break; 488 489 case PCI_EXP_RTCTL: { 490 /* Only mask/unmask PME interrupt */ 491 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & 492 ~PCIE_MSG_PM_PME_MASK; 493 if ((new & PCI_EXP_RTCTL_PMEIE) == 0) 494 val |= PCIE_MSG_PM_PME_MASK; 495 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 496 break; 497 } 498 499 case PCI_EXP_RTSTA: 500 new = (new & PCI_EXP_RTSTA_PME) >> 9; 501 advk_writel(pcie, new, PCIE_ISR0_REG); 502 break; 503 504 default: 505 break; 506 } 507 } 508 509 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 510 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 511 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 512 }; 513 514 /* 515 * Initialize the configuration space of the PCI-to-PCI bridge 516 * associated with the given PCIe interface. 517 */ 518 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie) 519 { 520 struct pci_bridge_emul *bridge = &pcie->bridge; 521 522 bridge->conf.vendor = 523 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 524 bridge->conf.device = 525 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 526 bridge->conf.class_revision = 527 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 528 529 /* Support 32 bits I/O addressing */ 530 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 531 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 532 533 /* Support 64 bits memory pref */ 534 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 535 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 536 537 /* Support interrupt A for MSI feature */ 538 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; 539 540 bridge->has_pcie = true; 541 bridge->data = pcie; 542 bridge->ops = &advk_pci_bridge_emul_ops; 543 544 pci_bridge_emul_init(bridge, 0); 545 546 } 547 548 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 549 int devfn) 550 { 551 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 552 return false; 553 554 return true; 555 } 556 557 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 558 int where, int size, u32 *val) 559 { 560 struct advk_pcie *pcie = bus->sysdata; 561 u32 reg; 562 int ret; 563 564 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 565 *val = 0xffffffff; 566 return PCIBIOS_DEVICE_NOT_FOUND; 567 } 568 569 if (bus->number == pcie->root_bus_nr) 570 return pci_bridge_emul_conf_read(&pcie->bridge, where, 571 size, val); 572 573 /* Start PIO */ 574 advk_writel(pcie, 0, PIO_START); 575 advk_writel(pcie, 1, PIO_ISR); 576 577 /* Program the control register */ 578 reg = advk_readl(pcie, PIO_CTRL); 579 reg &= ~PIO_CTRL_TYPE_MASK; 580 if (bus->primary == pcie->root_bus_nr) 581 reg |= PCIE_CONFIG_RD_TYPE0; 582 else 583 reg |= PCIE_CONFIG_RD_TYPE1; 584 advk_writel(pcie, reg, PIO_CTRL); 585 586 /* Program the address registers */ 587 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 588 advk_writel(pcie, reg, PIO_ADDR_LS); 589 advk_writel(pcie, 0, PIO_ADDR_MS); 590 591 /* Program the data strobe */ 592 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 593 594 /* Start the transfer */ 595 advk_writel(pcie, 1, PIO_START); 596 597 ret = advk_pcie_wait_pio(pcie); 598 if (ret < 0) 599 return PCIBIOS_SET_FAILED; 600 601 advk_pcie_check_pio_status(pcie); 602 603 /* Get the read result */ 604 *val = advk_readl(pcie, PIO_RD_DATA); 605 if (size == 1) 606 *val = (*val >> (8 * (where & 3))) & 0xff; 607 else if (size == 2) 608 *val = (*val >> (8 * (where & 3))) & 0xffff; 609 610 return PCIBIOS_SUCCESSFUL; 611 } 612 613 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 614 int where, int size, u32 val) 615 { 616 struct advk_pcie *pcie = bus->sysdata; 617 u32 reg; 618 u32 data_strobe = 0x0; 619 int offset; 620 int ret; 621 622 if (!advk_pcie_valid_device(pcie, bus, devfn)) 623 return PCIBIOS_DEVICE_NOT_FOUND; 624 625 if (bus->number == pcie->root_bus_nr) 626 return pci_bridge_emul_conf_write(&pcie->bridge, where, 627 size, val); 628 629 if (where % size) 630 return PCIBIOS_SET_FAILED; 631 632 /* Start PIO */ 633 advk_writel(pcie, 0, PIO_START); 634 advk_writel(pcie, 1, PIO_ISR); 635 636 /* Program the control register */ 637 reg = advk_readl(pcie, PIO_CTRL); 638 reg &= ~PIO_CTRL_TYPE_MASK; 639 if (bus->primary == pcie->root_bus_nr) 640 reg |= PCIE_CONFIG_WR_TYPE0; 641 else 642 reg |= PCIE_CONFIG_WR_TYPE1; 643 advk_writel(pcie, reg, PIO_CTRL); 644 645 /* Program the address registers */ 646 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 647 advk_writel(pcie, reg, PIO_ADDR_LS); 648 advk_writel(pcie, 0, PIO_ADDR_MS); 649 650 /* Calculate the write strobe */ 651 offset = where & 0x3; 652 reg = val << (8 * offset); 653 data_strobe = GENMASK(size - 1, 0) << offset; 654 655 /* Program the data register */ 656 advk_writel(pcie, reg, PIO_WR_DATA); 657 658 /* Program the data strobe */ 659 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 660 661 /* Start the transfer */ 662 advk_writel(pcie, 1, PIO_START); 663 664 ret = advk_pcie_wait_pio(pcie); 665 if (ret < 0) 666 return PCIBIOS_SET_FAILED; 667 668 advk_pcie_check_pio_status(pcie); 669 670 return PCIBIOS_SUCCESSFUL; 671 } 672 673 static struct pci_ops advk_pcie_ops = { 674 .read = advk_pcie_rd_conf, 675 .write = advk_pcie_wr_conf, 676 }; 677 678 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 679 struct msi_msg *msg) 680 { 681 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 682 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 683 684 msg->address_lo = lower_32_bits(msi_msg); 685 msg->address_hi = upper_32_bits(msi_msg); 686 msg->data = data->irq; 687 } 688 689 static int advk_msi_set_affinity(struct irq_data *irq_data, 690 const struct cpumask *mask, bool force) 691 { 692 return -EINVAL; 693 } 694 695 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 696 unsigned int virq, 697 unsigned int nr_irqs, void *args) 698 { 699 struct advk_pcie *pcie = domain->host_data; 700 int hwirq, i; 701 702 mutex_lock(&pcie->msi_used_lock); 703 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 704 0, nr_irqs, 0); 705 if (hwirq >= MSI_IRQ_NUM) { 706 mutex_unlock(&pcie->msi_used_lock); 707 return -ENOSPC; 708 } 709 710 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 711 mutex_unlock(&pcie->msi_used_lock); 712 713 for (i = 0; i < nr_irqs; i++) 714 irq_domain_set_info(domain, virq + i, hwirq + i, 715 &pcie->msi_bottom_irq_chip, 716 domain->host_data, handle_simple_irq, 717 NULL, NULL); 718 719 return hwirq; 720 } 721 722 static void advk_msi_irq_domain_free(struct irq_domain *domain, 723 unsigned int virq, unsigned int nr_irqs) 724 { 725 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 726 struct advk_pcie *pcie = domain->host_data; 727 728 mutex_lock(&pcie->msi_used_lock); 729 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 730 mutex_unlock(&pcie->msi_used_lock); 731 } 732 733 static const struct irq_domain_ops advk_msi_domain_ops = { 734 .alloc = advk_msi_irq_domain_alloc, 735 .free = advk_msi_irq_domain_free, 736 }; 737 738 static void advk_pcie_irq_mask(struct irq_data *d) 739 { 740 struct advk_pcie *pcie = d->domain->host_data; 741 irq_hw_number_t hwirq = irqd_to_hwirq(d); 742 u32 mask; 743 744 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 745 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 746 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 747 } 748 749 static void advk_pcie_irq_unmask(struct irq_data *d) 750 { 751 struct advk_pcie *pcie = d->domain->host_data; 752 irq_hw_number_t hwirq = irqd_to_hwirq(d); 753 u32 mask; 754 755 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 756 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 757 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 758 } 759 760 static int advk_pcie_irq_map(struct irq_domain *h, 761 unsigned int virq, irq_hw_number_t hwirq) 762 { 763 struct advk_pcie *pcie = h->host_data; 764 765 advk_pcie_irq_mask(irq_get_irq_data(virq)); 766 irq_set_status_flags(virq, IRQ_LEVEL); 767 irq_set_chip_and_handler(virq, &pcie->irq_chip, 768 handle_level_irq); 769 irq_set_chip_data(virq, pcie); 770 771 return 0; 772 } 773 774 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 775 .map = advk_pcie_irq_map, 776 .xlate = irq_domain_xlate_onecell, 777 }; 778 779 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 780 { 781 struct device *dev = &pcie->pdev->dev; 782 struct device_node *node = dev->of_node; 783 struct irq_chip *bottom_ic, *msi_ic; 784 struct msi_domain_info *msi_di; 785 phys_addr_t msi_msg_phys; 786 787 mutex_init(&pcie->msi_used_lock); 788 789 bottom_ic = &pcie->msi_bottom_irq_chip; 790 791 bottom_ic->name = "MSI"; 792 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 793 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 794 795 msi_ic = &pcie->msi_irq_chip; 796 msi_ic->name = "advk-MSI"; 797 798 msi_di = &pcie->msi_domain_info; 799 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 800 MSI_FLAG_MULTI_PCI_MSI; 801 msi_di->chip = msi_ic; 802 803 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 804 805 advk_writel(pcie, lower_32_bits(msi_msg_phys), 806 PCIE_MSI_ADDR_LOW_REG); 807 advk_writel(pcie, upper_32_bits(msi_msg_phys), 808 PCIE_MSI_ADDR_HIGH_REG); 809 810 pcie->msi_inner_domain = 811 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 812 &advk_msi_domain_ops, pcie); 813 if (!pcie->msi_inner_domain) 814 return -ENOMEM; 815 816 pcie->msi_domain = 817 pci_msi_create_irq_domain(of_node_to_fwnode(node), 818 msi_di, pcie->msi_inner_domain); 819 if (!pcie->msi_domain) { 820 irq_domain_remove(pcie->msi_inner_domain); 821 return -ENOMEM; 822 } 823 824 return 0; 825 } 826 827 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 828 { 829 irq_domain_remove(pcie->msi_domain); 830 irq_domain_remove(pcie->msi_inner_domain); 831 } 832 833 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 834 { 835 struct device *dev = &pcie->pdev->dev; 836 struct device_node *node = dev->of_node; 837 struct device_node *pcie_intc_node; 838 struct irq_chip *irq_chip; 839 int ret = 0; 840 841 pcie_intc_node = of_get_next_child(node, NULL); 842 if (!pcie_intc_node) { 843 dev_err(dev, "No PCIe Intc node found\n"); 844 return -ENODEV; 845 } 846 847 irq_chip = &pcie->irq_chip; 848 849 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 850 dev_name(dev)); 851 if (!irq_chip->name) { 852 ret = -ENOMEM; 853 goto out_put_node; 854 } 855 856 irq_chip->irq_mask = advk_pcie_irq_mask; 857 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 858 irq_chip->irq_unmask = advk_pcie_irq_unmask; 859 860 pcie->irq_domain = 861 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 862 &advk_pcie_irq_domain_ops, pcie); 863 if (!pcie->irq_domain) { 864 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 865 ret = -ENOMEM; 866 goto out_put_node; 867 } 868 869 out_put_node: 870 of_node_put(pcie_intc_node); 871 return ret; 872 } 873 874 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 875 { 876 irq_domain_remove(pcie->irq_domain); 877 } 878 879 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 880 { 881 u32 msi_val, msi_mask, msi_status, msi_idx; 882 u16 msi_data; 883 884 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 885 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 886 msi_status = msi_val & ~msi_mask; 887 888 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 889 if (!(BIT(msi_idx) & msi_status)) 890 continue; 891 892 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 893 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 894 generic_handle_irq(msi_data); 895 } 896 897 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 898 PCIE_ISR0_REG); 899 } 900 901 static void advk_pcie_handle_int(struct advk_pcie *pcie) 902 { 903 u32 isr0_val, isr0_mask, isr0_status; 904 u32 isr1_val, isr1_mask, isr1_status; 905 int i, virq; 906 907 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 908 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 909 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 910 911 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 912 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 913 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 914 915 if (!isr0_status && !isr1_status) { 916 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 917 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 918 return; 919 } 920 921 /* Process MSI interrupts */ 922 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 923 advk_pcie_handle_msi(pcie); 924 925 /* Process legacy interrupts */ 926 for (i = 0; i < PCI_NUM_INTX; i++) { 927 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 928 continue; 929 930 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 931 PCIE_ISR1_REG); 932 933 virq = irq_find_mapping(pcie->irq_domain, i); 934 generic_handle_irq(virq); 935 } 936 } 937 938 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 939 { 940 struct advk_pcie *pcie = arg; 941 u32 status; 942 943 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 944 if (!(status & PCIE_IRQ_CORE_INT)) 945 return IRQ_NONE; 946 947 advk_pcie_handle_int(pcie); 948 949 /* Clear interrupt */ 950 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 951 952 return IRQ_HANDLED; 953 } 954 955 static int advk_pcie_probe(struct platform_device *pdev) 956 { 957 struct device *dev = &pdev->dev; 958 struct advk_pcie *pcie; 959 struct resource *res, *bus; 960 struct pci_host_bridge *bridge; 961 int ret, irq; 962 963 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 964 if (!bridge) 965 return -ENOMEM; 966 967 pcie = pci_host_bridge_priv(bridge); 968 pcie->pdev = pdev; 969 970 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 971 pcie->base = devm_ioremap_resource(dev, res); 972 if (IS_ERR(pcie->base)) 973 return PTR_ERR(pcie->base); 974 975 irq = platform_get_irq(pdev, 0); 976 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 977 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 978 pcie); 979 if (ret) { 980 dev_err(dev, "Failed to register interrupt\n"); 981 return ret; 982 } 983 984 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, 985 &bridge->dma_ranges, &bus); 986 if (ret) { 987 dev_err(dev, "Failed to parse resources\n"); 988 return ret; 989 } 990 pcie->root_bus_nr = bus->start; 991 992 advk_pcie_setup_hw(pcie); 993 994 advk_sw_pci_bridge_init(pcie); 995 996 ret = advk_pcie_init_irq_domain(pcie); 997 if (ret) { 998 dev_err(dev, "Failed to initialize irq\n"); 999 return ret; 1000 } 1001 1002 ret = advk_pcie_init_msi_irq_domain(pcie); 1003 if (ret) { 1004 dev_err(dev, "Failed to initialize irq\n"); 1005 advk_pcie_remove_irq_domain(pcie); 1006 return ret; 1007 } 1008 1009 bridge->dev.parent = dev; 1010 bridge->sysdata = pcie; 1011 bridge->busnr = 0; 1012 bridge->ops = &advk_pcie_ops; 1013 bridge->map_irq = of_irq_parse_and_map_pci; 1014 bridge->swizzle_irq = pci_common_swizzle; 1015 1016 ret = pci_host_probe(bridge); 1017 if (ret < 0) { 1018 advk_pcie_remove_msi_irq_domain(pcie); 1019 advk_pcie_remove_irq_domain(pcie); 1020 return ret; 1021 } 1022 1023 return 0; 1024 } 1025 1026 static const struct of_device_id advk_pcie_of_match_table[] = { 1027 { .compatible = "marvell,armada-3700-pcie", }, 1028 {}, 1029 }; 1030 1031 static struct platform_driver advk_pcie_driver = { 1032 .driver = { 1033 .name = "advk-pcie", 1034 .of_match_table = advk_pcie_of_match_table, 1035 /* Driver unloading/unbinding currently not supported */ 1036 .suppress_bind_attrs = true, 1037 }, 1038 .probe = advk_pcie_probe, 1039 }; 1040 builtin_platform_driver(advk_pcie_driver); 1041