1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/init.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/msi.h> 24 #include <linux/of_address.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_pci.h> 27 28 #include "../pci.h" 29 #include "../pci-bridge-emul.h" 30 31 /* PCIe core registers */ 32 #define PCIE_CORE_DEV_ID_REG 0x0 33 #define PCIE_CORE_CMD_STATUS_REG 0x4 34 #define PCIE_CORE_DEV_REV_REG 0x8 35 #define PCIE_CORE_PCIEXP_CAP 0xc0 36 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 41 /* PIO registers base address and register offsets */ 42 #define PIO_BASE_ADDR 0x4000 43 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 44 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 45 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 46 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 47 #define PIO_COMPLETION_STATUS_SHIFT 7 48 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 49 #define PIO_COMPLETION_STATUS_OK 0 50 #define PIO_COMPLETION_STATUS_UR 1 51 #define PIO_COMPLETION_STATUS_CRS 2 52 #define PIO_COMPLETION_STATUS_CA 4 53 #define PIO_NON_POSTED_REQ BIT(10) 54 #define PIO_ERR_STATUS BIT(11) 55 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 56 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 57 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 58 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 59 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 60 #define PIO_START (PIO_BASE_ADDR + 0x1c) 61 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 62 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 63 64 /* Aardvark Control registers */ 65 #define CONTROL_BASE_ADDR 0x4800 66 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 67 #define PCIE_GEN_SEL_MSK 0x3 68 #define PCIE_GEN_SEL_SHIFT 0x0 69 #define SPEED_GEN_1 0 70 #define SPEED_GEN_2 1 71 #define SPEED_GEN_3 2 72 #define IS_RC_MSK 1 73 #define IS_RC_SHIFT 2 74 #define LANE_CNT_MSK 0x18 75 #define LANE_CNT_SHIFT 0x3 76 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 77 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 78 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 79 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 80 #define LINK_TRAINING_EN BIT(6) 81 #define LEGACY_INTA BIT(28) 82 #define LEGACY_INTB BIT(29) 83 #define LEGACY_INTC BIT(30) 84 #define LEGACY_INTD BIT(31) 85 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 86 #define HOT_RESET_GEN BIT(0) 87 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 88 #define PCIE_CORE_CTRL2_RESERVED 0x7 89 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 90 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 91 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 92 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 93 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) 94 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) 95 #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2) 96 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 97 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 98 #define PCIE_MSG_PM_PME_MASK BIT(7) 99 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 100 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 101 #define PCIE_ISR0_CORR_ERR BIT(11) 102 #define PCIE_ISR0_NFAT_ERR BIT(12) 103 #define PCIE_ISR0_FAT_ERR BIT(13) 104 #define PCIE_ISR0_ERR_MASK GENMASK(13, 11) 105 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 106 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 107 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) 108 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 109 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 110 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 111 #define PCIE_ISR1_FLUSH BIT(5) 112 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 113 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0) 114 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 115 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 116 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 117 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 118 #define PCIE_MSI_ALL_MASK GENMASK(31, 0) 119 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 120 #define PCIE_MSI_DATA_MASK GENMASK(15, 0) 121 122 /* PCIe window configuration */ 123 #define OB_WIN_BASE_ADDR 0x4c00 124 #define OB_WIN_BLOCK_SIZE 0x20 125 #define OB_WIN_COUNT 8 126 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ 127 OB_WIN_BLOCK_SIZE * (win) + \ 128 (offset)) 129 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) 130 #define OB_WIN_ENABLE BIT(0) 131 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) 132 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) 133 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) 134 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) 135 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) 136 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) 137 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) 138 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) 139 #define OB_WIN_FUNC_NUM_SHIFT 24 140 #define OB_WIN_FUNC_NUM_ENABLE BIT(23) 141 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) 142 #define OB_WIN_BUS_NUM_BITS_SHIFT 20 143 #define OB_WIN_MSG_CODE_ENABLE BIT(22) 144 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) 145 #define OB_WIN_MSG_CODE_SHIFT 14 146 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12) 147 #define OB_WIN_ATTR_ENABLE BIT(11) 148 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) 149 #define OB_WIN_ATTR_TC_SHIFT 8 150 #define OB_WIN_ATTR_RELAXED BIT(7) 151 #define OB_WIN_ATTR_NOSNOOP BIT(6) 152 #define OB_WIN_ATTR_POISON BIT(5) 153 #define OB_WIN_ATTR_IDO BIT(4) 154 #define OB_WIN_TYPE_MASK GENMASK(3, 0) 155 #define OB_WIN_TYPE_SHIFT 0 156 #define OB_WIN_TYPE_MEM 0x0 157 #define OB_WIN_TYPE_IO 0x4 158 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8 159 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9 160 #define OB_WIN_TYPE_MSG 0xc 161 162 /* LMI registers base address and register offsets */ 163 #define LMI_BASE_ADDR 0x6000 164 #define CFG_REG (LMI_BASE_ADDR + 0x0) 165 #define LTSSM_SHIFT 24 166 #define LTSSM_MASK 0x3f 167 #define RC_BAR_CONFIG 0x300 168 169 /* LTSSM values in CFG_REG */ 170 enum { 171 LTSSM_DETECT_QUIET = 0x0, 172 LTSSM_DETECT_ACTIVE = 0x1, 173 LTSSM_POLLING_ACTIVE = 0x2, 174 LTSSM_POLLING_COMPLIANCE = 0x3, 175 LTSSM_POLLING_CONFIGURATION = 0x4, 176 LTSSM_CONFIG_LINKWIDTH_START = 0x5, 177 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6, 178 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7, 179 LTSSM_CONFIG_LANENUM_WAIT = 0x8, 180 LTSSM_CONFIG_COMPLETE = 0x9, 181 LTSSM_CONFIG_IDLE = 0xa, 182 LTSSM_RECOVERY_RCVR_LOCK = 0xb, 183 LTSSM_RECOVERY_SPEED = 0xc, 184 LTSSM_RECOVERY_RCVR_CFG = 0xd, 185 LTSSM_RECOVERY_IDLE = 0xe, 186 LTSSM_L0 = 0x10, 187 LTSSM_RX_L0S_ENTRY = 0x11, 188 LTSSM_RX_L0S_IDLE = 0x12, 189 LTSSM_RX_L0S_FTS = 0x13, 190 LTSSM_TX_L0S_ENTRY = 0x14, 191 LTSSM_TX_L0S_IDLE = 0x15, 192 LTSSM_TX_L0S_FTS = 0x16, 193 LTSSM_L1_ENTRY = 0x17, 194 LTSSM_L1_IDLE = 0x18, 195 LTSSM_L2_IDLE = 0x19, 196 LTSSM_L2_TRANSMIT_WAKE = 0x1a, 197 LTSSM_DISABLED = 0x20, 198 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21, 199 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22, 200 LTSSM_LOOPBACK_EXIT_MASTER = 0x23, 201 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24, 202 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25, 203 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26, 204 LTSSM_HOT_RESET = 0x27, 205 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28, 206 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29, 207 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a, 208 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b, 209 }; 210 211 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) 212 213 /* PCIe core controller registers */ 214 #define CTRL_CORE_BASE_ADDR 0x18000 215 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 216 #define CTRL_MODE_SHIFT 0x0 217 #define CTRL_MODE_MASK 0x1 218 #define PCIE_CORE_MODE_DIRECT 0x0 219 #define PCIE_CORE_MODE_COMMAND 0x1 220 221 /* PCIe Central Interrupts Registers */ 222 #define CENTRAL_INT_BASE_ADDR 0x1b000 223 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 224 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 225 #define PCIE_IRQ_CMDQ_INT BIT(0) 226 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 227 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 228 #define PCIE_IRQ_DMA_INT BIT(4) 229 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 230 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 231 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 232 #define PCIE_IRQ_COMPQ_INT BIT(12) 233 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 234 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 235 #define PCIE_IRQ_CORE_INT BIT(16) 236 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 237 #define PCIE_IRQ_DPMU_INT BIT(18) 238 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 239 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 240 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 241 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 242 #define PCIE_IRQ_EP_STATUS BIT(23) 243 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0) 244 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 245 246 /* Transaction types */ 247 #define PCIE_CONFIG_RD_TYPE0 0x8 248 #define PCIE_CONFIG_RD_TYPE1 0x9 249 #define PCIE_CONFIG_WR_TYPE0 0xa 250 #define PCIE_CONFIG_WR_TYPE1 0xb 251 252 #define PIO_RETRY_CNT 750000 /* 1.5 s */ 253 #define PIO_RETRY_DELAY 2 /* 2 us*/ 254 255 #define LINK_WAIT_MAX_RETRIES 10 256 #define LINK_WAIT_USLEEP_MIN 90000 257 #define LINK_WAIT_USLEEP_MAX 100000 258 #define RETRAIN_WAIT_MAX_RETRIES 10 259 #define RETRAIN_WAIT_USLEEP_US 2000 260 261 #define MSI_IRQ_NUM 32 262 263 #define CFG_RD_CRS_VAL 0xffff0001 264 265 struct advk_pcie { 266 struct platform_device *pdev; 267 void __iomem *base; 268 struct { 269 phys_addr_t match; 270 phys_addr_t remap; 271 phys_addr_t mask; 272 u32 actions; 273 } wins[OB_WIN_COUNT]; 274 u8 wins_count; 275 struct irq_domain *rp_irq_domain; 276 struct irq_domain *irq_domain; 277 struct irq_chip irq_chip; 278 raw_spinlock_t irq_lock; 279 struct irq_domain *msi_domain; 280 struct irq_domain *msi_inner_domain; 281 raw_spinlock_t msi_irq_lock; 282 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 283 struct mutex msi_used_lock; 284 int link_gen; 285 struct pci_bridge_emul bridge; 286 struct gpio_desc *reset_gpio; 287 struct phy *phy; 288 }; 289 290 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 291 { 292 writel(val, pcie->base + reg); 293 } 294 295 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 296 { 297 return readl(pcie->base + reg); 298 } 299 300 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) 301 { 302 u32 val; 303 u8 ltssm_state; 304 305 val = advk_readl(pcie, CFG_REG); 306 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 307 return ltssm_state; 308 } 309 310 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) 311 { 312 /* check if LTSSM is in normal operation - some L* state */ 313 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 314 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; 315 } 316 317 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) 318 { 319 /* 320 * According to PCIe Base specification 3.0, Table 4-14: Link 321 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle 322 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, 323 * L0s, L1 and L2 states. And according to 3.2.1. Data Link 324 * Control and Management State Machine Rules is DL Up status 325 * reported in DL Active state. 326 */ 327 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 328 return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED; 329 } 330 331 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) 332 { 333 /* 334 * According to PCIe Base specification 3.0, Table 4-14: Link 335 * Status Mapped to the LTSSM is Link Training mapped to LTSSM 336 * Configuration and Recovery states. 337 */ 338 u8 ltssm_state = advk_pcie_ltssm_state(pcie); 339 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START && 340 ltssm_state < LTSSM_L0) || 341 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 && 342 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3)); 343 } 344 345 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 346 { 347 int retries; 348 349 /* check if the link is up or not */ 350 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 351 if (advk_pcie_link_up(pcie)) 352 return 0; 353 354 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 355 } 356 357 return -ETIMEDOUT; 358 } 359 360 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 361 { 362 size_t retries; 363 364 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 365 if (advk_pcie_link_training(pcie)) 366 break; 367 udelay(RETRAIN_WAIT_USLEEP_US); 368 } 369 } 370 371 static void advk_pcie_issue_perst(struct advk_pcie *pcie) 372 { 373 if (!pcie->reset_gpio) 374 return; 375 376 /* 10ms delay is needed for some cards */ 377 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); 378 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 379 usleep_range(10000, 11000); 380 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 381 } 382 383 static void advk_pcie_train_link(struct advk_pcie *pcie) 384 { 385 struct device *dev = &pcie->pdev->dev; 386 u32 reg; 387 int ret; 388 389 /* 390 * Setup PCIe rev / gen compliance based on device tree property 391 * 'max-link-speed' which also forces maximal link speed. 392 */ 393 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 394 reg &= ~PCIE_GEN_SEL_MSK; 395 if (pcie->link_gen == 3) 396 reg |= SPEED_GEN_3; 397 else if (pcie->link_gen == 2) 398 reg |= SPEED_GEN_2; 399 else 400 reg |= SPEED_GEN_1; 401 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 402 403 /* 404 * Set maximal link speed value also into PCIe Link Control 2 register. 405 * Armada 3700 Functional Specification says that default value is based 406 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s. 407 */ 408 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 409 reg &= ~PCI_EXP_LNKCTL2_TLS; 410 if (pcie->link_gen == 3) 411 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT; 412 else if (pcie->link_gen == 2) 413 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT; 414 else 415 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT; 416 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); 417 418 /* Enable link training after selecting PCIe generation */ 419 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 420 reg |= LINK_TRAINING_EN; 421 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 422 423 /* 424 * Reset PCIe card via PERST# signal. Some cards are not detected 425 * during link training when they are in some non-initial state. 426 */ 427 advk_pcie_issue_perst(pcie); 428 429 /* 430 * PERST# signal could have been asserted by pinctrl subsystem before 431 * probe() callback has been called or issued explicitly by reset gpio 432 * function advk_pcie_issue_perst(), making the endpoint going into 433 * fundamental reset. As required by PCI Express spec (PCI Express 434 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1 435 * Conventional Reset) a delay for at least 100ms after such a reset 436 * before sending a Configuration Request to the device is needed. 437 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() 438 * waits for link at least 900ms. 439 */ 440 ret = advk_pcie_wait_for_link(pcie); 441 if (ret < 0) 442 dev_err(dev, "link never came up\n"); 443 else 444 dev_info(dev, "link up\n"); 445 } 446 447 /* 448 * Set PCIe address window register which could be used for memory 449 * mapping. 450 */ 451 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, 452 phys_addr_t match, phys_addr_t remap, 453 phys_addr_t mask, u32 actions) 454 { 455 advk_writel(pcie, OB_WIN_ENABLE | 456 lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); 457 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); 458 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); 459 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); 460 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); 461 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); 462 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); 463 } 464 465 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) 466 { 467 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); 468 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); 469 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); 470 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); 471 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); 472 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); 473 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); 474 } 475 476 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 477 { 478 phys_addr_t msi_addr; 479 u32 reg; 480 int i; 481 482 /* 483 * Configure PCIe Reference clock. Direction is from the PCIe 484 * controller to the endpoint card, so enable transmitting of 485 * Reference clock differential signal off-chip and disable 486 * receiving off-chip differential signal. 487 */ 488 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); 489 reg |= PCIE_CORE_REF_CLK_TX_ENABLE; 490 reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE; 491 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); 492 493 /* Set to Direct mode */ 494 reg = advk_readl(pcie, CTRL_CONFIG_REG); 495 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 496 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 497 advk_writel(pcie, reg, CTRL_CONFIG_REG); 498 499 /* Set PCI global control register to RC mode */ 500 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 501 reg |= (IS_RC_MSK << IS_RC_SHIFT); 502 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 503 504 /* 505 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. 506 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor 507 * id in high 16 bits. Updating this register changes readback value of 508 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround 509 * for erratum 4.1: "The value of device and vendor ID is incorrect". 510 */ 511 reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; 512 advk_writel(pcie, reg, VENDOR_ID_REG); 513 514 /* 515 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), 516 * because the default value is Mass storage controller (0x010400). 517 * 518 * Note that this Aardvark PCI Bridge does not have compliant Type 1 519 * Configuration Space and it even cannot be accessed via Aardvark's 520 * PCI config space access method. Something like config space is 521 * available in internal Aardvark registers starting at offset 0x0 522 * and is reported as Type 0. In range 0x10 - 0x34 it has totally 523 * different registers. 524 * 525 * Therefore driver uses emulation of PCI Bridge which emulates 526 * access to configuration space via internal Aardvark registers or 527 * emulated configuration buffer. 528 */ 529 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); 530 reg &= ~0xffffff00; 531 reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; 532 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); 533 534 /* Disable Root Bridge I/O space, memory space and bus mastering */ 535 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 536 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 537 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 538 539 /* Set Advanced Error Capabilities and Control PF0 register */ 540 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 541 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 542 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 543 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 544 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 545 546 /* Set PCIe Device Control register */ 547 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 548 reg &= ~PCI_EXP_DEVCTL_RELAX_EN; 549 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 550 reg &= ~PCI_EXP_DEVCTL_PAYLOAD; 551 reg &= ~PCI_EXP_DEVCTL_READRQ; 552 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; 553 reg |= PCI_EXP_DEVCTL_READRQ_512B; 554 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 555 556 /* Program PCIe Control 2 to disable strict ordering */ 557 reg = PCIE_CORE_CTRL2_RESERVED | 558 PCIE_CORE_CTRL2_TD_ENABLE; 559 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 560 561 /* Set lane X1 */ 562 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 563 reg &= ~LANE_CNT_MSK; 564 reg |= LANE_COUNT_1; 565 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 566 567 /* Set MSI address */ 568 msi_addr = virt_to_phys(pcie); 569 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); 570 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); 571 572 /* Enable MSI */ 573 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 574 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 575 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 576 577 /* Clear all interrupts */ 578 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); 579 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 580 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 581 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 582 583 /* Disable All ISR0/1 and MSI Sources */ 584 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); 585 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 586 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); 587 588 /* Unmask summary MSI interrupt */ 589 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); 590 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 591 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 592 593 /* Unmask PME interrupt for processing of PME requester */ 594 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); 595 reg &= ~PCIE_MSG_PM_PME_MASK; 596 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 597 598 /* Enable summary interrupt for GIC SPI source */ 599 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 600 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 601 602 /* 603 * Enable AXI address window location generation: 604 * When it is enabled, the default outbound window 605 * configurations (Default User Field: 0xD0074CFC) 606 * are used to transparent address translation for 607 * the outbound transactions. Thus, PCIe address 608 * windows are not required for transparent memory 609 * access when default outbound window configuration 610 * is set for memory access. 611 */ 612 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 613 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 614 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 615 616 /* 617 * Set memory access in Default User Field so it 618 * is not required to configure PCIe address for 619 * transparent memory access. 620 */ 621 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); 622 623 /* 624 * Bypass the address window mapping for PIO: 625 * Since PIO access already contains all required 626 * info over AXI interface by PIO registers, the 627 * address window is not required. 628 */ 629 reg = advk_readl(pcie, PIO_CTRL); 630 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 631 advk_writel(pcie, reg, PIO_CTRL); 632 633 /* 634 * Configure PCIe address windows for non-memory or 635 * non-transparent access as by default PCIe uses 636 * transparent memory access. 637 */ 638 for (i = 0; i < pcie->wins_count; i++) 639 advk_pcie_set_ob_win(pcie, i, 640 pcie->wins[i].match, pcie->wins[i].remap, 641 pcie->wins[i].mask, pcie->wins[i].actions); 642 643 /* Disable remaining PCIe outbound windows */ 644 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) 645 advk_pcie_disable_ob_win(pcie, i); 646 647 advk_pcie_train_link(pcie); 648 } 649 650 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) 651 { 652 struct device *dev = &pcie->pdev->dev; 653 u32 reg; 654 unsigned int status; 655 char *strcomp_status, *str_posted; 656 int ret; 657 658 reg = advk_readl(pcie, PIO_STAT); 659 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 660 PIO_COMPLETION_STATUS_SHIFT; 661 662 /* 663 * According to HW spec, the PIO status check sequence as below: 664 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, 665 * it still needs to check Error Status(bit11), only when this bit 666 * indicates no error happen, the operation is successful. 667 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only 668 * means a PIO write error, and for PIO read it is successful with 669 * a read value of 0xFFFFFFFF. 670 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) 671 * only means a PIO write error, and for PIO read it is successful 672 * with a read value of 0xFFFF0001. 673 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means 674 * error for both PIO read and PIO write operation. 675 * 5) other errors are indicated as 'unknown'. 676 */ 677 switch (status) { 678 case PIO_COMPLETION_STATUS_OK: 679 if (reg & PIO_ERR_STATUS) { 680 strcomp_status = "COMP_ERR"; 681 ret = -EFAULT; 682 break; 683 } 684 /* Get the read result */ 685 if (val) 686 *val = advk_readl(pcie, PIO_RD_DATA); 687 /* No error */ 688 strcomp_status = NULL; 689 ret = 0; 690 break; 691 case PIO_COMPLETION_STATUS_UR: 692 strcomp_status = "UR"; 693 ret = -EOPNOTSUPP; 694 break; 695 case PIO_COMPLETION_STATUS_CRS: 696 if (allow_crs && val) { 697 /* PCIe r4.0, sec 2.3.2, says: 698 * If CRS Software Visibility is enabled: 699 * For a Configuration Read Request that includes both 700 * bytes of the Vendor ID field of a device Function's 701 * Configuration Space Header, the Root Complex must 702 * complete the Request to the host by returning a 703 * read-data value of 0001h for the Vendor ID field and 704 * all '1's for any additional bytes included in the 705 * request. 706 * 707 * So CRS in this case is not an error status. 708 */ 709 *val = CFG_RD_CRS_VAL; 710 strcomp_status = NULL; 711 ret = 0; 712 break; 713 } 714 /* PCIe r4.0, sec 2.3.2, says: 715 * If CRS Software Visibility is not enabled, the Root Complex 716 * must re-issue the Configuration Request as a new Request. 717 * If CRS Software Visibility is enabled: For a Configuration 718 * Write Request or for any other Configuration Read Request, 719 * the Root Complex must re-issue the Configuration Request as 720 * a new Request. 721 * A Root Complex implementation may choose to limit the number 722 * of Configuration Request/CRS Completion Status loops before 723 * determining that something is wrong with the target of the 724 * Request and taking appropriate action, e.g., complete the 725 * Request to the host as a failed transaction. 726 * 727 * So return -EAGAIN and caller (pci-aardvark.c driver) will 728 * re-issue request again up to the PIO_RETRY_CNT retries. 729 */ 730 strcomp_status = "CRS"; 731 ret = -EAGAIN; 732 break; 733 case PIO_COMPLETION_STATUS_CA: 734 strcomp_status = "CA"; 735 ret = -ECANCELED; 736 break; 737 default: 738 strcomp_status = "Unknown"; 739 ret = -EINVAL; 740 break; 741 } 742 743 if (!strcomp_status) 744 return ret; 745 746 if (reg & PIO_NON_POSTED_REQ) 747 str_posted = "Non-posted"; 748 else 749 str_posted = "Posted"; 750 751 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 752 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 753 754 return ret; 755 } 756 757 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 758 { 759 struct device *dev = &pcie->pdev->dev; 760 int i; 761 762 for (i = 1; i <= PIO_RETRY_CNT; i++) { 763 u32 start, isr; 764 765 start = advk_readl(pcie, PIO_START); 766 isr = advk_readl(pcie, PIO_ISR); 767 if (!start && isr) 768 return i; 769 udelay(PIO_RETRY_DELAY); 770 } 771 772 dev_err(dev, "PIO read/write transfer time out\n"); 773 return -ETIMEDOUT; 774 } 775 776 static pci_bridge_emul_read_status_t 777 advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 778 int reg, u32 *value) 779 { 780 struct advk_pcie *pcie = bridge->data; 781 782 switch (reg) { 783 case PCI_COMMAND: 784 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 785 return PCI_BRIDGE_EMUL_HANDLED; 786 787 case PCI_INTERRUPT_LINE: { 788 /* 789 * From the whole 32bit register we support reading from HW only 790 * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR. 791 * Other bits are retrieved only from emulated config buffer. 792 */ 793 __le32 *cfgspace = (__le32 *)&bridge->conf; 794 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); 795 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) 796 val &= ~(PCI_BRIDGE_CTL_SERR << 16); 797 else 798 val |= PCI_BRIDGE_CTL_SERR << 16; 799 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) 800 val |= PCI_BRIDGE_CTL_BUS_RESET << 16; 801 else 802 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); 803 *value = val; 804 return PCI_BRIDGE_EMUL_HANDLED; 805 } 806 807 default: 808 return PCI_BRIDGE_EMUL_NOT_HANDLED; 809 } 810 } 811 812 static void 813 advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 814 int reg, u32 old, u32 new, u32 mask) 815 { 816 struct advk_pcie *pcie = bridge->data; 817 818 switch (reg) { 819 case PCI_COMMAND: 820 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); 821 break; 822 823 case PCI_INTERRUPT_LINE: 824 /* 825 * According to Figure 6-3: Pseudo Logic Diagram for Error 826 * Message Controls in PCIe base specification, SERR# Enable bit 827 * in Bridge Control register enable receiving of ERR_* messages 828 */ 829 if (mask & (PCI_BRIDGE_CTL_SERR << 16)) { 830 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 831 if (new & (PCI_BRIDGE_CTL_SERR << 16)) 832 val &= ~PCIE_ISR0_ERR_MASK; 833 else 834 val |= PCIE_ISR0_ERR_MASK; 835 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 836 } 837 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { 838 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); 839 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) 840 val |= HOT_RESET_GEN; 841 else 842 val &= ~HOT_RESET_GEN; 843 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); 844 } 845 break; 846 847 default: 848 break; 849 } 850 } 851 852 static pci_bridge_emul_read_status_t 853 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 854 int reg, u32 *value) 855 { 856 struct advk_pcie *pcie = bridge->data; 857 858 859 switch (reg) { 860 case PCI_EXP_SLTCTL: 861 *value = PCI_EXP_SLTSTA_PDS << 16; 862 return PCI_BRIDGE_EMUL_HANDLED; 863 864 /* 865 * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need 866 * to be handled here, because their values are stored in emulated 867 * config space buffer, and we read them from there when needed. 868 */ 869 870 case PCI_EXP_LNKCAP: { 871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 872 /* 873 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. 874 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm 875 * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag. 876 */ 877 val |= PCI_EXP_LNKCAP_DLLLARC; 878 *value = val; 879 return PCI_BRIDGE_EMUL_HANDLED; 880 } 881 882 case PCI_EXP_LNKCTL: { 883 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 885 ~(PCI_EXP_LNKSTA_LT << 16); 886 if (advk_pcie_link_training(pcie)) 887 val |= (PCI_EXP_LNKSTA_LT << 16); 888 if (advk_pcie_link_active(pcie)) 889 val |= (PCI_EXP_LNKSTA_DLLLA << 16); 890 *value = val; 891 return PCI_BRIDGE_EMUL_HANDLED; 892 } 893 894 case PCI_EXP_DEVCAP: 895 case PCI_EXP_DEVCTL: 896 case PCI_EXP_DEVCAP2: 897 case PCI_EXP_DEVCTL2: 898 case PCI_EXP_LNKCAP2: 899 case PCI_EXP_LNKCTL2: 900 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 901 return PCI_BRIDGE_EMUL_HANDLED; 902 903 default: 904 return PCI_BRIDGE_EMUL_NOT_HANDLED; 905 } 906 907 } 908 909 static void 910 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 911 int reg, u32 old, u32 new, u32 mask) 912 { 913 struct advk_pcie *pcie = bridge->data; 914 915 switch (reg) { 916 case PCI_EXP_LNKCTL: 917 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 918 if (new & PCI_EXP_LNKCTL_RL) 919 advk_pcie_wait_for_retrain(pcie); 920 break; 921 922 case PCI_EXP_RTCTL: { 923 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); 924 /* Only emulation of PMEIE and CRSSVE bits is provided */ 925 rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE; 926 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); 927 break; 928 } 929 930 /* 931 * PCI_EXP_RTSTA is also supported, but does not need to be handled 932 * here, because its value is stored in emulated config space buffer, 933 * and we write it there when needed. 934 */ 935 936 case PCI_EXP_DEVCTL: 937 case PCI_EXP_DEVCTL2: 938 case PCI_EXP_LNKCTL2: 939 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 940 break; 941 942 default: 943 break; 944 } 945 } 946 947 static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 948 .read_base = advk_pci_bridge_emul_base_conf_read, 949 .write_base = advk_pci_bridge_emul_base_conf_write, 950 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 951 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 952 }; 953 954 /* 955 * Initialize the configuration space of the PCI-to-PCI bridge 956 * associated with the given PCIe interface. 957 */ 958 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 959 { 960 struct pci_bridge_emul *bridge = &pcie->bridge; 961 962 bridge->conf.vendor = 963 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 964 bridge->conf.device = 965 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 966 bridge->conf.class_revision = 967 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 968 969 /* Support 32 bits I/O addressing */ 970 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 971 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 972 973 /* Support 64 bits memory pref */ 974 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 975 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 976 977 /* Support interrupt A for MSI feature */ 978 bridge->conf.intpin = PCI_INTERRUPT_INTA; 979 980 /* Aardvark HW provides PCIe Capability structure in version 2 */ 981 bridge->pcie_conf.cap = cpu_to_le16(2); 982 983 /* Indicates supports for Completion Retry Status */ 984 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); 985 986 bridge->has_pcie = true; 987 bridge->data = pcie; 988 bridge->ops = &advk_pci_bridge_emul_ops; 989 990 return pci_bridge_emul_init(bridge, 0); 991 } 992 993 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 994 int devfn) 995 { 996 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) 997 return false; 998 999 /* 1000 * If the link goes down after we check for link-up, we have a problem: 1001 * if a PIO request is executed while link-down, the whole controller 1002 * gets stuck in a non-functional state, and even after link comes up 1003 * again, PIO requests won't work anymore, and a reset of the whole PCIe 1004 * controller is needed. Therefore we need to prevent sending PIO 1005 * requests while the link is down. 1006 */ 1007 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) 1008 return false; 1009 1010 return true; 1011 } 1012 1013 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) 1014 { 1015 struct device *dev = &pcie->pdev->dev; 1016 1017 /* 1018 * Trying to start a new PIO transfer when previous has not completed 1019 * cause External Abort on CPU which results in kernel panic: 1020 * 1021 * SError Interrupt on CPU0, code 0xbf000002 -- SError 1022 * Kernel panic - not syncing: Asynchronous SError Interrupt 1023 * 1024 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected 1025 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent 1026 * concurrent calls at the same time. But because PIO transfer may take 1027 * about 1.5s when link is down or card is disconnected, it means that 1028 * advk_pcie_wait_pio() does not always have to wait for completion. 1029 * 1030 * Some versions of ARM Trusted Firmware handles this External Abort at 1031 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: 1032 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 1033 */ 1034 if (advk_readl(pcie, PIO_START)) { 1035 dev_err(dev, "Previous PIO read/write transfer is still running\n"); 1036 return true; 1037 } 1038 1039 return false; 1040 } 1041 1042 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 1043 int where, int size, u32 *val) 1044 { 1045 struct advk_pcie *pcie = bus->sysdata; 1046 int retry_count; 1047 bool allow_crs; 1048 u32 reg; 1049 int ret; 1050 1051 if (!advk_pcie_valid_device(pcie, bus, devfn)) 1052 return PCIBIOS_DEVICE_NOT_FOUND; 1053 1054 if (pci_is_root_bus(bus)) 1055 return pci_bridge_emul_conf_read(&pcie->bridge, where, 1056 size, val); 1057 1058 /* 1059 * Completion Retry Status is possible to return only when reading all 1060 * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and 1061 * CRSSVE flag on Root Bridge is enabled. 1062 */ 1063 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && 1064 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & 1065 PCI_EXP_RTCTL_CRSSVE); 1066 1067 if (advk_pcie_pio_is_running(pcie)) 1068 goto try_crs; 1069 1070 /* Program the control register */ 1071 reg = advk_readl(pcie, PIO_CTRL); 1072 reg &= ~PIO_CTRL_TYPE_MASK; 1073 if (pci_is_root_bus(bus->parent)) 1074 reg |= PCIE_CONFIG_RD_TYPE0; 1075 else 1076 reg |= PCIE_CONFIG_RD_TYPE1; 1077 advk_writel(pcie, reg, PIO_CTRL); 1078 1079 /* Program the address registers */ 1080 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1081 advk_writel(pcie, reg, PIO_ADDR_LS); 1082 advk_writel(pcie, 0, PIO_ADDR_MS); 1083 1084 /* Program the data strobe */ 1085 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 1086 1087 retry_count = 0; 1088 do { 1089 /* Clear PIO DONE ISR and start the transfer */ 1090 advk_writel(pcie, 1, PIO_ISR); 1091 advk_writel(pcie, 1, PIO_START); 1092 1093 ret = advk_pcie_wait_pio(pcie); 1094 if (ret < 0) 1095 goto try_crs; 1096 1097 retry_count += ret; 1098 1099 /* Check PIO status and get the read result */ 1100 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); 1101 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1102 1103 if (ret < 0) 1104 goto fail; 1105 1106 if (size == 1) 1107 *val = (*val >> (8 * (where & 3))) & 0xff; 1108 else if (size == 2) 1109 *val = (*val >> (8 * (where & 3))) & 0xffff; 1110 1111 return PCIBIOS_SUCCESSFUL; 1112 1113 try_crs: 1114 /* 1115 * If it is possible, return Completion Retry Status so that caller 1116 * tries to issue the request again instead of failing. 1117 */ 1118 if (allow_crs) { 1119 *val = CFG_RD_CRS_VAL; 1120 return PCIBIOS_SUCCESSFUL; 1121 } 1122 1123 fail: 1124 *val = 0xffffffff; 1125 return PCIBIOS_SET_FAILED; 1126 } 1127 1128 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 1129 int where, int size, u32 val) 1130 { 1131 struct advk_pcie *pcie = bus->sysdata; 1132 u32 reg; 1133 u32 data_strobe = 0x0; 1134 int retry_count; 1135 int offset; 1136 int ret; 1137 1138 if (!advk_pcie_valid_device(pcie, bus, devfn)) 1139 return PCIBIOS_DEVICE_NOT_FOUND; 1140 1141 if (pci_is_root_bus(bus)) 1142 return pci_bridge_emul_conf_write(&pcie->bridge, where, 1143 size, val); 1144 1145 if (where % size) 1146 return PCIBIOS_SET_FAILED; 1147 1148 if (advk_pcie_pio_is_running(pcie)) 1149 return PCIBIOS_SET_FAILED; 1150 1151 /* Program the control register */ 1152 reg = advk_readl(pcie, PIO_CTRL); 1153 reg &= ~PIO_CTRL_TYPE_MASK; 1154 if (pci_is_root_bus(bus->parent)) 1155 reg |= PCIE_CONFIG_WR_TYPE0; 1156 else 1157 reg |= PCIE_CONFIG_WR_TYPE1; 1158 advk_writel(pcie, reg, PIO_CTRL); 1159 1160 /* Program the address registers */ 1161 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1162 advk_writel(pcie, reg, PIO_ADDR_LS); 1163 advk_writel(pcie, 0, PIO_ADDR_MS); 1164 1165 /* Calculate the write strobe */ 1166 offset = where & 0x3; 1167 reg = val << (8 * offset); 1168 data_strobe = GENMASK(size - 1, 0) << offset; 1169 1170 /* Program the data register */ 1171 advk_writel(pcie, reg, PIO_WR_DATA); 1172 1173 /* Program the data strobe */ 1174 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 1175 1176 retry_count = 0; 1177 do { 1178 /* Clear PIO DONE ISR and start the transfer */ 1179 advk_writel(pcie, 1, PIO_ISR); 1180 advk_writel(pcie, 1, PIO_START); 1181 1182 ret = advk_pcie_wait_pio(pcie); 1183 if (ret < 0) 1184 return PCIBIOS_SET_FAILED; 1185 1186 retry_count += ret; 1187 1188 ret = advk_pcie_check_pio_status(pcie, false, NULL); 1189 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1190 1191 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; 1192 } 1193 1194 static struct pci_ops advk_pcie_ops = { 1195 .read = advk_pcie_rd_conf, 1196 .write = advk_pcie_wr_conf, 1197 }; 1198 1199 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 1200 struct msi_msg *msg) 1201 { 1202 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 1203 phys_addr_t msi_addr = virt_to_phys(pcie); 1204 1205 msg->address_lo = lower_32_bits(msi_addr); 1206 msg->address_hi = upper_32_bits(msi_addr); 1207 msg->data = data->hwirq; 1208 } 1209 1210 static int advk_msi_set_affinity(struct irq_data *irq_data, 1211 const struct cpumask *mask, bool force) 1212 { 1213 return -EINVAL; 1214 } 1215 1216 static void advk_msi_irq_mask(struct irq_data *d) 1217 { 1218 struct advk_pcie *pcie = d->domain->host_data; 1219 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1220 unsigned long flags; 1221 u32 mask; 1222 1223 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); 1224 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1225 mask |= BIT(hwirq); 1226 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); 1227 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); 1228 } 1229 1230 static void advk_msi_irq_unmask(struct irq_data *d) 1231 { 1232 struct advk_pcie *pcie = d->domain->host_data; 1233 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1234 unsigned long flags; 1235 u32 mask; 1236 1237 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); 1238 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1239 mask &= ~BIT(hwirq); 1240 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); 1241 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); 1242 } 1243 1244 static void advk_msi_top_irq_mask(struct irq_data *d) 1245 { 1246 pci_msi_mask_irq(d); 1247 irq_chip_mask_parent(d); 1248 } 1249 1250 static void advk_msi_top_irq_unmask(struct irq_data *d) 1251 { 1252 pci_msi_unmask_irq(d); 1253 irq_chip_unmask_parent(d); 1254 } 1255 1256 static struct irq_chip advk_msi_bottom_irq_chip = { 1257 .name = "MSI", 1258 .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, 1259 .irq_set_affinity = advk_msi_set_affinity, 1260 .irq_mask = advk_msi_irq_mask, 1261 .irq_unmask = advk_msi_irq_unmask, 1262 }; 1263 1264 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 1265 unsigned int virq, 1266 unsigned int nr_irqs, void *args) 1267 { 1268 struct advk_pcie *pcie = domain->host_data; 1269 int hwirq, i; 1270 1271 mutex_lock(&pcie->msi_used_lock); 1272 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, 1273 order_base_2(nr_irqs)); 1274 mutex_unlock(&pcie->msi_used_lock); 1275 if (hwirq < 0) 1276 return -ENOSPC; 1277 1278 for (i = 0; i < nr_irqs; i++) 1279 irq_domain_set_info(domain, virq + i, hwirq + i, 1280 &advk_msi_bottom_irq_chip, 1281 domain->host_data, handle_simple_irq, 1282 NULL, NULL); 1283 1284 return 0; 1285 } 1286 1287 static void advk_msi_irq_domain_free(struct irq_domain *domain, 1288 unsigned int virq, unsigned int nr_irqs) 1289 { 1290 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1291 struct advk_pcie *pcie = domain->host_data; 1292 1293 mutex_lock(&pcie->msi_used_lock); 1294 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); 1295 mutex_unlock(&pcie->msi_used_lock); 1296 } 1297 1298 static const struct irq_domain_ops advk_msi_domain_ops = { 1299 .alloc = advk_msi_irq_domain_alloc, 1300 .free = advk_msi_irq_domain_free, 1301 }; 1302 1303 static void advk_pcie_irq_mask(struct irq_data *d) 1304 { 1305 struct advk_pcie *pcie = d->domain->host_data; 1306 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1307 unsigned long flags; 1308 u32 mask; 1309 1310 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1311 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1312 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 1313 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1314 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1315 } 1316 1317 static void advk_pcie_irq_unmask(struct irq_data *d) 1318 { 1319 struct advk_pcie *pcie = d->domain->host_data; 1320 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1321 unsigned long flags; 1322 u32 mask; 1323 1324 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 1325 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1326 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 1327 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 1328 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 1329 } 1330 1331 static int advk_pcie_irq_map(struct irq_domain *h, 1332 unsigned int virq, irq_hw_number_t hwirq) 1333 { 1334 struct advk_pcie *pcie = h->host_data; 1335 1336 irq_set_status_flags(virq, IRQ_LEVEL); 1337 irq_set_chip_and_handler(virq, &pcie->irq_chip, 1338 handle_level_irq); 1339 irq_set_chip_data(virq, pcie); 1340 1341 return 0; 1342 } 1343 1344 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 1345 .map = advk_pcie_irq_map, 1346 .xlate = irq_domain_xlate_onecell, 1347 }; 1348 1349 static struct irq_chip advk_msi_irq_chip = { 1350 .name = "advk-MSI", 1351 .irq_mask = advk_msi_top_irq_mask, 1352 .irq_unmask = advk_msi_top_irq_unmask, 1353 }; 1354 1355 static struct msi_domain_info advk_msi_domain_info = { 1356 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1357 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 1358 .chip = &advk_msi_irq_chip, 1359 }; 1360 1361 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 1362 { 1363 struct device *dev = &pcie->pdev->dev; 1364 1365 raw_spin_lock_init(&pcie->msi_irq_lock); 1366 mutex_init(&pcie->msi_used_lock); 1367 1368 pcie->msi_inner_domain = 1369 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 1370 &advk_msi_domain_ops, pcie); 1371 if (!pcie->msi_inner_domain) 1372 return -ENOMEM; 1373 1374 pcie->msi_domain = 1375 pci_msi_create_irq_domain(dev_fwnode(dev), 1376 &advk_msi_domain_info, 1377 pcie->msi_inner_domain); 1378 if (!pcie->msi_domain) { 1379 irq_domain_remove(pcie->msi_inner_domain); 1380 return -ENOMEM; 1381 } 1382 1383 return 0; 1384 } 1385 1386 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 1387 { 1388 irq_domain_remove(pcie->msi_domain); 1389 irq_domain_remove(pcie->msi_inner_domain); 1390 } 1391 1392 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 1393 { 1394 struct device *dev = &pcie->pdev->dev; 1395 struct device_node *node = dev->of_node; 1396 struct device_node *pcie_intc_node; 1397 struct irq_chip *irq_chip; 1398 int ret = 0; 1399 1400 raw_spin_lock_init(&pcie->irq_lock); 1401 1402 pcie_intc_node = of_get_next_child(node, NULL); 1403 if (!pcie_intc_node) { 1404 dev_err(dev, "No PCIe Intc node found\n"); 1405 return -ENODEV; 1406 } 1407 1408 irq_chip = &pcie->irq_chip; 1409 1410 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 1411 dev_name(dev)); 1412 if (!irq_chip->name) { 1413 ret = -ENOMEM; 1414 goto out_put_node; 1415 } 1416 1417 irq_chip->irq_mask = advk_pcie_irq_mask; 1418 irq_chip->irq_unmask = advk_pcie_irq_unmask; 1419 1420 pcie->irq_domain = 1421 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 1422 &advk_pcie_irq_domain_ops, pcie); 1423 if (!pcie->irq_domain) { 1424 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 1425 ret = -ENOMEM; 1426 goto out_put_node; 1427 } 1428 1429 out_put_node: 1430 of_node_put(pcie_intc_node); 1431 return ret; 1432 } 1433 1434 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 1435 { 1436 irq_domain_remove(pcie->irq_domain); 1437 } 1438 1439 static struct irq_chip advk_rp_irq_chip = { 1440 .name = "advk-RP", 1441 }; 1442 1443 static int advk_pcie_rp_irq_map(struct irq_domain *h, 1444 unsigned int virq, irq_hw_number_t hwirq) 1445 { 1446 struct advk_pcie *pcie = h->host_data; 1447 1448 irq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq); 1449 irq_set_chip_data(virq, pcie); 1450 1451 return 0; 1452 } 1453 1454 static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = { 1455 .map = advk_pcie_rp_irq_map, 1456 .xlate = irq_domain_xlate_onecell, 1457 }; 1458 1459 static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) 1460 { 1461 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, 1462 &advk_pcie_rp_irq_domain_ops, 1463 pcie); 1464 if (!pcie->rp_irq_domain) { 1465 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); 1466 return -ENOMEM; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) 1473 { 1474 irq_domain_remove(pcie->rp_irq_domain); 1475 } 1476 1477 static void advk_pcie_handle_pme(struct advk_pcie *pcie) 1478 { 1479 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; 1480 1481 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); 1482 1483 /* 1484 * PCIE_MSG_LOG_REG contains the last inbound message, so store 1485 * the requester ID only when PME was not asserted yet. 1486 * Also do not trigger PME interrupt when PME is still asserted. 1487 */ 1488 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { 1489 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); 1490 1491 /* 1492 * Trigger PME interrupt only if PMEIE bit in Root Control is set. 1493 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. 1494 */ 1495 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) 1496 return; 1497 1498 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) 1499 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); 1500 } 1501 } 1502 1503 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 1504 { 1505 u32 msi_val, msi_mask, msi_status, msi_idx; 1506 1507 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 1508 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 1509 msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK); 1510 1511 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 1512 if (!(BIT(msi_idx) & msi_status)) 1513 continue; 1514 1515 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 1516 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) 1517 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); 1518 } 1519 1520 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 1521 PCIE_ISR0_REG); 1522 } 1523 1524 static void advk_pcie_handle_int(struct advk_pcie *pcie) 1525 { 1526 u32 isr0_val, isr0_mask, isr0_status; 1527 u32 isr1_val, isr1_mask, isr1_status; 1528 int i; 1529 1530 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 1531 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 1532 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 1533 1534 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 1535 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1536 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 1537 1538 /* Process PME interrupt as the first one to do not miss PME requester id */ 1539 if (isr0_status & PCIE_MSG_PM_PME_MASK) 1540 advk_pcie_handle_pme(pcie); 1541 1542 /* Process ERR interrupt */ 1543 if (isr0_status & PCIE_ISR0_ERR_MASK) { 1544 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); 1545 1546 /* 1547 * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use 1548 * PCIe interrupt 0 1549 */ 1550 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) 1551 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); 1552 } 1553 1554 /* Process MSI interrupts */ 1555 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 1556 advk_pcie_handle_msi(pcie); 1557 1558 /* Process legacy interrupts */ 1559 for (i = 0; i < PCI_NUM_INTX; i++) { 1560 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 1561 continue; 1562 1563 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 1564 PCIE_ISR1_REG); 1565 1566 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) 1567 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", 1568 (char)i + 'A'); 1569 } 1570 } 1571 1572 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 1573 { 1574 struct advk_pcie *pcie = arg; 1575 u32 status; 1576 1577 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 1578 if (!(status & PCIE_IRQ_CORE_INT)) 1579 return IRQ_NONE; 1580 1581 advk_pcie_handle_int(pcie); 1582 1583 /* Clear interrupt */ 1584 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 1585 1586 return IRQ_HANDLED; 1587 } 1588 1589 static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1590 { 1591 struct advk_pcie *pcie = dev->bus->sysdata; 1592 1593 /* 1594 * Emulated root bridge has its own emulated irq chip and irq domain. 1595 * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and 1596 * hwirq for irq_create_mapping() is indexed from zero. 1597 */ 1598 if (pci_is_root_bus(dev->bus)) 1599 return irq_create_mapping(pcie->rp_irq_domain, pin - 1); 1600 else 1601 return of_irq_parse_and_map_pci(dev, slot, pin); 1602 } 1603 1604 static void advk_pcie_disable_phy(struct advk_pcie *pcie) 1605 { 1606 phy_power_off(pcie->phy); 1607 phy_exit(pcie->phy); 1608 } 1609 1610 static int advk_pcie_enable_phy(struct advk_pcie *pcie) 1611 { 1612 int ret; 1613 1614 if (!pcie->phy) 1615 return 0; 1616 1617 ret = phy_init(pcie->phy); 1618 if (ret) 1619 return ret; 1620 1621 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); 1622 if (ret) { 1623 phy_exit(pcie->phy); 1624 return ret; 1625 } 1626 1627 ret = phy_power_on(pcie->phy); 1628 if (ret) { 1629 phy_exit(pcie->phy); 1630 return ret; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int advk_pcie_setup_phy(struct advk_pcie *pcie) 1637 { 1638 struct device *dev = &pcie->pdev->dev; 1639 struct device_node *node = dev->of_node; 1640 int ret = 0; 1641 1642 pcie->phy = devm_of_phy_get(dev, node, NULL); 1643 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) 1644 return PTR_ERR(pcie->phy); 1645 1646 /* Old bindings miss the PHY handle */ 1647 if (IS_ERR(pcie->phy)) { 1648 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); 1649 pcie->phy = NULL; 1650 return 0; 1651 } 1652 1653 ret = advk_pcie_enable_phy(pcie); 1654 if (ret) 1655 dev_err(dev, "Failed to initialize PHY (%d)\n", ret); 1656 1657 return ret; 1658 } 1659 1660 static int advk_pcie_probe(struct platform_device *pdev) 1661 { 1662 struct device *dev = &pdev->dev; 1663 struct advk_pcie *pcie; 1664 struct pci_host_bridge *bridge; 1665 struct resource_entry *entry; 1666 int ret, irq; 1667 1668 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 1669 if (!bridge) 1670 return -ENOMEM; 1671 1672 pcie = pci_host_bridge_priv(bridge); 1673 pcie->pdev = pdev; 1674 platform_set_drvdata(pdev, pcie); 1675 1676 resource_list_for_each_entry(entry, &bridge->windows) { 1677 resource_size_t start = entry->res->start; 1678 resource_size_t size = resource_size(entry->res); 1679 unsigned long type = resource_type(entry->res); 1680 u64 win_size; 1681 1682 /* 1683 * Aardvark hardware allows to configure also PCIe window 1684 * for config type 0 and type 1 mapping, but driver uses 1685 * only PIO for issuing configuration transfers which does 1686 * not use PCIe window configuration. 1687 */ 1688 if (type != IORESOURCE_MEM && type != IORESOURCE_IO) 1689 continue; 1690 1691 /* 1692 * Skip transparent memory resources. Default outbound access 1693 * configuration is set to transparent memory access so it 1694 * does not need window configuration. 1695 */ 1696 if (type == IORESOURCE_MEM && entry->offset == 0) 1697 continue; 1698 1699 /* 1700 * The n-th PCIe window is configured by tuple (match, remap, mask) 1701 * and an access to address A uses this window if A matches the 1702 * match with given mask. 1703 * So every PCIe window size must be a power of two and every start 1704 * address must be aligned to window size. Minimal size is 64 KiB 1705 * because lower 16 bits of mask must be zero. Remapped address 1706 * may have set only bits from the mask. 1707 */ 1708 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { 1709 /* Calculate the largest aligned window size */ 1710 win_size = (1ULL << (fls64(size)-1)) | 1711 (start ? (1ULL << __ffs64(start)) : 0); 1712 win_size = 1ULL << __ffs64(win_size); 1713 if (win_size < 0x10000) 1714 break; 1715 1716 dev_dbg(dev, 1717 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", 1718 pcie->wins_count, (unsigned long long)start, 1719 (unsigned long long)start + win_size, type); 1720 1721 if (type == IORESOURCE_IO) { 1722 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; 1723 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); 1724 } else { 1725 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; 1726 pcie->wins[pcie->wins_count].match = start; 1727 } 1728 pcie->wins[pcie->wins_count].remap = start - entry->offset; 1729 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); 1730 1731 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) 1732 break; 1733 1734 start += win_size; 1735 size -= win_size; 1736 pcie->wins_count++; 1737 } 1738 1739 if (size > 0) { 1740 dev_err(&pcie->pdev->dev, 1741 "Invalid PCIe region [0x%llx-0x%llx]\n", 1742 (unsigned long long)entry->res->start, 1743 (unsigned long long)entry->res->end + 1); 1744 return -EINVAL; 1745 } 1746 } 1747 1748 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1749 if (IS_ERR(pcie->base)) 1750 return PTR_ERR(pcie->base); 1751 1752 irq = platform_get_irq(pdev, 0); 1753 if (irq < 0) 1754 return irq; 1755 1756 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 1757 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 1758 pcie); 1759 if (ret) { 1760 dev_err(dev, "Failed to register interrupt\n"); 1761 return ret; 1762 } 1763 1764 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, 1765 "reset-gpios", 0, 1766 GPIOD_OUT_LOW, 1767 "pcie1-reset"); 1768 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); 1769 if (ret) { 1770 if (ret == -ENOENT) { 1771 pcie->reset_gpio = NULL; 1772 } else { 1773 if (ret != -EPROBE_DEFER) 1774 dev_err(dev, "Failed to get reset-gpio: %i\n", 1775 ret); 1776 return ret; 1777 } 1778 } 1779 1780 ret = of_pci_get_max_link_speed(dev->of_node); 1781 if (ret <= 0 || ret > 3) 1782 pcie->link_gen = 3; 1783 else 1784 pcie->link_gen = ret; 1785 1786 ret = advk_pcie_setup_phy(pcie); 1787 if (ret) 1788 return ret; 1789 1790 advk_pcie_setup_hw(pcie); 1791 1792 ret = advk_sw_pci_bridge_init(pcie); 1793 if (ret) { 1794 dev_err(dev, "Failed to register emulated root PCI bridge\n"); 1795 return ret; 1796 } 1797 1798 ret = advk_pcie_init_irq_domain(pcie); 1799 if (ret) { 1800 dev_err(dev, "Failed to initialize irq\n"); 1801 return ret; 1802 } 1803 1804 ret = advk_pcie_init_msi_irq_domain(pcie); 1805 if (ret) { 1806 dev_err(dev, "Failed to initialize irq\n"); 1807 advk_pcie_remove_irq_domain(pcie); 1808 return ret; 1809 } 1810 1811 ret = advk_pcie_init_rp_irq_domain(pcie); 1812 if (ret) { 1813 dev_err(dev, "Failed to initialize irq\n"); 1814 advk_pcie_remove_msi_irq_domain(pcie); 1815 advk_pcie_remove_irq_domain(pcie); 1816 return ret; 1817 } 1818 1819 bridge->sysdata = pcie; 1820 bridge->ops = &advk_pcie_ops; 1821 bridge->map_irq = advk_pcie_map_irq; 1822 1823 ret = pci_host_probe(bridge); 1824 if (ret < 0) { 1825 advk_pcie_remove_rp_irq_domain(pcie); 1826 advk_pcie_remove_msi_irq_domain(pcie); 1827 advk_pcie_remove_irq_domain(pcie); 1828 return ret; 1829 } 1830 1831 return 0; 1832 } 1833 1834 static int advk_pcie_remove(struct platform_device *pdev) 1835 { 1836 struct advk_pcie *pcie = platform_get_drvdata(pdev); 1837 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1838 u32 val; 1839 int i; 1840 1841 /* Remove PCI bus with all devices */ 1842 pci_lock_rescan_remove(); 1843 pci_stop_root_bus(bridge->bus); 1844 pci_remove_root_bus(bridge->bus); 1845 pci_unlock_rescan_remove(); 1846 1847 /* Disable Root Bridge I/O space, memory space and bus mastering */ 1848 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 1849 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 1850 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); 1851 1852 /* Disable MSI */ 1853 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 1854 val &= ~PCIE_CORE_CTRL2_MSI_ENABLE; 1855 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); 1856 1857 /* Clear MSI address */ 1858 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); 1859 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); 1860 1861 /* Mask all interrupts */ 1862 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); 1863 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); 1864 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 1865 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); 1866 1867 /* Clear all interrupts */ 1868 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); 1869 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 1870 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 1871 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 1872 1873 /* Remove IRQ domains */ 1874 advk_pcie_remove_rp_irq_domain(pcie); 1875 advk_pcie_remove_msi_irq_domain(pcie); 1876 advk_pcie_remove_irq_domain(pcie); 1877 1878 /* Free config space for emulated root bridge */ 1879 pci_bridge_emul_cleanup(&pcie->bridge); 1880 1881 /* Assert PERST# signal which prepares PCIe card for power down */ 1882 if (pcie->reset_gpio) 1883 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 1884 1885 /* Disable link training */ 1886 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 1887 val &= ~LINK_TRAINING_EN; 1888 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); 1889 1890 /* Disable outbound address windows mapping */ 1891 for (i = 0; i < OB_WIN_COUNT; i++) 1892 advk_pcie_disable_ob_win(pcie, i); 1893 1894 /* Disable phy */ 1895 advk_pcie_disable_phy(pcie); 1896 1897 return 0; 1898 } 1899 1900 static const struct of_device_id advk_pcie_of_match_table[] = { 1901 { .compatible = "marvell,armada-3700-pcie", }, 1902 {}, 1903 }; 1904 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table); 1905 1906 static struct platform_driver advk_pcie_driver = { 1907 .driver = { 1908 .name = "advk-pcie", 1909 .of_match_table = advk_pcie_of_match_table, 1910 }, 1911 .probe = advk_pcie_probe, 1912 .remove = advk_pcie_remove, 1913 }; 1914 module_platform_driver(advk_pcie_driver); 1915 1916 MODULE_DESCRIPTION("Aardvark PCIe controller"); 1917 MODULE_LICENSE("GPL v2"); 1918