1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Mobiveil PCIe Host controller 4 * 5 * Copyright (c) 2018 Mobiveil Inc. 6 * Copyright 2019-2020 NXP 7 * 8 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> 9 * Hou Zhiqiang <Zhiqiang.Hou@nxp.com> 10 */ 11 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/msi.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 28 #include "pcie-mobiveil.h" 29 30 static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) 31 { 32 struct mobiveil_pcie *pcie = bus->sysdata; 33 struct mobiveil_root_port *rp = &pcie->rp; 34 35 /* Only one device down on each root port */ 36 if ((bus->number == rp->root_bus_nr) && (devfn > 0)) 37 return false; 38 39 /* 40 * Do not read more than one device on the bus directly 41 * attached to RC 42 */ 43 if ((bus->primary == rp->root_bus_nr) && (PCI_SLOT(devfn) > 0)) 44 return false; 45 46 return true; 47 } 48 49 /* 50 * mobiveil_pcie_map_bus - routine to get the configuration base of either 51 * root port or endpoint 52 */ 53 static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, 54 unsigned int devfn, int where) 55 { 56 struct mobiveil_pcie *pcie = bus->sysdata; 57 struct mobiveil_root_port *rp = &pcie->rp; 58 u32 value; 59 60 if (!mobiveil_pcie_valid_device(bus, devfn)) 61 return NULL; 62 63 /* RC config access */ 64 if (bus->number == rp->root_bus_nr) 65 return pcie->csr_axi_slave_base + where; 66 67 /* 68 * EP config access (in Config/APIO space) 69 * Program PEX Address base (31..16 bits) with appropriate value 70 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register. 71 * Relies on pci_lock serialization 72 */ 73 value = bus->number << PAB_BUS_SHIFT | 74 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT | 75 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT; 76 77 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); 78 79 return rp->config_axi_slave_base + where; 80 } 81 82 static struct pci_ops mobiveil_pcie_ops = { 83 .map_bus = mobiveil_pcie_map_bus, 84 .read = pci_generic_config_read, 85 .write = pci_generic_config_write, 86 }; 87 88 static void mobiveil_pcie_isr(struct irq_desc *desc) 89 { 90 struct irq_chip *chip = irq_desc_get_chip(desc); 91 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); 92 struct device *dev = &pcie->pdev->dev; 93 struct mobiveil_root_port *rp = &pcie->rp; 94 struct mobiveil_msi *msi = &rp->msi; 95 u32 msi_data, msi_addr_lo, msi_addr_hi; 96 u32 intr_status, msi_status; 97 unsigned long shifted_status; 98 u32 bit, virq, val, mask; 99 100 /* 101 * The core provides a single interrupt for both INTx/MSI messages. 102 * So we'll read both INTx and MSI status 103 */ 104 105 chained_irq_enter(chip, desc); 106 107 /* read INTx status */ 108 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); 109 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); 110 intr_status = val & mask; 111 112 /* Handle INTx */ 113 if (intr_status & PAB_INTP_INTX_MASK) { 114 shifted_status = mobiveil_csr_readl(pcie, 115 PAB_INTP_AMBA_MISC_STAT); 116 shifted_status &= PAB_INTP_INTX_MASK; 117 shifted_status >>= PAB_INTX_START; 118 do { 119 for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { 120 virq = irq_find_mapping(rp->intx_domain, 121 bit + 1); 122 if (virq) 123 generic_handle_irq(virq); 124 else 125 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", 126 bit); 127 128 /* clear interrupt handled */ 129 mobiveil_csr_writel(pcie, 130 1 << (PAB_INTX_START + bit), 131 PAB_INTP_AMBA_MISC_STAT); 132 } 133 134 shifted_status = mobiveil_csr_readl(pcie, 135 PAB_INTP_AMBA_MISC_STAT); 136 shifted_status &= PAB_INTP_INTX_MASK; 137 shifted_status >>= PAB_INTX_START; 138 } while (shifted_status != 0); 139 } 140 141 /* read extra MSI status register */ 142 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); 143 144 /* handle MSI interrupts */ 145 while (msi_status & 1) { 146 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); 147 148 /* 149 * MSI_STATUS_OFFSET register gets updated to zero 150 * once we pop not only the MSI data but also address 151 * from MSI hardware FIFO. So keeping these following 152 * two dummy reads. 153 */ 154 msi_addr_lo = readl_relaxed(pcie->apb_csr_base + 155 MSI_ADDR_L_OFFSET); 156 msi_addr_hi = readl_relaxed(pcie->apb_csr_base + 157 MSI_ADDR_H_OFFSET); 158 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", 159 msi_data, msi_addr_hi, msi_addr_lo); 160 161 virq = irq_find_mapping(msi->dev_domain, msi_data); 162 if (virq) 163 generic_handle_irq(virq); 164 165 msi_status = readl_relaxed(pcie->apb_csr_base + 166 MSI_STATUS_OFFSET); 167 } 168 169 /* Clear the interrupt status */ 170 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT); 171 chained_irq_exit(chip, desc); 172 } 173 174 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) 175 { 176 struct device *dev = &pcie->pdev->dev; 177 struct platform_device *pdev = pcie->pdev; 178 struct device_node *node = dev->of_node; 179 struct mobiveil_root_port *rp = &pcie->rp; 180 struct resource *res; 181 182 /* map config resource */ 183 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 184 "config_axi_slave"); 185 rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); 186 if (IS_ERR(rp->config_axi_slave_base)) 187 return PTR_ERR(rp->config_axi_slave_base); 188 rp->ob_io_res = res; 189 190 /* map csr resource */ 191 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 192 "csr_axi_slave"); 193 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); 194 if (IS_ERR(pcie->csr_axi_slave_base)) 195 return PTR_ERR(pcie->csr_axi_slave_base); 196 pcie->pcie_reg_base = res->start; 197 198 /* read the number of windows requested */ 199 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) 200 pcie->apio_wins = MAX_PIO_WINDOWS; 201 202 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) 203 pcie->ppio_wins = MAX_PIO_WINDOWS; 204 205 return 0; 206 } 207 208 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) 209 { 210 phys_addr_t msg_addr = pcie->pcie_reg_base; 211 struct mobiveil_msi *msi = &pcie->rp.msi; 212 213 msi->num_of_vectors = PCI_NUM_MSI; 214 msi->msi_pages_phys = (phys_addr_t)msg_addr; 215 216 writel_relaxed(lower_32_bits(msg_addr), 217 pcie->apb_csr_base + MSI_BASE_LO_OFFSET); 218 writel_relaxed(upper_32_bits(msg_addr), 219 pcie->apb_csr_base + MSI_BASE_HI_OFFSET); 220 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); 221 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); 222 } 223 224 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) 225 { 226 struct mobiveil_root_port *rp = &pcie->rp; 227 struct pci_host_bridge *bridge = rp->bridge; 228 u32 value, pab_ctrl, type; 229 struct resource_entry *win; 230 231 pcie->ib_wins_configured = 0; 232 pcie->ob_wins_configured = 0; 233 234 if (!reinit) { 235 /* setup bus numbers */ 236 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); 237 value &= 0xff000000; 238 value |= 0x00ff0100; 239 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); 240 } 241 242 /* 243 * program Bus Master Enable Bit in Command Register in PAB Config 244 * Space 245 */ 246 value = mobiveil_csr_readl(pcie, PCI_COMMAND); 247 value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 248 mobiveil_csr_writel(pcie, value, PCI_COMMAND); 249 250 /* 251 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL 252 * register 253 */ 254 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL); 255 pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); 256 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); 257 258 /* 259 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in 260 * PAB_AXI_PIO_CTRL Register 261 */ 262 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL); 263 value |= APIO_EN_MASK; 264 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL); 265 266 /* Enable PCIe PIO master */ 267 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL); 268 value |= 1 << PIO_ENABLE_SHIFT; 269 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL); 270 271 /* 272 * we'll program one outbound window for config reads and 273 * another default inbound window for all the upstream traffic 274 * rest of the outbound windows will be configured according to 275 * the "ranges" field defined in device tree 276 */ 277 278 /* config outbound translation window */ 279 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, 280 CFG_WINDOW_TYPE, resource_size(rp->ob_io_res)); 281 282 /* memory inbound translation window */ 283 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); 284 285 /* Get the I/O and memory ranges from DT */ 286 resource_list_for_each_entry(win, &bridge->windows) { 287 if (resource_type(win->res) == IORESOURCE_MEM) 288 type = MEM_WINDOW_TYPE; 289 else if (resource_type(win->res) == IORESOURCE_IO) 290 type = IO_WINDOW_TYPE; 291 else 292 continue; 293 294 /* configure outbound translation window */ 295 program_ob_windows(pcie, pcie->ob_wins_configured, 296 win->res->start, 297 win->res->start - win->offset, 298 type, resource_size(win->res)); 299 } 300 301 /* fixup for PCIe class register */ 302 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); 303 value &= 0xff; 304 value |= (PCI_CLASS_BRIDGE_PCI << 16); 305 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); 306 307 return 0; 308 } 309 310 static void mobiveil_mask_intx_irq(struct irq_data *data) 311 { 312 struct irq_desc *desc = irq_to_desc(data->irq); 313 struct mobiveil_pcie *pcie; 314 struct mobiveil_root_port *rp; 315 unsigned long flags; 316 u32 mask, shifted_val; 317 318 pcie = irq_desc_get_chip_data(desc); 319 rp = &pcie->rp; 320 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); 321 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); 322 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); 323 shifted_val &= ~mask; 324 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); 325 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); 326 } 327 328 static void mobiveil_unmask_intx_irq(struct irq_data *data) 329 { 330 struct irq_desc *desc = irq_to_desc(data->irq); 331 struct mobiveil_pcie *pcie; 332 struct mobiveil_root_port *rp; 333 unsigned long flags; 334 u32 shifted_val, mask; 335 336 pcie = irq_desc_get_chip_data(desc); 337 rp = &pcie->rp; 338 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); 339 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); 340 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); 341 shifted_val |= mask; 342 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); 343 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); 344 } 345 346 static struct irq_chip intx_irq_chip = { 347 .name = "mobiveil_pcie:intx", 348 .irq_enable = mobiveil_unmask_intx_irq, 349 .irq_disable = mobiveil_mask_intx_irq, 350 .irq_mask = mobiveil_mask_intx_irq, 351 .irq_unmask = mobiveil_unmask_intx_irq, 352 }; 353 354 /* routine to setup the INTx related data */ 355 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 356 irq_hw_number_t hwirq) 357 { 358 irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq); 359 irq_set_chip_data(irq, domain->host_data); 360 361 return 0; 362 } 363 364 /* INTx domain operations structure */ 365 static const struct irq_domain_ops intx_domain_ops = { 366 .map = mobiveil_pcie_intx_map, 367 }; 368 369 static struct irq_chip mobiveil_msi_irq_chip = { 370 .name = "Mobiveil PCIe MSI", 371 .irq_mask = pci_msi_mask_irq, 372 .irq_unmask = pci_msi_unmask_irq, 373 }; 374 375 static struct msi_domain_info mobiveil_msi_domain_info = { 376 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 377 MSI_FLAG_PCI_MSIX), 378 .chip = &mobiveil_msi_irq_chip, 379 }; 380 381 static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 382 { 383 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); 384 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); 385 386 msg->address_lo = lower_32_bits(addr); 387 msg->address_hi = upper_32_bits(addr); 388 msg->data = data->hwirq; 389 390 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", 391 (int)data->hwirq, msg->address_hi, msg->address_lo); 392 } 393 394 static int mobiveil_msi_set_affinity(struct irq_data *irq_data, 395 const struct cpumask *mask, bool force) 396 { 397 return -EINVAL; 398 } 399 400 static struct irq_chip mobiveil_msi_bottom_irq_chip = { 401 .name = "Mobiveil MSI", 402 .irq_compose_msi_msg = mobiveil_compose_msi_msg, 403 .irq_set_affinity = mobiveil_msi_set_affinity, 404 }; 405 406 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, 407 unsigned int virq, 408 unsigned int nr_irqs, void *args) 409 { 410 struct mobiveil_pcie *pcie = domain->host_data; 411 struct mobiveil_msi *msi = &pcie->rp.msi; 412 unsigned long bit; 413 414 WARN_ON(nr_irqs != 1); 415 mutex_lock(&msi->lock); 416 417 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); 418 if (bit >= msi->num_of_vectors) { 419 mutex_unlock(&msi->lock); 420 return -ENOSPC; 421 } 422 423 set_bit(bit, msi->msi_irq_in_use); 424 425 mutex_unlock(&msi->lock); 426 427 irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip, 428 domain->host_data, handle_level_irq, NULL, NULL); 429 return 0; 430 } 431 432 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, 433 unsigned int virq, 434 unsigned int nr_irqs) 435 { 436 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 437 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); 438 struct mobiveil_msi *msi = &pcie->rp.msi; 439 440 mutex_lock(&msi->lock); 441 442 if (!test_bit(d->hwirq, msi->msi_irq_in_use)) 443 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", 444 d->hwirq); 445 else 446 __clear_bit(d->hwirq, msi->msi_irq_in_use); 447 448 mutex_unlock(&msi->lock); 449 } 450 static const struct irq_domain_ops msi_domain_ops = { 451 .alloc = mobiveil_irq_msi_domain_alloc, 452 .free = mobiveil_irq_msi_domain_free, 453 }; 454 455 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) 456 { 457 struct device *dev = &pcie->pdev->dev; 458 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 459 struct mobiveil_msi *msi = &pcie->rp.msi; 460 461 mutex_init(&msi->lock); 462 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, 463 &msi_domain_ops, pcie); 464 if (!msi->dev_domain) { 465 dev_err(dev, "failed to create IRQ domain\n"); 466 return -ENOMEM; 467 } 468 469 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 470 &mobiveil_msi_domain_info, 471 msi->dev_domain); 472 if (!msi->msi_domain) { 473 dev_err(dev, "failed to create MSI domain\n"); 474 irq_domain_remove(msi->dev_domain); 475 return -ENOMEM; 476 } 477 478 return 0; 479 } 480 481 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) 482 { 483 struct device *dev = &pcie->pdev->dev; 484 struct device_node *node = dev->of_node; 485 struct mobiveil_root_port *rp = &pcie->rp; 486 int ret; 487 488 /* setup INTx */ 489 rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, 490 &intx_domain_ops, pcie); 491 492 if (!rp->intx_domain) { 493 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 494 return -ENOMEM; 495 } 496 497 raw_spin_lock_init(&rp->intx_mask_lock); 498 499 /* setup MSI */ 500 ret = mobiveil_allocate_msi_domains(pcie); 501 if (ret) 502 return ret; 503 504 return 0; 505 } 506 507 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie) 508 { 509 struct platform_device *pdev = pcie->pdev; 510 struct device *dev = &pdev->dev; 511 struct mobiveil_root_port *rp = &pcie->rp; 512 struct resource *res; 513 int ret; 514 515 /* map MSI config resource */ 516 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); 517 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); 518 if (IS_ERR(pcie->apb_csr_base)) 519 return PTR_ERR(pcie->apb_csr_base); 520 521 /* setup MSI hardware registers */ 522 mobiveil_pcie_enable_msi(pcie); 523 524 rp->irq = platform_get_irq(pdev, 0); 525 if (rp->irq <= 0) { 526 dev_err(dev, "failed to map IRQ: %d\n", rp->irq); 527 return -ENODEV; 528 } 529 530 /* initialize the IRQ domains */ 531 ret = mobiveil_pcie_init_irq_domain(pcie); 532 if (ret) { 533 dev_err(dev, "Failed creating IRQ Domain\n"); 534 return ret; 535 } 536 537 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); 538 539 /* Enable interrupts */ 540 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), 541 PAB_INTP_AMBA_MISC_ENB); 542 543 544 return 0; 545 } 546 547 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) 548 { 549 struct mobiveil_root_port *rp = &pcie->rp; 550 551 if (rp->ops->interrupt_init) 552 return rp->ops->interrupt_init(pcie); 553 554 return mobiveil_pcie_integrated_interrupt_init(pcie); 555 } 556 557 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie) 558 { 559 u32 header_type; 560 561 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE); 562 header_type &= 0x7f; 563 564 return header_type == PCI_HEADER_TYPE_BRIDGE; 565 } 566 567 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) 568 { 569 struct mobiveil_root_port *rp = &pcie->rp; 570 struct pci_host_bridge *bridge = rp->bridge; 571 struct device *dev = &pcie->pdev->dev; 572 struct pci_bus *bus; 573 struct pci_bus *child; 574 int ret; 575 576 ret = mobiveil_pcie_parse_dt(pcie); 577 if (ret) { 578 dev_err(dev, "Parsing DT failed, ret: %x\n", ret); 579 return ret; 580 } 581 582 if (!mobiveil_pcie_is_bridge(pcie)) 583 return -ENODEV; 584 585 /* parse the host bridge base addresses from the device tree file */ 586 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, 587 &bridge->dma_ranges, NULL); 588 if (ret) { 589 dev_err(dev, "Getting bridge resources failed\n"); 590 return ret; 591 } 592 593 /* 594 * configure all inbound and outbound windows and prepare the RC for 595 * config access 596 */ 597 ret = mobiveil_host_init(pcie, false); 598 if (ret) { 599 dev_err(dev, "Failed to initialize host\n"); 600 return ret; 601 } 602 603 ret = mobiveil_pcie_interrupt_init(pcie); 604 if (ret) { 605 dev_err(dev, "Interrupt init failed\n"); 606 return ret; 607 } 608 609 /* Initialize bridge */ 610 bridge->dev.parent = dev; 611 bridge->sysdata = pcie; 612 bridge->busnr = rp->root_bus_nr; 613 bridge->ops = &mobiveil_pcie_ops; 614 bridge->map_irq = of_irq_parse_and_map_pci; 615 bridge->swizzle_irq = pci_common_swizzle; 616 617 ret = mobiveil_bringup_link(pcie); 618 if (ret) { 619 dev_info(dev, "link bring-up failed\n"); 620 return ret; 621 } 622 623 /* setup the kernel resources for the newly added PCIe root bus */ 624 ret = pci_scan_root_bus_bridge(bridge); 625 if (ret) 626 return ret; 627 628 bus = bridge->bus; 629 630 pci_assign_unassigned_bus_resources(bus); 631 list_for_each_entry(child, &bus->children, node) 632 pcie_bus_configure_settings(child); 633 pci_bus_add_devices(bus); 634 635 return 0; 636 } 637