1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * PCIe host controller driver for UniPhier SoCs
4  * Copyright 2018 Socionext Inc.
5  * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
6  */
7 
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/of_irq.h>
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 
23 #include "pcie-designware.h"
24 
25 #define PCL_PINCTRL0			0x002c
26 #define PCL_PERST_PLDN_REGEN		BIT(12)
27 #define PCL_PERST_NOE_REGEN		BIT(11)
28 #define PCL_PERST_OUT_REGEN		BIT(8)
29 #define PCL_PERST_PLDN_REGVAL		BIT(4)
30 #define PCL_PERST_NOE_REGVAL		BIT(3)
31 #define PCL_PERST_OUT_REGVAL		BIT(0)
32 
33 #define PCL_PIPEMON			0x0044
34 #define PCL_PCLK_ALIVE			BIT(15)
35 
36 #define PCL_MODE			0x8000
37 #define PCL_MODE_REGEN			BIT(8)
38 #define PCL_MODE_REGVAL			BIT(0)
39 
40 #define PCL_APP_READY_CTRL		0x8008
41 #define PCL_APP_LTSSM_ENABLE		BIT(0)
42 
43 #define PCL_APP_PM0			0x8078
44 #define PCL_SYS_AUX_PWR_DET		BIT(8)
45 
46 #define PCL_RCV_INT			0x8108
47 #define PCL_RCV_INT_ALL_ENABLE		GENMASK(20, 17)
48 #define PCL_CFG_BW_MGT_STATUS		BIT(4)
49 #define PCL_CFG_LINK_AUTO_BW_STATUS	BIT(3)
50 #define PCL_CFG_AER_RC_ERR_MSI_STATUS	BIT(2)
51 #define PCL_CFG_PME_MSI_STATUS		BIT(1)
52 
53 #define PCL_RCV_INTX			0x810c
54 #define PCL_RCV_INTX_ALL_ENABLE		GENMASK(19, 16)
55 #define PCL_RCV_INTX_ALL_MASK		GENMASK(11, 8)
56 #define PCL_RCV_INTX_MASK_SHIFT		8
57 #define PCL_RCV_INTX_ALL_STATUS		GENMASK(3, 0)
58 #define PCL_RCV_INTX_STATUS_SHIFT	0
59 
60 #define PCL_STATUS_LINK			0x8140
61 #define PCL_RDLH_LINK_UP		BIT(1)
62 #define PCL_XMLH_LINK_UP		BIT(0)
63 
64 struct uniphier_pcie_priv {
65 	void __iomem *base;
66 	struct dw_pcie pci;
67 	struct clk *clk;
68 	struct reset_control *rst;
69 	struct phy *phy;
70 	struct irq_domain *legacy_irq_domain;
71 };
72 
73 #define to_uniphier_pcie(x)	dev_get_drvdata((x)->dev)
74 
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
76 				       bool enable)
77 {
78 	u32 val;
79 
80 	val = readl(priv->base + PCL_APP_READY_CTRL);
81 	if (enable)
82 		val |= PCL_APP_LTSSM_ENABLE;
83 	else
84 		val &= ~PCL_APP_LTSSM_ENABLE;
85 	writel(val, priv->base + PCL_APP_READY_CTRL);
86 }
87 
88 static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
89 {
90 	u32 val;
91 
92 	/* set RC MODE */
93 	val = readl(priv->base + PCL_MODE);
94 	val |= PCL_MODE_REGEN;
95 	val &= ~PCL_MODE_REGVAL;
96 	writel(val, priv->base + PCL_MODE);
97 
98 	/* use auxiliary power detection */
99 	val = readl(priv->base + PCL_APP_PM0);
100 	val |= PCL_SYS_AUX_PWR_DET;
101 	writel(val, priv->base + PCL_APP_PM0);
102 
103 	/* assert PERST# */
104 	val = readl(priv->base + PCL_PINCTRL0);
105 	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
106 		 | PCL_PERST_PLDN_REGVAL);
107 	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
108 		| PCL_PERST_PLDN_REGEN;
109 	writel(val, priv->base + PCL_PINCTRL0);
110 
111 	uniphier_pcie_ltssm_enable(priv, false);
112 
113 	usleep_range(100000, 200000);
114 
115 	/* deassert PERST# */
116 	val = readl(priv->base + PCL_PINCTRL0);
117 	val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 	writel(val, priv->base + PCL_PINCTRL0);
119 }
120 
121 static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
122 {
123 	u32 status;
124 	int ret;
125 
126 	/* wait PIPE clock */
127 	ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
128 				 status & PCL_PCLK_ALIVE, 100000, 1000000);
129 	if (ret) {
130 		dev_err(priv->pci.dev,
131 			"Failed to initialize controller in RC mode\n");
132 		return ret;
133 	}
134 
135 	return 0;
136 }
137 
138 static int uniphier_pcie_link_up(struct dw_pcie *pci)
139 {
140 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
141 	u32 val, mask;
142 
143 	val = readl(priv->base + PCL_STATUS_LINK);
144 	mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
145 
146 	return (val & mask) == mask;
147 }
148 
149 static int uniphier_pcie_start_link(struct dw_pcie *pci)
150 {
151 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
152 
153 	uniphier_pcie_ltssm_enable(priv, true);
154 
155 	return 0;
156 }
157 
158 static void uniphier_pcie_stop_link(struct dw_pcie *pci)
159 {
160 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
161 
162 	uniphier_pcie_ltssm_enable(priv, false);
163 }
164 
165 static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
166 {
167 	writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
168 	writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
169 }
170 
171 static void uniphier_pcie_irq_mask(struct irq_data *d)
172 {
173 	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
174 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
175 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
176 	unsigned long flags;
177 	u32 val;
178 
179 	raw_spin_lock_irqsave(&pp->lock, flags);
180 
181 	val = readl(priv->base + PCL_RCV_INTX);
182 	val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
183 	writel(val, priv->base + PCL_RCV_INTX);
184 
185 	raw_spin_unlock_irqrestore(&pp->lock, flags);
186 }
187 
188 static void uniphier_pcie_irq_unmask(struct irq_data *d)
189 {
190 	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
191 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
192 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
193 	unsigned long flags;
194 	u32 val;
195 
196 	raw_spin_lock_irqsave(&pp->lock, flags);
197 
198 	val = readl(priv->base + PCL_RCV_INTX);
199 	val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
200 	writel(val, priv->base + PCL_RCV_INTX);
201 
202 	raw_spin_unlock_irqrestore(&pp->lock, flags);
203 }
204 
205 static struct irq_chip uniphier_pcie_irq_chip = {
206 	.name = "PCI",
207 	.irq_mask = uniphier_pcie_irq_mask,
208 	.irq_unmask = uniphier_pcie_irq_unmask,
209 };
210 
211 static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
212 				  irq_hw_number_t hwirq)
213 {
214 	irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
215 				 handle_level_irq);
216 	irq_set_chip_data(irq, domain->host_data);
217 
218 	return 0;
219 }
220 
221 static const struct irq_domain_ops uniphier_intx_domain_ops = {
222 	.map = uniphier_pcie_intx_map,
223 };
224 
225 static void uniphier_pcie_irq_handler(struct irq_desc *desc)
226 {
227 	struct pcie_port *pp = irq_desc_get_handler_data(desc);
228 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
229 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
230 	struct irq_chip *chip = irq_desc_get_chip(desc);
231 	unsigned long reg;
232 	u32 val, bit;
233 
234 	/* INT for debug */
235 	val = readl(priv->base + PCL_RCV_INT);
236 
237 	if (val & PCL_CFG_BW_MGT_STATUS)
238 		dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
239 	if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
240 		dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
241 	if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
242 		dev_dbg(pci->dev, "Root Error\n");
243 	if (val & PCL_CFG_PME_MSI_STATUS)
244 		dev_dbg(pci->dev, "PME Interrupt\n");
245 
246 	writel(val, priv->base + PCL_RCV_INT);
247 
248 	/* INTx */
249 	chained_irq_enter(chip, desc);
250 
251 	val = readl(priv->base + PCL_RCV_INTX);
252 	reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
253 
254 	for_each_set_bit(bit, &reg, PCI_NUM_INTX)
255 		generic_handle_domain_irq(priv->legacy_irq_domain, bit);
256 
257 	chained_irq_exit(chip, desc);
258 }
259 
260 static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
261 {
262 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
263 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
264 	struct device_node *np = pci->dev->of_node;
265 	struct device_node *np_intc;
266 	int ret = 0;
267 
268 	np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
269 	if (!np_intc) {
270 		dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
271 		return -EINVAL;
272 	}
273 
274 	pp->irq = irq_of_parse_and_map(np_intc, 0);
275 	if (!pp->irq) {
276 		dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
277 		ret = -EINVAL;
278 		goto out_put_node;
279 	}
280 
281 	priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
282 						&uniphier_intx_domain_ops, pp);
283 	if (!priv->legacy_irq_domain) {
284 		dev_err(pci->dev, "Failed to get INTx domain\n");
285 		ret = -ENODEV;
286 		goto out_put_node;
287 	}
288 
289 	irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
290 					 pp);
291 
292 out_put_node:
293 	of_node_put(np_intc);
294 	return ret;
295 }
296 
297 static int uniphier_pcie_host_init(struct pcie_port *pp)
298 {
299 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
300 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
301 	int ret;
302 
303 	ret = uniphier_pcie_config_legacy_irq(pp);
304 	if (ret)
305 		return ret;
306 
307 	uniphier_pcie_irq_enable(priv);
308 
309 	return 0;
310 }
311 
312 static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
313 	.host_init = uniphier_pcie_host_init,
314 };
315 
316 static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
317 {
318 	int ret;
319 
320 	ret = clk_prepare_enable(priv->clk);
321 	if (ret)
322 		return ret;
323 
324 	ret = reset_control_deassert(priv->rst);
325 	if (ret)
326 		goto out_clk_disable;
327 
328 	uniphier_pcie_init_rc(priv);
329 
330 	ret = phy_init(priv->phy);
331 	if (ret)
332 		goto out_rst_assert;
333 
334 	ret = uniphier_pcie_wait_rc(priv);
335 	if (ret)
336 		goto out_phy_exit;
337 
338 	return 0;
339 
340 out_phy_exit:
341 	phy_exit(priv->phy);
342 out_rst_assert:
343 	reset_control_assert(priv->rst);
344 out_clk_disable:
345 	clk_disable_unprepare(priv->clk);
346 
347 	return ret;
348 }
349 
350 static const struct dw_pcie_ops dw_pcie_ops = {
351 	.start_link = uniphier_pcie_start_link,
352 	.stop_link = uniphier_pcie_stop_link,
353 	.link_up = uniphier_pcie_link_up,
354 };
355 
356 static int uniphier_pcie_probe(struct platform_device *pdev)
357 {
358 	struct device *dev = &pdev->dev;
359 	struct uniphier_pcie_priv *priv;
360 	int ret;
361 
362 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
363 	if (!priv)
364 		return -ENOMEM;
365 
366 	priv->pci.dev = dev;
367 	priv->pci.ops = &dw_pcie_ops;
368 
369 	priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
370 	if (IS_ERR(priv->base))
371 		return PTR_ERR(priv->base);
372 
373 	priv->clk = devm_clk_get(dev, NULL);
374 	if (IS_ERR(priv->clk))
375 		return PTR_ERR(priv->clk);
376 
377 	priv->rst = devm_reset_control_get_shared(dev, NULL);
378 	if (IS_ERR(priv->rst))
379 		return PTR_ERR(priv->rst);
380 
381 	priv->phy = devm_phy_optional_get(dev, "pcie-phy");
382 	if (IS_ERR(priv->phy))
383 		return PTR_ERR(priv->phy);
384 
385 	platform_set_drvdata(pdev, priv);
386 
387 	ret = uniphier_pcie_host_enable(priv);
388 	if (ret)
389 		return ret;
390 
391 	priv->pci.pp.ops = &uniphier_pcie_host_ops;
392 
393 	return dw_pcie_host_init(&priv->pci.pp);
394 }
395 
396 static const struct of_device_id uniphier_pcie_match[] = {
397 	{ .compatible = "socionext,uniphier-pcie", },
398 	{ /* sentinel */ },
399 };
400 
401 static struct platform_driver uniphier_pcie_driver = {
402 	.probe  = uniphier_pcie_probe,
403 	.driver = {
404 		.name = "uniphier-pcie",
405 		.of_match_table = uniphier_pcie_match,
406 	},
407 };
408 builtin_platform_driver(uniphier_pcie_driver);
409