1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe endpoint controller driver for UniPhier SoCs 4 * Copyright 2018 Socionext Inc. 5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/of_device.h> 14 #include <linux/pci.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 19 #include "pcie-designware.h" 20 21 /* Link Glue registers */ 22 #define PCL_RSTCTRL0 0x0010 23 #define PCL_RSTCTRL_AXI_REG BIT(3) 24 #define PCL_RSTCTRL_AXI_SLAVE BIT(2) 25 #define PCL_RSTCTRL_AXI_MASTER BIT(1) 26 #define PCL_RSTCTRL_PIPE3 BIT(0) 27 28 #define PCL_RSTCTRL1 0x0020 29 #define PCL_RSTCTRL_PERST BIT(0) 30 31 #define PCL_RSTCTRL2 0x0024 32 #define PCL_RSTCTRL_PHY_RESET BIT(0) 33 34 #define PCL_MODE 0x8000 35 #define PCL_MODE_REGEN BIT(8) 36 #define PCL_MODE_REGVAL BIT(0) 37 38 #define PCL_APP_CLK_CTRL 0x8004 39 #define PCL_APP_CLK_REQ BIT(0) 40 41 #define PCL_APP_READY_CTRL 0x8008 42 #define PCL_APP_LTSSM_ENABLE BIT(0) 43 44 #define PCL_APP_MSI0 0x8040 45 #define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8) 46 #define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0) 47 48 #define PCL_APP_MSI1 0x8044 49 #define PCL_APP_MSI_REQ BIT(0) 50 51 #define PCL_APP_INTX 0x8074 52 #define PCL_APP_INTX_SYS_INT BIT(0) 53 54 /* assertion time of INTx in usec */ 55 #define PCL_INTX_WIDTH_USEC 30 56 57 struct uniphier_pcie_ep_priv { 58 void __iomem *base; 59 struct dw_pcie pci; 60 struct clk *clk, *clk_gio; 61 struct reset_control *rst, *rst_gio; 62 struct phy *phy; 63 const struct uniphier_pcie_ep_soc_data *data; 64 }; 65 66 struct uniphier_pcie_ep_soc_data { 67 bool has_gio; 68 void (*init)(struct uniphier_pcie_ep_priv *priv); 69 int (*wait)(struct uniphier_pcie_ep_priv *priv); 70 const struct pci_epc_features features; 71 }; 72 73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) 74 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv, 76 bool enable) 77 { 78 u32 val; 79 80 val = readl(priv->base + PCL_APP_READY_CTRL); 81 if (enable) 82 val |= PCL_APP_LTSSM_ENABLE; 83 else 84 val &= ~PCL_APP_LTSSM_ENABLE; 85 writel(val, priv->base + PCL_APP_READY_CTRL); 86 } 87 88 static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv, 89 bool assert) 90 { 91 u32 val; 92 93 val = readl(priv->base + PCL_RSTCTRL2); 94 if (assert) 95 val |= PCL_RSTCTRL_PHY_RESET; 96 else 97 val &= ~PCL_RSTCTRL_PHY_RESET; 98 writel(val, priv->base + PCL_RSTCTRL2); 99 } 100 101 static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv) 102 { 103 u32 val; 104 105 /* set EP mode */ 106 val = readl(priv->base + PCL_MODE); 107 val |= PCL_MODE_REGEN | PCL_MODE_REGVAL; 108 writel(val, priv->base + PCL_MODE); 109 110 /* clock request */ 111 val = readl(priv->base + PCL_APP_CLK_CTRL); 112 val &= ~PCL_APP_CLK_REQ; 113 writel(val, priv->base + PCL_APP_CLK_CTRL); 114 115 /* deassert PIPE3 and AXI reset */ 116 val = readl(priv->base + PCL_RSTCTRL0); 117 val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE 118 | PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3; 119 writel(val, priv->base + PCL_RSTCTRL0); 120 121 uniphier_pcie_ltssm_enable(priv, false); 122 123 msleep(100); 124 } 125 126 static int uniphier_pcie_start_link(struct dw_pcie *pci) 127 { 128 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); 129 130 uniphier_pcie_ltssm_enable(priv, true); 131 132 return 0; 133 } 134 135 static void uniphier_pcie_stop_link(struct dw_pcie *pci) 136 { 137 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); 138 139 uniphier_pcie_ltssm_enable(priv, false); 140 } 141 142 static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep) 143 { 144 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 145 enum pci_barno bar; 146 147 for (bar = BAR_0; bar <= BAR_5; bar++) 148 dw_pcie_ep_reset_bar(pci, bar); 149 } 150 151 static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep) 152 { 153 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 154 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); 155 u32 val; 156 157 /* 158 * This makes pulse signal to send INTx to the RC, so this should 159 * be cleared as soon as possible. This sequence is covered with 160 * mutex in pci_epc_raise_irq(). 161 */ 162 /* assert INTx */ 163 val = readl(priv->base + PCL_APP_INTX); 164 val |= PCL_APP_INTX_SYS_INT; 165 writel(val, priv->base + PCL_APP_INTX); 166 167 udelay(PCL_INTX_WIDTH_USEC); 168 169 /* deassert INTx */ 170 val &= ~PCL_APP_INTX_SYS_INT; 171 writel(val, priv->base + PCL_APP_INTX); 172 173 return 0; 174 } 175 176 static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, 177 u8 func_no, u16 interrupt_num) 178 { 179 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 180 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); 181 u32 val; 182 183 val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no) 184 | FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1); 185 writel(val, priv->base + PCL_APP_MSI0); 186 187 val = readl(priv->base + PCL_APP_MSI1); 188 val |= PCL_APP_MSI_REQ; 189 writel(val, priv->base + PCL_APP_MSI1); 190 191 return 0; 192 } 193 194 static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 195 enum pci_epc_irq_type type, 196 u16 interrupt_num) 197 { 198 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 199 200 switch (type) { 201 case PCI_EPC_IRQ_LEGACY: 202 return uniphier_pcie_ep_raise_legacy_irq(ep); 203 case PCI_EPC_IRQ_MSI: 204 return uniphier_pcie_ep_raise_msi_irq(ep, func_no, 205 interrupt_num); 206 default: 207 dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type); 208 } 209 210 return 0; 211 } 212 213 static const struct pci_epc_features* 214 uniphier_pcie_get_features(struct dw_pcie_ep *ep) 215 { 216 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 217 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); 218 219 return &priv->data->features; 220 } 221 222 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = { 223 .ep_init = uniphier_pcie_ep_init, 224 .raise_irq = uniphier_pcie_ep_raise_irq, 225 .get_features = uniphier_pcie_get_features, 226 }; 227 228 static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv) 229 { 230 int ret; 231 232 ret = clk_prepare_enable(priv->clk); 233 if (ret) 234 return ret; 235 236 ret = clk_prepare_enable(priv->clk_gio); 237 if (ret) 238 goto out_clk_disable; 239 240 ret = reset_control_deassert(priv->rst); 241 if (ret) 242 goto out_clk_gio_disable; 243 244 ret = reset_control_deassert(priv->rst_gio); 245 if (ret) 246 goto out_rst_assert; 247 248 if (priv->data->init) 249 priv->data->init(priv); 250 251 uniphier_pcie_phy_reset(priv, true); 252 253 ret = phy_init(priv->phy); 254 if (ret) 255 goto out_rst_gio_assert; 256 257 uniphier_pcie_phy_reset(priv, false); 258 259 if (priv->data->wait) { 260 ret = priv->data->wait(priv); 261 if (ret) 262 goto out_phy_exit; 263 } 264 265 return 0; 266 267 out_phy_exit: 268 phy_exit(priv->phy); 269 out_rst_gio_assert: 270 reset_control_assert(priv->rst_gio); 271 out_rst_assert: 272 reset_control_assert(priv->rst); 273 out_clk_gio_disable: 274 clk_disable_unprepare(priv->clk_gio); 275 out_clk_disable: 276 clk_disable_unprepare(priv->clk); 277 278 return ret; 279 } 280 281 static const struct dw_pcie_ops dw_pcie_ops = { 282 .start_link = uniphier_pcie_start_link, 283 .stop_link = uniphier_pcie_stop_link, 284 }; 285 286 static int uniphier_pcie_ep_probe(struct platform_device *pdev) 287 { 288 struct device *dev = &pdev->dev; 289 struct uniphier_pcie_ep_priv *priv; 290 int ret; 291 292 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 293 if (!priv) 294 return -ENOMEM; 295 296 priv->data = of_device_get_match_data(dev); 297 if (WARN_ON(!priv->data)) 298 return -EINVAL; 299 300 priv->pci.dev = dev; 301 priv->pci.ops = &dw_pcie_ops; 302 303 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); 304 if (IS_ERR(priv->base)) 305 return PTR_ERR(priv->base); 306 307 if (priv->data->has_gio) { 308 priv->clk_gio = devm_clk_get(dev, "gio"); 309 if (IS_ERR(priv->clk_gio)) 310 return PTR_ERR(priv->clk_gio); 311 312 priv->rst_gio = devm_reset_control_get_shared(dev, "gio"); 313 if (IS_ERR(priv->rst_gio)) 314 return PTR_ERR(priv->rst_gio); 315 } 316 317 priv->clk = devm_clk_get(dev, "link"); 318 if (IS_ERR(priv->clk)) 319 return PTR_ERR(priv->clk); 320 321 priv->rst = devm_reset_control_get_shared(dev, "link"); 322 if (IS_ERR(priv->rst)) 323 return PTR_ERR(priv->rst); 324 325 priv->phy = devm_phy_optional_get(dev, "pcie-phy"); 326 if (IS_ERR(priv->phy)) { 327 ret = PTR_ERR(priv->phy); 328 dev_err(dev, "Failed to get phy (%d)\n", ret); 329 return ret; 330 } 331 332 platform_set_drvdata(pdev, priv); 333 334 ret = uniphier_pcie_ep_enable(priv); 335 if (ret) 336 return ret; 337 338 priv->pci.ep.ops = &uniphier_pcie_ep_ops; 339 return dw_pcie_ep_init(&priv->pci.ep); 340 } 341 342 static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = { 343 .has_gio = true, 344 .init = uniphier_pcie_pro5_init_ep, 345 .wait = NULL, 346 .features = { 347 .linkup_notifier = false, 348 .msi_capable = true, 349 .msix_capable = false, 350 .align = 1 << 16, 351 .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), 352 .reserved_bar = BIT(BAR_4), 353 }, 354 }; 355 356 static const struct of_device_id uniphier_pcie_ep_match[] = { 357 { 358 .compatible = "socionext,uniphier-pro5-pcie-ep", 359 .data = &uniphier_pro5_data, 360 }, 361 { /* sentinel */ }, 362 }; 363 364 static struct platform_driver uniphier_pcie_ep_driver = { 365 .probe = uniphier_pcie_ep_probe, 366 .driver = { 367 .name = "uniphier-pcie-ep", 368 .of_match_table = uniphier_pcie_ep_match, 369 .suppress_bind_attrs = true, 370 }, 371 }; 372 builtin_platform_driver(uniphier_pcie_ep_driver); 373