1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for Tegra194 SoC 4 * 5 * Copyright (C) 2019 NVIDIA Corporation. 6 * 7 * Author: Vidya Sagar <vidyas@nvidia.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/reset.h> 31 #include <linux/resource.h> 32 #include <linux/types.h> 33 #include "pcie-designware.h" 34 #include <soc/tegra/bpmp.h> 35 #include <soc/tegra/bpmp-abi.h> 36 #include "../../pci.h" 37 38 #define APPL_PINMUX 0x0 39 #define APPL_PINMUX_PEX_RST BIT(0) 40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) 41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) 42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) 43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) 44 45 #define APPL_CTRL 0x4 46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) 47 #define APPL_CTRL_LTSSM_EN BIT(7) 48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20) 49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) 50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22 51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 52 53 #define APPL_INTR_EN_L0_0 0x8 54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0) 55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4) 56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8) 57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15) 58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19) 59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30) 60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31) 61 62 #define APPL_INTR_STATUS_L0 0xC 63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0) 64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8) 65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15) 66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16) 67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18) 68 69 #define APPL_INTR_EN_L1_0_0 0x1C 70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1) 71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3) 72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30) 73 74 #define APPL_INTR_STATUS_L1_0_0 0x20 75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1) 76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3) 77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30) 78 79 #define APPL_INTR_STATUS_L1_1 0x2C 80 #define APPL_INTR_STATUS_L1_2 0x30 81 #define APPL_INTR_STATUS_L1_3 0x34 82 #define APPL_INTR_STATUS_L1_6 0x3C 83 #define APPL_INTR_STATUS_L1_7 0x40 84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1) 85 86 #define APPL_INTR_EN_L1_8_0 0x44 87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) 88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) 89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) 90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) 91 92 #define APPL_INTR_STATUS_L1_8_0 0x4C 93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6) 94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2) 95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3) 96 97 #define APPL_INTR_STATUS_L1_9 0x54 98 #define APPL_INTR_STATUS_L1_10 0x58 99 #define APPL_INTR_STATUS_L1_11 0x64 100 #define APPL_INTR_STATUS_L1_13 0x74 101 #define APPL_INTR_STATUS_L1_14 0x78 102 #define APPL_INTR_STATUS_L1_15 0x7C 103 #define APPL_INTR_STATUS_L1_17 0x88 104 105 #define APPL_INTR_EN_L1_18 0x90 106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2) 107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 109 110 #define APPL_INTR_STATUS_L1_18 0x94 111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2) 112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 114 115 #define APPL_MSI_CTRL_1 0xAC 116 117 #define APPL_MSI_CTRL_2 0xB0 118 119 #define APPL_LEGACY_INTX 0xB8 120 121 #define APPL_LTR_MSG_1 0xC4 122 #define LTR_MSG_REQ BIT(15) 123 #define LTR_MST_NO_SNOOP_SHIFT 16 124 125 #define APPL_LTR_MSG_2 0xC8 126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) 127 128 #define APPL_LINK_STATUS 0xCC 129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0) 130 131 #define APPL_DEBUG 0xD0 132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) 133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) 135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 136 #define LTSSM_STATE_PRE_DETECT 5 137 138 #define APPL_RADM_STATUS 0xE4 139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) 140 141 #define APPL_DM_TYPE 0x100 142 #define APPL_DM_TYPE_MASK GENMASK(3, 0) 143 #define APPL_DM_TYPE_RP 0x4 144 #define APPL_DM_TYPE_EP 0x0 145 146 #define APPL_CFG_BASE_ADDR 0x104 147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12) 148 149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108 150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18) 151 152 #define APPL_CFG_MISC 0x110 153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) 154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10) 155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10 156 #define APPL_CFG_MISC_ARCACHE_VAL 3 157 158 #define APPL_CFG_SLCG_OVERRIDE 0x114 159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0) 160 161 #define APPL_CAR_RESET_OVRD 0x12C 162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0) 163 164 #define IO_BASE_IO_DECODE BIT(0) 165 #define IO_BASE_IO_DECODE_BIT8 BIT(8) 166 167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0) 168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) 169 170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718 171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19) 172 173 #define EVENT_COUNTER_ALL_CLEAR 0x3 174 #define EVENT_COUNTER_ENABLE_ALL 0x7 175 #define EVENT_COUNTER_ENABLE_SHIFT 2 176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) 177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 180 #define EVENT_COUNTER_EVENT_L1 0x5 181 #define EVENT_COUNTER_EVENT_L1_1 0x7 182 #define EVENT_COUNTER_EVENT_L1_2 0x8 183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 184 #define EVENT_COUNTER_GROUP_5 0x5 185 186 #define N_FTS_VAL 52 187 #define FTS_VAL 52 188 189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 190 191 #define GEN3_EQ_CONTROL_OFF 0x8a8 192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8 193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) 194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) 195 196 #define GEN3_RELATED_OFF 0x890 197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) 198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 201 202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) 205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0 206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 208 209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940 210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) 211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) 212 213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944 214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0) 215 216 #define PORT_LOGIC_MSIX_DOORBELL 0x948 217 218 #define CAP_SPCIE_CAP_OFF 0x154 219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0) 220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) 221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 222 223 #define PME_ACK_TIMEOUT 10000 224 225 #define LTSSM_TIMEOUT 50000 /* 50ms */ 226 227 #define GEN3_GEN4_EQ_PRESET_INIT 5 228 229 #define GEN1_CORE_CLK_FREQ 62500000 230 #define GEN2_CORE_CLK_FREQ 125000000 231 #define GEN3_CORE_CLK_FREQ 250000000 232 #define GEN4_CORE_CLK_FREQ 500000000 233 234 #define LTR_MSG_TIMEOUT (100 * 1000) 235 236 #define PERST_DEBOUNCE_TIME (5 * 1000) 237 238 #define EP_STATE_DISABLED 0 239 #define EP_STATE_ENABLED 1 240 241 static const unsigned int pcie_gen_freq[] = { 242 GEN1_CORE_CLK_FREQ, 243 GEN2_CORE_CLK_FREQ, 244 GEN3_CORE_CLK_FREQ, 245 GEN4_CORE_CLK_FREQ 246 }; 247 248 static const u32 event_cntr_ctrl_offset[] = { 249 0x1d8, 250 0x1a8, 251 0x1a8, 252 0x1a8, 253 0x1c4, 254 0x1d8 255 }; 256 257 static const u32 event_cntr_data_offset[] = { 258 0x1dc, 259 0x1ac, 260 0x1ac, 261 0x1ac, 262 0x1c8, 263 0x1dc 264 }; 265 266 struct tegra_pcie_dw { 267 struct device *dev; 268 struct resource *appl_res; 269 struct resource *dbi_res; 270 struct resource *atu_dma_res; 271 void __iomem *appl_base; 272 struct clk *core_clk; 273 struct reset_control *core_apb_rst; 274 struct reset_control *core_rst; 275 struct dw_pcie pci; 276 struct tegra_bpmp *bpmp; 277 278 enum dw_pcie_device_mode mode; 279 280 bool supports_clkreq; 281 bool enable_cdm_check; 282 bool link_state; 283 bool update_fc_fixup; 284 u8 init_link_width; 285 u32 msi_ctrl_int; 286 u32 num_lanes; 287 u32 cid; 288 u32 cfg_link_cap_l1sub; 289 u32 pcie_cap_base; 290 u32 aspm_cmrt; 291 u32 aspm_pwr_on_t; 292 u32 aspm_l0s_enter_lat; 293 294 struct regulator *pex_ctl_supply; 295 struct regulator *slot_ctl_3v3; 296 struct regulator *slot_ctl_12v; 297 298 unsigned int phy_count; 299 struct phy **phys; 300 301 struct dentry *debugfs; 302 303 /* Endpoint mode specific */ 304 struct gpio_desc *pex_rst_gpiod; 305 struct gpio_desc *pex_refclk_sel_gpiod; 306 unsigned int pex_rst_irq; 307 int ep_state; 308 }; 309 310 struct tegra_pcie_dw_of_data { 311 enum dw_pcie_device_mode mode; 312 }; 313 314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) 315 { 316 return container_of(pci, struct tegra_pcie_dw, pci); 317 } 318 319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, 320 const u32 reg) 321 { 322 writel_relaxed(value, pcie->appl_base + reg); 323 } 324 325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) 326 { 327 return readl_relaxed(pcie->appl_base + reg); 328 } 329 330 struct tegra_pcie_soc { 331 enum dw_pcie_device_mode mode; 332 }; 333 334 static void apply_bad_link_workaround(struct pcie_port *pp) 335 { 336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 338 u32 current_link_width; 339 u16 val; 340 341 /* 342 * NOTE:- Since this scenario is uncommon and link as such is not 343 * stable anyway, not waiting to confirm if link is really 344 * transitioning to Gen-2 speed 345 */ 346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 347 if (val & PCI_EXP_LNKSTA_LBMS) { 348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> 349 PCI_EXP_LNKSTA_NLW_SHIFT; 350 if (pcie->init_link_width > current_link_width) { 351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); 352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 353 PCI_EXP_LNKCTL2); 354 val &= ~PCI_EXP_LNKCTL2_TLS; 355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT; 356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 357 PCI_EXP_LNKCTL2, val); 358 359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 360 PCI_EXP_LNKCTL); 361 val |= PCI_EXP_LNKCTL_RL; 362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 363 PCI_EXP_LNKCTL, val); 364 } 365 } 366 } 367 368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) 369 { 370 struct tegra_pcie_dw *pcie = arg; 371 struct dw_pcie *pci = &pcie->pci; 372 struct pcie_port *pp = &pci->pp; 373 u32 val, tmp; 374 u16 val_w; 375 376 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 377 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 378 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 379 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) { 380 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 381 382 /* SBR & Surprise Link Down WAR */ 383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 386 udelay(1); 387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 390 391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 392 val |= PORT_LOGIC_SPEED_CHANGE; 393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 394 } 395 } 396 397 if (val & APPL_INTR_STATUS_L0_INT_INT) { 398 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); 399 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) { 400 appl_writel(pcie, 401 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS, 402 APPL_INTR_STATUS_L1_8_0); 403 apply_bad_link_workaround(pp); 404 } 405 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { 406 appl_writel(pcie, 407 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, 408 APPL_INTR_STATUS_L1_8_0); 409 410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 411 PCI_EXP_LNKSTA); 412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & 413 PCI_EXP_LNKSTA_CLS); 414 } 415 } 416 417 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 418 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { 419 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18); 420 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 421 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { 422 dev_info(pci->dev, "CDM check complete\n"); 423 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE; 424 } 425 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) { 426 dev_err(pci->dev, "CDM comparison mismatch\n"); 427 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR; 428 } 429 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) { 430 dev_err(pci->dev, "CDM Logic error\n"); 431 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; 432 } 433 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp); 434 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); 435 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp); 436 } 437 438 return IRQ_HANDLED; 439 } 440 441 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) 442 { 443 u32 val; 444 445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 460 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2); 461 462 val = appl_readl(pcie, APPL_CTRL); 463 val |= APPL_CTRL_LTSSM_EN; 464 appl_writel(pcie, val, APPL_CTRL); 465 } 466 467 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) 468 { 469 struct tegra_pcie_dw *pcie = arg; 470 struct dw_pcie *pci = &pcie->pci; 471 u32 val, speed; 472 473 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 474 PCI_EXP_LNKSTA_CLS; 475 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 476 477 /* If EP doesn't advertise L1SS, just return */ 478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 479 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2))) 480 return IRQ_HANDLED; 481 482 /* Check if BME is set to '1' */ 483 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 484 if (val & PCI_COMMAND_MASTER) { 485 ktime_t timeout; 486 487 /* 110us for both snoop and no-snoop */ 488 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; 489 val |= (val << LTR_MST_NO_SNOOP_SHIFT); 490 appl_writel(pcie, val, APPL_LTR_MSG_1); 491 492 /* Send LTR upstream */ 493 val = appl_readl(pcie, APPL_LTR_MSG_2); 494 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; 495 appl_writel(pcie, val, APPL_LTR_MSG_2); 496 497 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT); 498 for (;;) { 499 val = appl_readl(pcie, APPL_LTR_MSG_2); 500 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)) 501 break; 502 if (ktime_after(ktime_get(), timeout)) 503 break; 504 usleep_range(1000, 1100); 505 } 506 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE) 507 dev_err(pcie->dev, "Failed to send LTR message\n"); 508 } 509 510 return IRQ_HANDLED; 511 } 512 513 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) 514 { 515 struct tegra_pcie_dw *pcie = arg; 516 struct dw_pcie_ep *ep = &pcie->pci.ep; 517 int spurious = 1; 518 u32 val, tmp; 519 520 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 521 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 522 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 523 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 524 525 if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) 526 pex_ep_event_hot_rst_done(pcie); 527 528 if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { 529 tmp = appl_readl(pcie, APPL_LINK_STATUS); 530 if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { 531 dev_dbg(pcie->dev, "Link is up with Host\n"); 532 dw_pcie_ep_linkup(ep); 533 } 534 } 535 536 spurious = 0; 537 } 538 539 if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { 540 val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); 541 appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); 542 543 if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) 544 return IRQ_WAKE_THREAD; 545 546 spurious = 0; 547 } 548 549 if (spurious) { 550 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", 551 val); 552 appl_writel(pcie, val, APPL_INTR_STATUS_L0); 553 } 554 555 return IRQ_HANDLED; 556 } 557 558 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, 559 int size, u32 *val) 560 { 561 /* 562 * This is an endpoint mode specific register happen to appear even 563 * when controller is operating in root port mode and system hangs 564 * when it is accessed with link being in ASPM-L1 state. 565 * So skip accessing it altogether 566 */ 567 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { 568 *val = 0x00000000; 569 return PCIBIOS_SUCCESSFUL; 570 } 571 572 return pci_generic_config_read(bus, devfn, where, size, val); 573 } 574 575 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, 576 int size, u32 val) 577 { 578 /* 579 * This is an endpoint mode specific register happen to appear even 580 * when controller is operating in root port mode and system hangs 581 * when it is accessed with link being in ASPM-L1 state. 582 * So skip accessing it altogether 583 */ 584 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) 585 return PCIBIOS_SUCCESSFUL; 586 587 return pci_generic_config_write(bus, devfn, where, size, val); 588 } 589 590 static struct pci_ops tegra_pci_ops = { 591 .map_bus = dw_pcie_own_conf_map_bus, 592 .read = tegra_pcie_dw_rd_own_conf, 593 .write = tegra_pcie_dw_wr_own_conf, 594 }; 595 596 #if defined(CONFIG_PCIEASPM) 597 static void disable_aspm_l11(struct tegra_pcie_dw *pcie) 598 { 599 u32 val; 600 601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 602 val &= ~PCI_L1SS_CAP_ASPM_L1_1; 603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 604 } 605 606 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) 607 { 608 u32 val; 609 610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 611 val &= ~PCI_L1SS_CAP_ASPM_L1_2; 612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 613 } 614 615 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) 616 { 617 u32 val; 618 619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); 620 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); 621 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 622 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT; 623 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); 626 627 return val; 628 } 629 630 static int aspm_state_cnt(struct seq_file *s, void *data) 631 { 632 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *) 633 dev_get_drvdata(s->private); 634 u32 val; 635 636 seq_printf(s, "Tx L0s entry count : %u\n", 637 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S)); 638 639 seq_printf(s, "Rx L0s entry count : %u\n", 640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S)); 641 642 seq_printf(s, "Link L1 entry count : %u\n", 643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1)); 644 645 seq_printf(s, "Link L1.1 entry count : %u\n", 646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1)); 647 648 seq_printf(s, "Link L1.2 entry count : %u\n", 649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2)); 650 651 /* Clear all counters */ 652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], 653 EVENT_COUNTER_ALL_CLEAR); 654 655 /* Re-enable counting */ 656 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 657 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 659 660 return 0; 661 } 662 663 static void init_host_aspm(struct tegra_pcie_dw *pcie) 664 { 665 struct dw_pcie *pci = &pcie->pci; 666 u32 val; 667 668 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; 670 671 /* Enable ASPM counters */ 672 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 673 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); 675 676 /* Program T_cmrt and T_pwr_on values */ 677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 678 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); 679 val |= (pcie->aspm_cmrt << 8); 680 val |= (pcie->aspm_pwr_on_t << 19); 681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); 682 683 /* Program L0s and L1 entrance latencies */ 684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 685 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; 686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); 687 val |= PORT_AFR_ENTER_ASPM; 688 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 689 } 690 691 static int init_debugfs(struct tegra_pcie_dw *pcie) 692 { 693 struct dentry *d; 694 695 d = debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", 696 pcie->debugfs, aspm_state_cnt); 697 if (IS_ERR_OR_NULL(d)) 698 dev_err(pcie->dev, 699 "Failed to create debugfs file \"aspm_state_cnt\"\n"); 700 701 return 0; 702 } 703 #else 704 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; } 705 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; } 706 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; } 707 static inline int init_debugfs(struct tegra_pcie_dw *pcie) { return 0; } 708 #endif 709 710 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) 711 { 712 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 713 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 714 u32 val; 715 u16 val_w; 716 717 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 718 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 719 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 720 721 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 722 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN; 723 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 724 725 if (pcie->enable_cdm_check) { 726 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 727 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN; 728 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 729 730 val = appl_readl(pcie, APPL_INTR_EN_L1_18); 731 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR; 732 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR; 733 appl_writel(pcie, val, APPL_INTR_EN_L1_18); 734 } 735 736 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 737 PCI_EXP_LNKSTA); 738 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> 739 PCI_EXP_LNKSTA_NLW_SHIFT; 740 741 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 742 PCI_EXP_LNKCTL); 743 val_w |= PCI_EXP_LNKCTL_LBMIE; 744 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, 745 val_w); 746 } 747 748 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) 749 { 750 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 751 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 752 u32 val; 753 754 /* Enable legacy interrupt generation */ 755 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 756 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 757 val |= APPL_INTR_EN_L0_0_INT_INT_EN; 758 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 759 760 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); 761 val |= APPL_INTR_EN_L1_8_INTX_EN; 762 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; 763 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; 764 if (IS_ENABLED(CONFIG_PCIEAER)) 765 val |= APPL_INTR_EN_L1_8_AER_INT_EN; 766 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); 767 } 768 769 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) 770 { 771 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 772 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 773 u32 val; 774 775 dw_pcie_msi_init(pp); 776 777 /* Enable MSI interrupt generation */ 778 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 779 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; 780 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN; 781 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 782 } 783 784 static void tegra_pcie_enable_interrupts(struct pcie_port *pp) 785 { 786 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 787 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 788 789 /* Clear interrupt statuses before enabling interrupts */ 790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 796 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 797 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 798 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 799 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 800 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 801 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 802 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 803 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 804 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 805 806 tegra_pcie_enable_system_interrupts(pp); 807 tegra_pcie_enable_legacy_interrupts(pp); 808 if (IS_ENABLED(CONFIG_PCI_MSI)) 809 tegra_pcie_enable_msi_interrupts(pp); 810 } 811 812 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) 813 { 814 struct dw_pcie *pci = &pcie->pci; 815 u32 val, offset, i; 816 817 /* Program init preset */ 818 for (i = 0; i < pcie->num_lanes; i++) { 819 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2)); 820 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; 821 val |= GEN3_GEN4_EQ_PRESET_INIT; 822 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; 823 val |= (GEN3_GEN4_EQ_PRESET_INIT << 824 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT); 825 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); 826 827 offset = dw_pcie_find_ext_capability(pci, 828 PCI_EXT_CAP_ID_PL_16GT) + 829 PCI_PL_16GT_LE_CTRL; 830 val = dw_pcie_readb_dbi(pci, offset + i); 831 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; 832 val |= GEN3_GEN4_EQ_PRESET_INIT; 833 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; 834 val |= (GEN3_GEN4_EQ_PRESET_INIT << 835 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT); 836 dw_pcie_writeb_dbi(pci, offset + i, val); 837 } 838 839 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 840 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 841 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 842 843 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 844 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 845 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 846 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 847 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 848 849 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 850 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 851 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); 852 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 853 854 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 855 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 856 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 857 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 858 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 859 860 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 861 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 862 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 863 } 864 865 static void tegra_pcie_prepare_host(struct pcie_port *pp) 866 { 867 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 868 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 869 u32 val; 870 871 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); 872 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); 873 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); 874 875 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); 876 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; 877 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; 878 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); 879 880 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 881 882 /* Enable as 0xFFFF0001 response for CRS */ 883 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); 884 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); 885 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << 886 AMBA_ERROR_RESPONSE_CRS_SHIFT); 887 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); 888 889 /* Configure Max lane width from DT */ 890 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); 891 val &= ~PCI_EXP_LNKCAP_MLW; 892 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); 893 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); 894 895 config_gen3_gen4_eq_presets(pcie); 896 897 init_host_aspm(pcie); 898 899 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 900 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 901 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 902 903 if (pcie->update_fc_fixup) { 904 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 905 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 906 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 907 } 908 909 dw_pcie_setup_rc(pp); 910 911 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 912 913 /* Assert RST */ 914 val = appl_readl(pcie, APPL_PINMUX); 915 val &= ~APPL_PINMUX_PEX_RST; 916 appl_writel(pcie, val, APPL_PINMUX); 917 918 usleep_range(100, 200); 919 920 /* Enable LTSSM */ 921 val = appl_readl(pcie, APPL_CTRL); 922 val |= APPL_CTRL_LTSSM_EN; 923 appl_writel(pcie, val, APPL_CTRL); 924 925 /* De-assert RST */ 926 val = appl_readl(pcie, APPL_PINMUX); 927 val |= APPL_PINMUX_PEX_RST; 928 appl_writel(pcie, val, APPL_PINMUX); 929 930 msleep(100); 931 } 932 933 static int tegra_pcie_dw_host_init(struct pcie_port *pp) 934 { 935 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 936 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 937 u32 val, tmp, offset, speed; 938 939 pp->bridge->ops = &tegra_pci_ops; 940 941 tegra_pcie_prepare_host(pp); 942 943 if (dw_pcie_wait_for_link(pci)) { 944 /* 945 * There are some endpoints which can't get the link up if 946 * root port has Data Link Feature (DLF) enabled. 947 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info 948 * on Scaled Flow Control and DLF. 949 * So, need to confirm that is indeed the case here and attempt 950 * link up once again with DLF disabled. 951 */ 952 val = appl_readl(pcie, APPL_DEBUG); 953 val &= APPL_DEBUG_LTSSM_STATE_MASK; 954 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; 955 tmp = appl_readl(pcie, APPL_LINK_STATUS); 956 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP; 957 if (!(val == 0x11 && !tmp)) { 958 /* Link is down for all good reasons */ 959 return 0; 960 } 961 962 dev_info(pci->dev, "Link is down in DLL"); 963 dev_info(pci->dev, "Trying again with DLFE disabled\n"); 964 /* Disable LTSSM */ 965 val = appl_readl(pcie, APPL_CTRL); 966 val &= ~APPL_CTRL_LTSSM_EN; 967 appl_writel(pcie, val, APPL_CTRL); 968 969 reset_control_assert(pcie->core_rst); 970 reset_control_deassert(pcie->core_rst); 971 972 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); 973 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); 974 val &= ~PCI_DLF_EXCHANGE_ENABLE; 975 dw_pcie_writel_dbi(pci, offset, val); 976 977 tegra_pcie_prepare_host(pp); 978 979 if (dw_pcie_wait_for_link(pci)) 980 return 0; 981 } 982 983 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 984 PCI_EXP_LNKSTA_CLS; 985 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 986 987 tegra_pcie_enable_interrupts(pp); 988 989 return 0; 990 } 991 992 static int tegra_pcie_dw_link_up(struct dw_pcie *pci) 993 { 994 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 995 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 996 997 return !!(val & PCI_EXP_LNKSTA_DLLLA); 998 } 999 1000 static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp) 1001 { 1002 pp->num_vectors = MAX_MSI_IRQS; 1003 } 1004 1005 static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 1006 { 1007 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1008 1009 enable_irq(pcie->pex_rst_irq); 1010 1011 return 0; 1012 } 1013 1014 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) 1015 { 1016 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1017 1018 disable_irq(pcie->pex_rst_irq); 1019 } 1020 1021 static const struct dw_pcie_ops tegra_dw_pcie_ops = { 1022 .link_up = tegra_pcie_dw_link_up, 1023 .start_link = tegra_pcie_dw_start_link, 1024 .stop_link = tegra_pcie_dw_stop_link, 1025 }; 1026 1027 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { 1028 .host_init = tegra_pcie_dw_host_init, 1029 .set_num_vectors = tegra_pcie_set_msi_vec_num, 1030 }; 1031 1032 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) 1033 { 1034 unsigned int phy_count = pcie->phy_count; 1035 1036 while (phy_count--) { 1037 phy_power_off(pcie->phys[phy_count]); 1038 phy_exit(pcie->phys[phy_count]); 1039 } 1040 } 1041 1042 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) 1043 { 1044 unsigned int i; 1045 int ret; 1046 1047 for (i = 0; i < pcie->phy_count; i++) { 1048 ret = phy_init(pcie->phys[i]); 1049 if (ret < 0) 1050 goto phy_power_off; 1051 1052 ret = phy_power_on(pcie->phys[i]); 1053 if (ret < 0) 1054 goto phy_exit; 1055 } 1056 1057 return 0; 1058 1059 phy_power_off: 1060 while (i--) { 1061 phy_power_off(pcie->phys[i]); 1062 phy_exit: 1063 phy_exit(pcie->phys[i]); 1064 } 1065 1066 return ret; 1067 } 1068 1069 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) 1070 { 1071 struct device_node *np = pcie->dev->of_node; 1072 int ret; 1073 1074 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); 1075 if (ret < 0) { 1076 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); 1077 return ret; 1078 } 1079 1080 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", 1081 &pcie->aspm_pwr_on_t); 1082 if (ret < 0) 1083 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", 1084 ret); 1085 1086 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", 1087 &pcie->aspm_l0s_enter_lat); 1088 if (ret < 0) 1089 dev_info(pcie->dev, 1090 "Failed to read ASPM L0s Entrance latency: %d\n", ret); 1091 1092 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); 1093 if (ret < 0) { 1094 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); 1095 return ret; 1096 } 1097 1098 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); 1099 if (ret) { 1100 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); 1101 return ret; 1102 } 1103 1104 ret = of_property_count_strings(np, "phy-names"); 1105 if (ret < 0) { 1106 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", 1107 ret); 1108 return ret; 1109 } 1110 pcie->phy_count = ret; 1111 1112 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) 1113 pcie->update_fc_fixup = true; 1114 1115 pcie->supports_clkreq = 1116 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); 1117 1118 pcie->enable_cdm_check = 1119 of_property_read_bool(np, "snps,enable-cdm-check"); 1120 1121 if (pcie->mode == DW_PCIE_RC_TYPE) 1122 return 0; 1123 1124 /* Endpoint mode specific DT entries */ 1125 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); 1126 if (IS_ERR(pcie->pex_rst_gpiod)) { 1127 int err = PTR_ERR(pcie->pex_rst_gpiod); 1128 const char *level = KERN_ERR; 1129 1130 if (err == -EPROBE_DEFER) 1131 level = KERN_DEBUG; 1132 1133 dev_printk(level, pcie->dev, 1134 dev_fmt("Failed to get PERST GPIO: %d\n"), 1135 err); 1136 return err; 1137 } 1138 1139 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, 1140 "nvidia,refclk-select", 1141 GPIOD_OUT_HIGH); 1142 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { 1143 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); 1144 const char *level = KERN_ERR; 1145 1146 if (err == -EPROBE_DEFER) 1147 level = KERN_DEBUG; 1148 1149 dev_printk(level, pcie->dev, 1150 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"), 1151 err); 1152 pcie->pex_refclk_sel_gpiod = NULL; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, 1159 bool enable) 1160 { 1161 struct mrq_uphy_response resp; 1162 struct tegra_bpmp_message msg; 1163 struct mrq_uphy_request req; 1164 1165 /* Controller-5 doesn't need to have its state set by BPMP-FW */ 1166 if (pcie->cid == 5) 1167 return 0; 1168 1169 memset(&req, 0, sizeof(req)); 1170 memset(&resp, 0, sizeof(resp)); 1171 1172 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE; 1173 req.controller_state.pcie_controller = pcie->cid; 1174 req.controller_state.enable = enable; 1175 1176 memset(&msg, 0, sizeof(msg)); 1177 msg.mrq = MRQ_UPHY; 1178 msg.tx.data = &req; 1179 msg.tx.size = sizeof(req); 1180 msg.rx.data = &resp; 1181 msg.rx.size = sizeof(resp); 1182 1183 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1184 } 1185 1186 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, 1187 bool enable) 1188 { 1189 struct mrq_uphy_response resp; 1190 struct tegra_bpmp_message msg; 1191 struct mrq_uphy_request req; 1192 1193 memset(&req, 0, sizeof(req)); 1194 memset(&resp, 0, sizeof(resp)); 1195 1196 if (enable) { 1197 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT; 1198 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; 1199 } else { 1200 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF; 1201 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; 1202 } 1203 1204 memset(&msg, 0, sizeof(msg)); 1205 msg.mrq = MRQ_UPHY; 1206 msg.tx.data = &req; 1207 msg.tx.size = sizeof(req); 1208 msg.rx.data = &resp; 1209 msg.rx.size = sizeof(resp); 1210 1211 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1212 } 1213 1214 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) 1215 { 1216 struct pcie_port *pp = &pcie->pci.pp; 1217 struct pci_bus *child, *root_bus = NULL; 1218 struct pci_dev *pdev; 1219 1220 /* 1221 * link doesn't go into L2 state with some of the endpoints with Tegra 1222 * if they are not in D0 state. So, need to make sure that immediate 1223 * downstream devices are in D0 state before sending PME_TurnOff to put 1224 * link into L2 state. 1225 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, 1226 * 5.2 Link State Power Management (Page #428). 1227 */ 1228 1229 list_for_each_entry(child, &pp->bridge->bus->children, node) { 1230 /* Bring downstream devices to D0 if they are not already in */ 1231 if (child->parent == pp->bridge->bus) { 1232 root_bus = child; 1233 break; 1234 } 1235 } 1236 1237 if (!root_bus) { 1238 dev_err(pcie->dev, "Failed to find downstream devices\n"); 1239 return; 1240 } 1241 1242 list_for_each_entry(pdev, &root_bus->devices, bus_list) { 1243 if (PCI_SLOT(pdev->devfn) == 0) { 1244 if (pci_set_power_state(pdev, PCI_D0)) 1245 dev_err(pcie->dev, 1246 "Failed to transition %s to D0 state\n", 1247 dev_name(&pdev->dev)); 1248 } 1249 } 1250 } 1251 1252 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) 1253 { 1254 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); 1255 if (IS_ERR(pcie->slot_ctl_3v3)) { 1256 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) 1257 return PTR_ERR(pcie->slot_ctl_3v3); 1258 1259 pcie->slot_ctl_3v3 = NULL; 1260 } 1261 1262 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); 1263 if (IS_ERR(pcie->slot_ctl_12v)) { 1264 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) 1265 return PTR_ERR(pcie->slot_ctl_12v); 1266 1267 pcie->slot_ctl_12v = NULL; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) 1274 { 1275 int ret; 1276 1277 if (pcie->slot_ctl_3v3) { 1278 ret = regulator_enable(pcie->slot_ctl_3v3); 1279 if (ret < 0) { 1280 dev_err(pcie->dev, 1281 "Failed to enable 3.3V slot supply: %d\n", ret); 1282 return ret; 1283 } 1284 } 1285 1286 if (pcie->slot_ctl_12v) { 1287 ret = regulator_enable(pcie->slot_ctl_12v); 1288 if (ret < 0) { 1289 dev_err(pcie->dev, 1290 "Failed to enable 12V slot supply: %d\n", ret); 1291 goto fail_12v_enable; 1292 } 1293 } 1294 1295 /* 1296 * According to PCI Express Card Electromechanical Specification 1297 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) 1298 * should be a minimum of 100ms. 1299 */ 1300 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) 1301 msleep(100); 1302 1303 return 0; 1304 1305 fail_12v_enable: 1306 if (pcie->slot_ctl_3v3) 1307 regulator_disable(pcie->slot_ctl_3v3); 1308 return ret; 1309 } 1310 1311 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) 1312 { 1313 if (pcie->slot_ctl_12v) 1314 regulator_disable(pcie->slot_ctl_12v); 1315 if (pcie->slot_ctl_3v3) 1316 regulator_disable(pcie->slot_ctl_3v3); 1317 } 1318 1319 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, 1320 bool en_hw_hot_rst) 1321 { 1322 int ret; 1323 u32 val; 1324 1325 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true); 1326 if (ret) { 1327 dev_err(pcie->dev, 1328 "Failed to enable controller %u: %d\n", pcie->cid, ret); 1329 return ret; 1330 } 1331 1332 ret = tegra_pcie_enable_slot_regulators(pcie); 1333 if (ret < 0) 1334 goto fail_slot_reg_en; 1335 1336 ret = regulator_enable(pcie->pex_ctl_supply); 1337 if (ret < 0) { 1338 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); 1339 goto fail_reg_en; 1340 } 1341 1342 ret = clk_prepare_enable(pcie->core_clk); 1343 if (ret) { 1344 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); 1345 goto fail_core_clk; 1346 } 1347 1348 ret = reset_control_deassert(pcie->core_apb_rst); 1349 if (ret) { 1350 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", 1351 ret); 1352 goto fail_core_apb_rst; 1353 } 1354 1355 if (en_hw_hot_rst) { 1356 /* Enable HW_HOT_RST mode */ 1357 val = appl_readl(pcie, APPL_CTRL); 1358 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 1359 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 1360 val |= APPL_CTRL_HW_HOT_RST_EN; 1361 appl_writel(pcie, val, APPL_CTRL); 1362 } 1363 1364 ret = tegra_pcie_enable_phy(pcie); 1365 if (ret) { 1366 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); 1367 goto fail_phy; 1368 } 1369 1370 /* Update CFG base address */ 1371 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1372 APPL_CFG_BASE_ADDR); 1373 1374 /* Configure this core for RP mode operation */ 1375 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE); 1376 1377 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1378 1379 val = appl_readl(pcie, APPL_CTRL); 1380 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); 1381 1382 val = appl_readl(pcie, APPL_CFG_MISC); 1383 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1384 appl_writel(pcie, val, APPL_CFG_MISC); 1385 1386 if (!pcie->supports_clkreq) { 1387 val = appl_readl(pcie, APPL_PINMUX); 1388 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; 1389 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; 1390 appl_writel(pcie, val, APPL_PINMUX); 1391 } 1392 1393 /* Update iATU_DMA base address */ 1394 appl_writel(pcie, 1395 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1396 APPL_CFG_IATU_DMA_BASE_ADDR); 1397 1398 reset_control_deassert(pcie->core_rst); 1399 1400 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1401 PCI_CAP_ID_EXP); 1402 1403 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ 1404 if (!pcie->supports_clkreq) { 1405 disable_aspm_l11(pcie); 1406 disable_aspm_l12(pcie); 1407 } 1408 1409 return ret; 1410 1411 fail_phy: 1412 reset_control_assert(pcie->core_apb_rst); 1413 fail_core_apb_rst: 1414 clk_disable_unprepare(pcie->core_clk); 1415 fail_core_clk: 1416 regulator_disable(pcie->pex_ctl_supply); 1417 fail_reg_en: 1418 tegra_pcie_disable_slot_regulators(pcie); 1419 fail_slot_reg_en: 1420 tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1421 1422 return ret; 1423 } 1424 1425 static int __deinit_controller(struct tegra_pcie_dw *pcie) 1426 { 1427 int ret; 1428 1429 ret = reset_control_assert(pcie->core_rst); 1430 if (ret) { 1431 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", 1432 ret); 1433 return ret; 1434 } 1435 1436 tegra_pcie_disable_phy(pcie); 1437 1438 ret = reset_control_assert(pcie->core_apb_rst); 1439 if (ret) { 1440 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); 1441 return ret; 1442 } 1443 1444 clk_disable_unprepare(pcie->core_clk); 1445 1446 ret = regulator_disable(pcie->pex_ctl_supply); 1447 if (ret) { 1448 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); 1449 return ret; 1450 } 1451 1452 tegra_pcie_disable_slot_regulators(pcie); 1453 1454 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1455 if (ret) { 1456 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", 1457 pcie->cid, ret); 1458 return ret; 1459 } 1460 1461 return ret; 1462 } 1463 1464 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) 1465 { 1466 struct dw_pcie *pci = &pcie->pci; 1467 struct pcie_port *pp = &pci->pp; 1468 int ret; 1469 1470 ret = tegra_pcie_config_controller(pcie, false); 1471 if (ret < 0) 1472 return ret; 1473 1474 pp->ops = &tegra_pcie_dw_host_ops; 1475 1476 ret = dw_pcie_host_init(pp); 1477 if (ret < 0) { 1478 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); 1479 goto fail_host_init; 1480 } 1481 1482 return 0; 1483 1484 fail_host_init: 1485 return __deinit_controller(pcie); 1486 } 1487 1488 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) 1489 { 1490 u32 val; 1491 1492 if (!tegra_pcie_dw_link_up(&pcie->pci)) 1493 return 0; 1494 1495 val = appl_readl(pcie, APPL_RADM_STATUS); 1496 val |= APPL_PM_XMT_TURNOFF_STATE; 1497 appl_writel(pcie, val, APPL_RADM_STATUS); 1498 1499 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, 1500 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, 1501 1, PME_ACK_TIMEOUT); 1502 } 1503 1504 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) 1505 { 1506 u32 data; 1507 int err; 1508 1509 if (!tegra_pcie_dw_link_up(&pcie->pci)) { 1510 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); 1511 return; 1512 } 1513 1514 if (tegra_pcie_try_link_l2(pcie)) { 1515 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); 1516 /* 1517 * TX lane clock freq will reset to Gen1 only if link is in L2 1518 * or detect state. 1519 * So apply pex_rst to end point to force RP to go into detect 1520 * state 1521 */ 1522 data = appl_readl(pcie, APPL_PINMUX); 1523 data &= ~APPL_PINMUX_PEX_RST; 1524 appl_writel(pcie, data, APPL_PINMUX); 1525 1526 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, 1527 data, 1528 ((data & 1529 APPL_DEBUG_LTSSM_STATE_MASK) >> 1530 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1531 LTSSM_STATE_PRE_DETECT, 1532 1, LTSSM_TIMEOUT); 1533 if (err) { 1534 dev_info(pcie->dev, "Link didn't go to detect state\n"); 1535 } else { 1536 /* Disable LTSSM after link is in detect state */ 1537 data = appl_readl(pcie, APPL_CTRL); 1538 data &= ~APPL_CTRL_LTSSM_EN; 1539 appl_writel(pcie, data, APPL_CTRL); 1540 } 1541 } 1542 /* 1543 * DBI registers may not be accessible after this as PLL-E would be 1544 * down depending on how CLKREQ is pulled by end point 1545 */ 1546 data = appl_readl(pcie, APPL_PINMUX); 1547 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE); 1548 /* Cut REFCLK to slot */ 1549 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1550 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1551 appl_writel(pcie, data, APPL_PINMUX); 1552 } 1553 1554 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1555 { 1556 tegra_pcie_downstream_dev_to_D0(pcie); 1557 dw_pcie_host_deinit(&pcie->pci.pp); 1558 tegra_pcie_dw_pme_turnoff(pcie); 1559 1560 return __deinit_controller(pcie); 1561 } 1562 1563 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) 1564 { 1565 struct pcie_port *pp = &pcie->pci.pp; 1566 struct device *dev = pcie->dev; 1567 char *name; 1568 int ret; 1569 1570 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1571 pp->msi_irq = of_irq_get_byname(dev->of_node, "msi"); 1572 if (!pp->msi_irq) { 1573 dev_err(dev, "Failed to get MSI interrupt\n"); 1574 return -ENODEV; 1575 } 1576 } 1577 1578 pm_runtime_enable(dev); 1579 1580 ret = pm_runtime_get_sync(dev); 1581 if (ret < 0) { 1582 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1583 ret); 1584 goto fail_pm_get_sync; 1585 } 1586 1587 ret = pinctrl_pm_select_default_state(dev); 1588 if (ret < 0) { 1589 dev_err(dev, "Failed to configure sideband pins: %d\n", ret); 1590 goto fail_pm_get_sync; 1591 } 1592 1593 tegra_pcie_init_controller(pcie); 1594 1595 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); 1596 if (!pcie->link_state) { 1597 ret = -ENOMEDIUM; 1598 goto fail_host_init; 1599 } 1600 1601 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1602 if (!name) { 1603 ret = -ENOMEM; 1604 goto fail_host_init; 1605 } 1606 1607 pcie->debugfs = debugfs_create_dir(name, NULL); 1608 if (!pcie->debugfs) 1609 dev_err(dev, "Failed to create debugfs\n"); 1610 else 1611 init_debugfs(pcie); 1612 1613 return ret; 1614 1615 fail_host_init: 1616 tegra_pcie_deinit_controller(pcie); 1617 fail_pm_get_sync: 1618 pm_runtime_put_sync(dev); 1619 pm_runtime_disable(dev); 1620 return ret; 1621 } 1622 1623 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) 1624 { 1625 u32 val; 1626 int ret; 1627 1628 if (pcie->ep_state == EP_STATE_DISABLED) 1629 return; 1630 1631 /* Disable LTSSM */ 1632 val = appl_readl(pcie, APPL_CTRL); 1633 val &= ~APPL_CTRL_LTSSM_EN; 1634 appl_writel(pcie, val, APPL_CTRL); 1635 1636 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, 1637 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> 1638 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1639 LTSSM_STATE_PRE_DETECT, 1640 1, LTSSM_TIMEOUT); 1641 if (ret) 1642 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); 1643 1644 reset_control_assert(pcie->core_rst); 1645 1646 tegra_pcie_disable_phy(pcie); 1647 1648 reset_control_assert(pcie->core_apb_rst); 1649 1650 clk_disable_unprepare(pcie->core_clk); 1651 1652 pm_runtime_put_sync(pcie->dev); 1653 1654 ret = tegra_pcie_bpmp_set_pll_state(pcie, false); 1655 if (ret) 1656 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); 1657 1658 pcie->ep_state = EP_STATE_DISABLED; 1659 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); 1660 } 1661 1662 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) 1663 { 1664 struct dw_pcie *pci = &pcie->pci; 1665 struct dw_pcie_ep *ep = &pci->ep; 1666 struct device *dev = pcie->dev; 1667 u32 val; 1668 int ret; 1669 1670 if (pcie->ep_state == EP_STATE_ENABLED) 1671 return; 1672 1673 ret = pm_runtime_get_sync(dev); 1674 if (ret < 0) { 1675 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1676 ret); 1677 return; 1678 } 1679 1680 ret = tegra_pcie_bpmp_set_pll_state(pcie, true); 1681 if (ret) { 1682 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret); 1683 goto fail_pll_init; 1684 } 1685 1686 ret = clk_prepare_enable(pcie->core_clk); 1687 if (ret) { 1688 dev_err(dev, "Failed to enable core clock: %d\n", ret); 1689 goto fail_core_clk_enable; 1690 } 1691 1692 ret = reset_control_deassert(pcie->core_apb_rst); 1693 if (ret) { 1694 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret); 1695 goto fail_core_apb_rst; 1696 } 1697 1698 ret = tegra_pcie_enable_phy(pcie); 1699 if (ret) { 1700 dev_err(dev, "Failed to enable PHY: %d\n", ret); 1701 goto fail_phy; 1702 } 1703 1704 /* Clear any stale interrupt statuses */ 1705 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 1706 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 1707 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 1708 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 1709 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 1710 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 1711 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 1712 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 1713 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 1714 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 1715 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 1716 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 1717 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 1718 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 1719 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 1720 1721 /* configure this core for EP mode operation */ 1722 val = appl_readl(pcie, APPL_DM_TYPE); 1723 val &= ~APPL_DM_TYPE_MASK; 1724 val |= APPL_DM_TYPE_EP; 1725 appl_writel(pcie, val, APPL_DM_TYPE); 1726 1727 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1728 1729 val = appl_readl(pcie, APPL_CTRL); 1730 val |= APPL_CTRL_SYS_PRE_DET_STATE; 1731 val |= APPL_CTRL_HW_HOT_RST_EN; 1732 appl_writel(pcie, val, APPL_CTRL); 1733 1734 val = appl_readl(pcie, APPL_CFG_MISC); 1735 val |= APPL_CFG_MISC_SLV_EP_MODE; 1736 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1737 appl_writel(pcie, val, APPL_CFG_MISC); 1738 1739 val = appl_readl(pcie, APPL_PINMUX); 1740 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1741 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1742 appl_writel(pcie, val, APPL_PINMUX); 1743 1744 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1745 APPL_CFG_BASE_ADDR); 1746 1747 appl_writel(pcie, pcie->atu_dma_res->start & 1748 APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1749 APPL_CFG_IATU_DMA_BASE_ADDR); 1750 1751 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 1752 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 1753 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 1754 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; 1755 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 1756 1757 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 1758 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN; 1759 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; 1760 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 1761 1762 reset_control_deassert(pcie->core_rst); 1763 1764 if (pcie->update_fc_fixup) { 1765 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 1766 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 1767 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 1768 } 1769 1770 config_gen3_gen4_eq_presets(pcie); 1771 1772 init_host_aspm(pcie); 1773 1774 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 1775 if (!pcie->supports_clkreq) { 1776 disable_aspm_l11(pcie); 1777 disable_aspm_l12(pcie); 1778 } 1779 1780 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 1781 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 1782 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 1783 1784 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1785 PCI_CAP_ID_EXP); 1786 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 1787 1788 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); 1789 val |= MSIX_ADDR_MATCH_LOW_OFF_EN; 1790 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); 1791 val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); 1792 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); 1793 1794 ret = dw_pcie_ep_init_complete(ep); 1795 if (ret) { 1796 dev_err(dev, "Failed to complete initialization: %d\n", ret); 1797 goto fail_init_complete; 1798 } 1799 1800 dw_pcie_ep_init_notify(ep); 1801 1802 /* Enable LTSSM */ 1803 val = appl_readl(pcie, APPL_CTRL); 1804 val |= APPL_CTRL_LTSSM_EN; 1805 appl_writel(pcie, val, APPL_CTRL); 1806 1807 pcie->ep_state = EP_STATE_ENABLED; 1808 dev_dbg(dev, "Initialization of endpoint is completed\n"); 1809 1810 return; 1811 1812 fail_init_complete: 1813 reset_control_assert(pcie->core_rst); 1814 tegra_pcie_disable_phy(pcie); 1815 fail_phy: 1816 reset_control_assert(pcie->core_apb_rst); 1817 fail_core_apb_rst: 1818 clk_disable_unprepare(pcie->core_clk); 1819 fail_core_clk_enable: 1820 tegra_pcie_bpmp_set_pll_state(pcie, false); 1821 fail_pll_init: 1822 pm_runtime_put_sync(dev); 1823 } 1824 1825 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) 1826 { 1827 struct tegra_pcie_dw *pcie = arg; 1828 1829 if (gpiod_get_value(pcie->pex_rst_gpiod)) 1830 pex_ep_event_pex_rst_assert(pcie); 1831 else 1832 pex_ep_event_pex_rst_deassert(pcie); 1833 1834 return IRQ_HANDLED; 1835 } 1836 1837 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) 1838 { 1839 /* Tegra194 supports only INTA */ 1840 if (irq > 1) 1841 return -EINVAL; 1842 1843 appl_writel(pcie, 1, APPL_LEGACY_INTX); 1844 usleep_range(1000, 2000); 1845 appl_writel(pcie, 0, APPL_LEGACY_INTX); 1846 return 0; 1847 } 1848 1849 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) 1850 { 1851 if (unlikely(irq > 31)) 1852 return -EINVAL; 1853 1854 appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1); 1855 1856 return 0; 1857 } 1858 1859 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq) 1860 { 1861 struct dw_pcie_ep *ep = &pcie->pci.ep; 1862 1863 writel(irq, ep->msi_mem); 1864 1865 return 0; 1866 } 1867 1868 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1869 enum pci_epc_irq_type type, 1870 u16 interrupt_num) 1871 { 1872 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1873 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1874 1875 switch (type) { 1876 case PCI_EPC_IRQ_LEGACY: 1877 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); 1878 1879 case PCI_EPC_IRQ_MSI: 1880 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num); 1881 1882 case PCI_EPC_IRQ_MSIX: 1883 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num); 1884 1885 default: 1886 dev_err(pci->dev, "Unknown IRQ type\n"); 1887 return -EPERM; 1888 } 1889 1890 return 0; 1891 } 1892 1893 static const struct pci_epc_features tegra_pcie_epc_features = { 1894 .linkup_notifier = true, 1895 .core_init_notifier = true, 1896 .msi_capable = false, 1897 .msix_capable = false, 1898 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5, 1899 .bar_fixed_64bit = 1 << BAR_0, 1900 .bar_fixed_size[0] = SZ_1M, 1901 }; 1902 1903 static const struct pci_epc_features* 1904 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) 1905 { 1906 return &tegra_pcie_epc_features; 1907 } 1908 1909 static struct dw_pcie_ep_ops pcie_ep_ops = { 1910 .raise_irq = tegra_pcie_ep_raise_irq, 1911 .get_features = tegra_pcie_ep_get_features, 1912 }; 1913 1914 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, 1915 struct platform_device *pdev) 1916 { 1917 struct dw_pcie *pci = &pcie->pci; 1918 struct device *dev = pcie->dev; 1919 struct dw_pcie_ep *ep; 1920 struct resource *res; 1921 char *name; 1922 int ret; 1923 1924 ep = &pci->ep; 1925 ep->ops = &pcie_ep_ops; 1926 1927 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1928 if (!res) 1929 return -EINVAL; 1930 1931 ep->phys_base = res->start; 1932 ep->addr_size = resource_size(res); 1933 ep->page_size = SZ_64K; 1934 1935 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); 1936 if (ret < 0) { 1937 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n", 1938 ret); 1939 return ret; 1940 } 1941 1942 ret = gpiod_to_irq(pcie->pex_rst_gpiod); 1943 if (ret < 0) { 1944 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret); 1945 return ret; 1946 } 1947 pcie->pex_rst_irq = (unsigned int)ret; 1948 1949 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq", 1950 pcie->cid); 1951 if (!name) { 1952 dev_err(dev, "Failed to create PERST IRQ string\n"); 1953 return -ENOMEM; 1954 } 1955 1956 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); 1957 1958 pcie->ep_state = EP_STATE_DISABLED; 1959 1960 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, 1961 tegra_pcie_ep_pex_rst_irq, 1962 IRQF_TRIGGER_RISING | 1963 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1964 name, (void *)pcie); 1965 if (ret < 0) { 1966 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); 1967 return ret; 1968 } 1969 1970 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work", 1971 pcie->cid); 1972 if (!name) { 1973 dev_err(dev, "Failed to create PCIe EP work thread string\n"); 1974 return -ENOMEM; 1975 } 1976 1977 pm_runtime_enable(dev); 1978 1979 ret = dw_pcie_ep_init(ep); 1980 if (ret) { 1981 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n", 1982 ret); 1983 return ret; 1984 } 1985 1986 return 0; 1987 } 1988 1989 static int tegra_pcie_dw_probe(struct platform_device *pdev) 1990 { 1991 const struct tegra_pcie_dw_of_data *data; 1992 struct device *dev = &pdev->dev; 1993 struct resource *atu_dma_res; 1994 struct tegra_pcie_dw *pcie; 1995 struct resource *dbi_res; 1996 struct pcie_port *pp; 1997 struct dw_pcie *pci; 1998 struct phy **phys; 1999 char *name; 2000 int ret; 2001 u32 i; 2002 2003 data = of_device_get_match_data(dev); 2004 2005 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 2006 if (!pcie) 2007 return -ENOMEM; 2008 2009 pci = &pcie->pci; 2010 pci->dev = &pdev->dev; 2011 pci->ops = &tegra_dw_pcie_ops; 2012 pci->n_fts[0] = N_FTS_VAL; 2013 pci->n_fts[1] = FTS_VAL; 2014 2015 pp = &pci->pp; 2016 pcie->dev = &pdev->dev; 2017 pcie->mode = (enum dw_pcie_device_mode)data->mode; 2018 2019 ret = tegra_pcie_dw_parse_dt(pcie); 2020 if (ret < 0) { 2021 const char *level = KERN_ERR; 2022 2023 if (ret == -EPROBE_DEFER) 2024 level = KERN_DEBUG; 2025 2026 dev_printk(level, dev, 2027 dev_fmt("Failed to parse device tree: %d\n"), 2028 ret); 2029 return ret; 2030 } 2031 2032 ret = tegra_pcie_get_slot_regulators(pcie); 2033 if (ret < 0) { 2034 const char *level = KERN_ERR; 2035 2036 if (ret == -EPROBE_DEFER) 2037 level = KERN_DEBUG; 2038 2039 dev_printk(level, dev, 2040 dev_fmt("Failed to get slot regulators: %d\n"), 2041 ret); 2042 return ret; 2043 } 2044 2045 if (pcie->pex_refclk_sel_gpiod) 2046 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); 2047 2048 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); 2049 if (IS_ERR(pcie->pex_ctl_supply)) { 2050 ret = PTR_ERR(pcie->pex_ctl_supply); 2051 if (ret != -EPROBE_DEFER) 2052 dev_err(dev, "Failed to get regulator: %ld\n", 2053 PTR_ERR(pcie->pex_ctl_supply)); 2054 return ret; 2055 } 2056 2057 pcie->core_clk = devm_clk_get(dev, "core"); 2058 if (IS_ERR(pcie->core_clk)) { 2059 dev_err(dev, "Failed to get core clock: %ld\n", 2060 PTR_ERR(pcie->core_clk)); 2061 return PTR_ERR(pcie->core_clk); 2062 } 2063 2064 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2065 "appl"); 2066 if (!pcie->appl_res) { 2067 dev_err(dev, "Failed to find \"appl\" region\n"); 2068 return -ENODEV; 2069 } 2070 2071 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); 2072 if (IS_ERR(pcie->appl_base)) 2073 return PTR_ERR(pcie->appl_base); 2074 2075 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); 2076 if (IS_ERR(pcie->core_apb_rst)) { 2077 dev_err(dev, "Failed to get APB reset: %ld\n", 2078 PTR_ERR(pcie->core_apb_rst)); 2079 return PTR_ERR(pcie->core_apb_rst); 2080 } 2081 2082 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); 2083 if (!phys) 2084 return -ENOMEM; 2085 2086 for (i = 0; i < pcie->phy_count; i++) { 2087 name = kasprintf(GFP_KERNEL, "p2u-%u", i); 2088 if (!name) { 2089 dev_err(dev, "Failed to create P2U string\n"); 2090 return -ENOMEM; 2091 } 2092 phys[i] = devm_phy_get(dev, name); 2093 kfree(name); 2094 if (IS_ERR(phys[i])) { 2095 ret = PTR_ERR(phys[i]); 2096 if (ret != -EPROBE_DEFER) 2097 dev_err(dev, "Failed to get PHY: %d\n", ret); 2098 return ret; 2099 } 2100 } 2101 2102 pcie->phys = phys; 2103 2104 dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 2105 if (!dbi_res) { 2106 dev_err(dev, "Failed to find \"dbi\" region\n"); 2107 return -ENODEV; 2108 } 2109 pcie->dbi_res = dbi_res; 2110 2111 pci->dbi_base = devm_ioremap_resource(dev, dbi_res); 2112 if (IS_ERR(pci->dbi_base)) 2113 return PTR_ERR(pci->dbi_base); 2114 2115 /* Tegra HW locates DBI2 at a fixed offset from DBI */ 2116 pci->dbi_base2 = pci->dbi_base + 0x1000; 2117 2118 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2119 "atu_dma"); 2120 if (!atu_dma_res) { 2121 dev_err(dev, "Failed to find \"atu_dma\" region\n"); 2122 return -ENODEV; 2123 } 2124 pcie->atu_dma_res = atu_dma_res; 2125 2126 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); 2127 if (IS_ERR(pci->atu_base)) 2128 return PTR_ERR(pci->atu_base); 2129 2130 pcie->core_rst = devm_reset_control_get(dev, "core"); 2131 if (IS_ERR(pcie->core_rst)) { 2132 dev_err(dev, "Failed to get core reset: %ld\n", 2133 PTR_ERR(pcie->core_rst)); 2134 return PTR_ERR(pcie->core_rst); 2135 } 2136 2137 pp->irq = platform_get_irq_byname(pdev, "intr"); 2138 if (pp->irq < 0) 2139 return pp->irq; 2140 2141 pcie->bpmp = tegra_bpmp_get(dev); 2142 if (IS_ERR(pcie->bpmp)) 2143 return PTR_ERR(pcie->bpmp); 2144 2145 platform_set_drvdata(pdev, pcie); 2146 2147 switch (pcie->mode) { 2148 case DW_PCIE_RC_TYPE: 2149 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, 2150 IRQF_SHARED, "tegra-pcie-intr", pcie); 2151 if (ret) { 2152 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2153 ret); 2154 goto fail; 2155 } 2156 2157 ret = tegra_pcie_config_rp(pcie); 2158 if (ret && ret != -ENOMEDIUM) 2159 goto fail; 2160 else 2161 return 0; 2162 break; 2163 2164 case DW_PCIE_EP_TYPE: 2165 ret = devm_request_threaded_irq(dev, pp->irq, 2166 tegra_pcie_ep_hard_irq, 2167 tegra_pcie_ep_irq_thread, 2168 IRQF_SHARED | IRQF_ONESHOT, 2169 "tegra-pcie-ep-intr", pcie); 2170 if (ret) { 2171 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2172 ret); 2173 goto fail; 2174 } 2175 2176 ret = tegra_pcie_config_ep(pcie, pdev); 2177 if (ret < 0) 2178 goto fail; 2179 break; 2180 2181 default: 2182 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); 2183 } 2184 2185 fail: 2186 tegra_bpmp_put(pcie->bpmp); 2187 return ret; 2188 } 2189 2190 static int tegra_pcie_dw_remove(struct platform_device *pdev) 2191 { 2192 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2193 2194 if (!pcie->link_state) 2195 return 0; 2196 2197 debugfs_remove_recursive(pcie->debugfs); 2198 tegra_pcie_deinit_controller(pcie); 2199 pm_runtime_put_sync(pcie->dev); 2200 pm_runtime_disable(pcie->dev); 2201 tegra_bpmp_put(pcie->bpmp); 2202 if (pcie->pex_refclk_sel_gpiod) 2203 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); 2204 2205 return 0; 2206 } 2207 2208 static int tegra_pcie_dw_suspend_late(struct device *dev) 2209 { 2210 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2211 u32 val; 2212 2213 if (!pcie->link_state) 2214 return 0; 2215 2216 /* Enable HW_HOT_RST mode */ 2217 val = appl_readl(pcie, APPL_CTRL); 2218 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2219 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2220 val |= APPL_CTRL_HW_HOT_RST_EN; 2221 appl_writel(pcie, val, APPL_CTRL); 2222 2223 return 0; 2224 } 2225 2226 static int tegra_pcie_dw_suspend_noirq(struct device *dev) 2227 { 2228 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2229 2230 if (!pcie->link_state) 2231 return 0; 2232 2233 /* Save MSI interrupt vector */ 2234 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, 2235 PORT_LOGIC_MSI_CTRL_INT_0_EN); 2236 tegra_pcie_downstream_dev_to_D0(pcie); 2237 tegra_pcie_dw_pme_turnoff(pcie); 2238 2239 return __deinit_controller(pcie); 2240 } 2241 2242 static int tegra_pcie_dw_resume_noirq(struct device *dev) 2243 { 2244 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2245 int ret; 2246 2247 if (!pcie->link_state) 2248 return 0; 2249 2250 ret = tegra_pcie_config_controller(pcie, true); 2251 if (ret < 0) 2252 return ret; 2253 2254 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); 2255 if (ret < 0) { 2256 dev_err(dev, "Failed to init host: %d\n", ret); 2257 goto fail_host_init; 2258 } 2259 2260 /* Restore MSI interrupt vector */ 2261 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, 2262 pcie->msi_ctrl_int); 2263 2264 return 0; 2265 2266 fail_host_init: 2267 return __deinit_controller(pcie); 2268 } 2269 2270 static int tegra_pcie_dw_resume_early(struct device *dev) 2271 { 2272 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2273 u32 val; 2274 2275 if (!pcie->link_state) 2276 return 0; 2277 2278 /* Disable HW_HOT_RST mode */ 2279 val = appl_readl(pcie, APPL_CTRL); 2280 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2281 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2282 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << 2283 APPL_CTRL_HW_HOT_RST_MODE_SHIFT; 2284 val &= ~APPL_CTRL_HW_HOT_RST_EN; 2285 appl_writel(pcie, val, APPL_CTRL); 2286 2287 return 0; 2288 } 2289 2290 static void tegra_pcie_dw_shutdown(struct platform_device *pdev) 2291 { 2292 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2293 2294 if (!pcie->link_state) 2295 return; 2296 2297 debugfs_remove_recursive(pcie->debugfs); 2298 tegra_pcie_downstream_dev_to_D0(pcie); 2299 2300 disable_irq(pcie->pci.pp.irq); 2301 if (IS_ENABLED(CONFIG_PCI_MSI)) 2302 disable_irq(pcie->pci.pp.msi_irq); 2303 2304 tegra_pcie_dw_pme_turnoff(pcie); 2305 __deinit_controller(pcie); 2306 } 2307 2308 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { 2309 .mode = DW_PCIE_RC_TYPE, 2310 }; 2311 2312 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = { 2313 .mode = DW_PCIE_EP_TYPE, 2314 }; 2315 2316 static const struct of_device_id tegra_pcie_dw_of_match[] = { 2317 { 2318 .compatible = "nvidia,tegra194-pcie", 2319 .data = &tegra_pcie_dw_rc_of_data, 2320 }, 2321 { 2322 .compatible = "nvidia,tegra194-pcie-ep", 2323 .data = &tegra_pcie_dw_ep_of_data, 2324 }, 2325 {}, 2326 }; 2327 2328 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = { 2329 .suspend_late = tegra_pcie_dw_suspend_late, 2330 .suspend_noirq = tegra_pcie_dw_suspend_noirq, 2331 .resume_noirq = tegra_pcie_dw_resume_noirq, 2332 .resume_early = tegra_pcie_dw_resume_early, 2333 }; 2334 2335 static struct platform_driver tegra_pcie_dw_driver = { 2336 .probe = tegra_pcie_dw_probe, 2337 .remove = tegra_pcie_dw_remove, 2338 .shutdown = tegra_pcie_dw_shutdown, 2339 .driver = { 2340 .name = "tegra194-pcie", 2341 .pm = &tegra_pcie_dw_pm_ops, 2342 .of_match_table = tegra_pcie_dw_of_match, 2343 }, 2344 }; 2345 module_platform_driver(tegra_pcie_dw_driver); 2346 2347 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); 2348 2349 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 2350 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); 2351 MODULE_LICENSE("GPL v2"); 2352