1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for Tegra194 SoC 4 * 5 * Copyright (C) 2019 NVIDIA Corporation. 6 * 7 * Author: Vidya Sagar <vidyas@nvidia.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/reset.h> 31 #include <linux/resource.h> 32 #include <linux/types.h> 33 #include "pcie-designware.h" 34 #include <soc/tegra/bpmp.h> 35 #include <soc/tegra/bpmp-abi.h> 36 #include "../../pci.h" 37 38 #define APPL_PINMUX 0x0 39 #define APPL_PINMUX_PEX_RST BIT(0) 40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) 41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) 42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) 43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) 44 45 #define APPL_CTRL 0x4 46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) 47 #define APPL_CTRL_LTSSM_EN BIT(7) 48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20) 49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) 50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22 51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 52 53 #define APPL_INTR_EN_L0_0 0x8 54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0) 55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4) 56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8) 57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15) 58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19) 59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30) 60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31) 61 62 #define APPL_INTR_STATUS_L0 0xC 63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0) 64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8) 65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15) 66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16) 67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18) 68 69 #define APPL_INTR_EN_L1_0_0 0x1C 70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1) 71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3) 72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30) 73 74 #define APPL_INTR_STATUS_L1_0_0 0x20 75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1) 76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3) 77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30) 78 79 #define APPL_INTR_STATUS_L1_1 0x2C 80 #define APPL_INTR_STATUS_L1_2 0x30 81 #define APPL_INTR_STATUS_L1_3 0x34 82 #define APPL_INTR_STATUS_L1_6 0x3C 83 #define APPL_INTR_STATUS_L1_7 0x40 84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1) 85 86 #define APPL_INTR_EN_L1_8_0 0x44 87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) 88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) 89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) 90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) 91 92 #define APPL_INTR_STATUS_L1_8_0 0x4C 93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6) 94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2) 95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3) 96 97 #define APPL_INTR_STATUS_L1_9 0x54 98 #define APPL_INTR_STATUS_L1_10 0x58 99 #define APPL_INTR_STATUS_L1_11 0x64 100 #define APPL_INTR_STATUS_L1_13 0x74 101 #define APPL_INTR_STATUS_L1_14 0x78 102 #define APPL_INTR_STATUS_L1_15 0x7C 103 #define APPL_INTR_STATUS_L1_17 0x88 104 105 #define APPL_INTR_EN_L1_18 0x90 106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2) 107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 109 110 #define APPL_INTR_STATUS_L1_18 0x94 111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2) 112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 114 115 #define APPL_MSI_CTRL_1 0xAC 116 117 #define APPL_MSI_CTRL_2 0xB0 118 119 #define APPL_LEGACY_INTX 0xB8 120 121 #define APPL_LTR_MSG_1 0xC4 122 #define LTR_MSG_REQ BIT(15) 123 #define LTR_MST_NO_SNOOP_SHIFT 16 124 125 #define APPL_LTR_MSG_2 0xC8 126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) 127 128 #define APPL_LINK_STATUS 0xCC 129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0) 130 131 #define APPL_DEBUG 0xD0 132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) 133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) 135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 136 #define LTSSM_STATE_PRE_DETECT 5 137 138 #define APPL_RADM_STATUS 0xE4 139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) 140 141 #define APPL_DM_TYPE 0x100 142 #define APPL_DM_TYPE_MASK GENMASK(3, 0) 143 #define APPL_DM_TYPE_RP 0x4 144 #define APPL_DM_TYPE_EP 0x0 145 146 #define APPL_CFG_BASE_ADDR 0x104 147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12) 148 149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108 150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18) 151 152 #define APPL_CFG_MISC 0x110 153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) 154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10) 155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10 156 #define APPL_CFG_MISC_ARCACHE_VAL 3 157 158 #define APPL_CFG_SLCG_OVERRIDE 0x114 159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0) 160 161 #define APPL_CAR_RESET_OVRD 0x12C 162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0) 163 164 #define IO_BASE_IO_DECODE BIT(0) 165 #define IO_BASE_IO_DECODE_BIT8 BIT(8) 166 167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0) 168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) 169 170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718 171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19) 172 173 #define EVENT_COUNTER_ALL_CLEAR 0x3 174 #define EVENT_COUNTER_ENABLE_ALL 0x7 175 #define EVENT_COUNTER_ENABLE_SHIFT 2 176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) 177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 180 #define EVENT_COUNTER_EVENT_L1 0x5 181 #define EVENT_COUNTER_EVENT_L1_1 0x7 182 #define EVENT_COUNTER_EVENT_L1_2 0x8 183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 184 #define EVENT_COUNTER_GROUP_5 0x5 185 186 #define N_FTS_VAL 52 187 #define FTS_VAL 52 188 189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 190 191 #define GEN3_EQ_CONTROL_OFF 0x8a8 192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8 193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) 194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) 195 196 #define GEN3_RELATED_OFF 0x890 197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) 198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 201 202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) 205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0 206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 208 209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940 210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) 211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) 212 213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944 214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0) 215 216 #define PORT_LOGIC_MSIX_DOORBELL 0x948 217 218 #define CAP_SPCIE_CAP_OFF 0x154 219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0) 220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) 221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 222 223 #define PME_ACK_TIMEOUT 10000 224 225 #define LTSSM_TIMEOUT 50000 /* 50ms */ 226 227 #define GEN3_GEN4_EQ_PRESET_INIT 5 228 229 #define GEN1_CORE_CLK_FREQ 62500000 230 #define GEN2_CORE_CLK_FREQ 125000000 231 #define GEN3_CORE_CLK_FREQ 250000000 232 #define GEN4_CORE_CLK_FREQ 500000000 233 234 #define LTR_MSG_TIMEOUT (100 * 1000) 235 236 #define PERST_DEBOUNCE_TIME (5 * 1000) 237 238 #define EP_STATE_DISABLED 0 239 #define EP_STATE_ENABLED 1 240 241 static const unsigned int pcie_gen_freq[] = { 242 GEN1_CORE_CLK_FREQ, 243 GEN2_CORE_CLK_FREQ, 244 GEN3_CORE_CLK_FREQ, 245 GEN4_CORE_CLK_FREQ 246 }; 247 248 static const u32 event_cntr_ctrl_offset[] = { 249 0x1d8, 250 0x1a8, 251 0x1a8, 252 0x1a8, 253 0x1c4, 254 0x1d8 255 }; 256 257 static const u32 event_cntr_data_offset[] = { 258 0x1dc, 259 0x1ac, 260 0x1ac, 261 0x1ac, 262 0x1c8, 263 0x1dc 264 }; 265 266 struct tegra_pcie_dw { 267 struct device *dev; 268 struct resource *appl_res; 269 struct resource *dbi_res; 270 struct resource *atu_dma_res; 271 void __iomem *appl_base; 272 struct clk *core_clk; 273 struct reset_control *core_apb_rst; 274 struct reset_control *core_rst; 275 struct dw_pcie pci; 276 struct tegra_bpmp *bpmp; 277 278 enum dw_pcie_device_mode mode; 279 280 bool supports_clkreq; 281 bool enable_cdm_check; 282 bool link_state; 283 bool update_fc_fixup; 284 u8 init_link_width; 285 u32 msi_ctrl_int; 286 u32 num_lanes; 287 u32 cid; 288 u32 cfg_link_cap_l1sub; 289 u32 pcie_cap_base; 290 u32 aspm_cmrt; 291 u32 aspm_pwr_on_t; 292 u32 aspm_l0s_enter_lat; 293 294 struct regulator *pex_ctl_supply; 295 struct regulator *slot_ctl_3v3; 296 struct regulator *slot_ctl_12v; 297 298 unsigned int phy_count; 299 struct phy **phys; 300 301 struct dentry *debugfs; 302 303 /* Endpoint mode specific */ 304 struct gpio_desc *pex_rst_gpiod; 305 struct gpio_desc *pex_refclk_sel_gpiod; 306 unsigned int pex_rst_irq; 307 int ep_state; 308 }; 309 310 struct tegra_pcie_dw_of_data { 311 enum dw_pcie_device_mode mode; 312 }; 313 314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) 315 { 316 return container_of(pci, struct tegra_pcie_dw, pci); 317 } 318 319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, 320 const u32 reg) 321 { 322 writel_relaxed(value, pcie->appl_base + reg); 323 } 324 325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) 326 { 327 return readl_relaxed(pcie->appl_base + reg); 328 } 329 330 struct tegra_pcie_soc { 331 enum dw_pcie_device_mode mode; 332 }; 333 334 static void apply_bad_link_workaround(struct pcie_port *pp) 335 { 336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 338 u32 current_link_width; 339 u16 val; 340 341 /* 342 * NOTE:- Since this scenario is uncommon and link as such is not 343 * stable anyway, not waiting to confirm if link is really 344 * transitioning to Gen-2 speed 345 */ 346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 347 if (val & PCI_EXP_LNKSTA_LBMS) { 348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> 349 PCI_EXP_LNKSTA_NLW_SHIFT; 350 if (pcie->init_link_width > current_link_width) { 351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); 352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 353 PCI_EXP_LNKCTL2); 354 val &= ~PCI_EXP_LNKCTL2_TLS; 355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT; 356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 357 PCI_EXP_LNKCTL2, val); 358 359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 360 PCI_EXP_LNKCTL); 361 val |= PCI_EXP_LNKCTL_RL; 362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 363 PCI_EXP_LNKCTL, val); 364 } 365 } 366 } 367 368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) 369 { 370 struct tegra_pcie_dw *pcie = arg; 371 struct dw_pcie *pci = &pcie->pci; 372 struct pcie_port *pp = &pci->pp; 373 u32 val, tmp; 374 u16 val_w; 375 376 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 377 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 378 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 379 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) { 380 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 381 382 /* SBR & Surprise Link Down WAR */ 383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 386 udelay(1); 387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 390 391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 392 val |= PORT_LOGIC_SPEED_CHANGE; 393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 394 } 395 } 396 397 if (val & APPL_INTR_STATUS_L0_INT_INT) { 398 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); 399 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) { 400 appl_writel(pcie, 401 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS, 402 APPL_INTR_STATUS_L1_8_0); 403 apply_bad_link_workaround(pp); 404 } 405 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { 406 appl_writel(pcie, 407 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, 408 APPL_INTR_STATUS_L1_8_0); 409 410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 411 PCI_EXP_LNKSTA); 412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & 413 PCI_EXP_LNKSTA_CLS); 414 } 415 } 416 417 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 418 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { 419 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18); 420 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 421 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { 422 dev_info(pci->dev, "CDM check complete\n"); 423 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE; 424 } 425 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) { 426 dev_err(pci->dev, "CDM comparison mismatch\n"); 427 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR; 428 } 429 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) { 430 dev_err(pci->dev, "CDM Logic error\n"); 431 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; 432 } 433 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp); 434 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); 435 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp); 436 } 437 438 return IRQ_HANDLED; 439 } 440 441 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) 442 { 443 u32 val; 444 445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 460 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2); 461 462 val = appl_readl(pcie, APPL_CTRL); 463 val |= APPL_CTRL_LTSSM_EN; 464 appl_writel(pcie, val, APPL_CTRL); 465 } 466 467 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) 468 { 469 struct tegra_pcie_dw *pcie = arg; 470 struct dw_pcie *pci = &pcie->pci; 471 u32 val, speed; 472 473 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 474 PCI_EXP_LNKSTA_CLS; 475 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 476 477 /* If EP doesn't advertise L1SS, just return */ 478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 479 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2))) 480 return IRQ_HANDLED; 481 482 /* Check if BME is set to '1' */ 483 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 484 if (val & PCI_COMMAND_MASTER) { 485 ktime_t timeout; 486 487 /* 110us for both snoop and no-snoop */ 488 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; 489 val |= (val << LTR_MST_NO_SNOOP_SHIFT); 490 appl_writel(pcie, val, APPL_LTR_MSG_1); 491 492 /* Send LTR upstream */ 493 val = appl_readl(pcie, APPL_LTR_MSG_2); 494 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; 495 appl_writel(pcie, val, APPL_LTR_MSG_2); 496 497 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT); 498 for (;;) { 499 val = appl_readl(pcie, APPL_LTR_MSG_2); 500 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)) 501 break; 502 if (ktime_after(ktime_get(), timeout)) 503 break; 504 usleep_range(1000, 1100); 505 } 506 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE) 507 dev_err(pcie->dev, "Failed to send LTR message\n"); 508 } 509 510 return IRQ_HANDLED; 511 } 512 513 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) 514 { 515 struct tegra_pcie_dw *pcie = arg; 516 struct dw_pcie_ep *ep = &pcie->pci.ep; 517 int spurious = 1; 518 u32 val, tmp; 519 520 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 521 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 522 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 523 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 524 525 if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) 526 pex_ep_event_hot_rst_done(pcie); 527 528 if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { 529 tmp = appl_readl(pcie, APPL_LINK_STATUS); 530 if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { 531 dev_dbg(pcie->dev, "Link is up with Host\n"); 532 dw_pcie_ep_linkup(ep); 533 } 534 } 535 536 spurious = 0; 537 } 538 539 if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { 540 val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); 541 appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); 542 543 if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) 544 return IRQ_WAKE_THREAD; 545 546 spurious = 0; 547 } 548 549 if (spurious) { 550 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", 551 val); 552 appl_writel(pcie, val, APPL_INTR_STATUS_L0); 553 } 554 555 return IRQ_HANDLED; 556 } 557 558 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, 559 int size, u32 *val) 560 { 561 /* 562 * This is an endpoint mode specific register happen to appear even 563 * when controller is operating in root port mode and system hangs 564 * when it is accessed with link being in ASPM-L1 state. 565 * So skip accessing it altogether 566 */ 567 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { 568 *val = 0x00000000; 569 return PCIBIOS_SUCCESSFUL; 570 } 571 572 return pci_generic_config_read(bus, devfn, where, size, val); 573 } 574 575 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, 576 int size, u32 val) 577 { 578 /* 579 * This is an endpoint mode specific register happen to appear even 580 * when controller is operating in root port mode and system hangs 581 * when it is accessed with link being in ASPM-L1 state. 582 * So skip accessing it altogether 583 */ 584 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) 585 return PCIBIOS_SUCCESSFUL; 586 587 return pci_generic_config_write(bus, devfn, where, size, val); 588 } 589 590 static struct pci_ops tegra_pci_ops = { 591 .map_bus = dw_pcie_own_conf_map_bus, 592 .read = tegra_pcie_dw_rd_own_conf, 593 .write = tegra_pcie_dw_wr_own_conf, 594 }; 595 596 #if defined(CONFIG_PCIEASPM) 597 static void disable_aspm_l11(struct tegra_pcie_dw *pcie) 598 { 599 u32 val; 600 601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 602 val &= ~PCI_L1SS_CAP_ASPM_L1_1; 603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 604 } 605 606 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) 607 { 608 u32 val; 609 610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 611 val &= ~PCI_L1SS_CAP_ASPM_L1_2; 612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 613 } 614 615 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) 616 { 617 u32 val; 618 619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); 620 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); 621 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 622 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT; 623 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); 626 627 return val; 628 } 629 630 static int aspm_state_cnt(struct seq_file *s, void *data) 631 { 632 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *) 633 dev_get_drvdata(s->private); 634 u32 val; 635 636 seq_printf(s, "Tx L0s entry count : %u\n", 637 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S)); 638 639 seq_printf(s, "Rx L0s entry count : %u\n", 640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S)); 641 642 seq_printf(s, "Link L1 entry count : %u\n", 643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1)); 644 645 seq_printf(s, "Link L1.1 entry count : %u\n", 646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1)); 647 648 seq_printf(s, "Link L1.2 entry count : %u\n", 649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2)); 650 651 /* Clear all counters */ 652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], 653 EVENT_COUNTER_ALL_CLEAR); 654 655 /* Re-enable counting */ 656 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 657 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 659 660 return 0; 661 } 662 663 static void init_host_aspm(struct tegra_pcie_dw *pcie) 664 { 665 struct dw_pcie *pci = &pcie->pci; 666 u32 val; 667 668 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; 670 671 /* Enable ASPM counters */ 672 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 673 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); 675 676 /* Program T_cmrt and T_pwr_on values */ 677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 678 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); 679 val |= (pcie->aspm_cmrt << 8); 680 val |= (pcie->aspm_pwr_on_t << 19); 681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); 682 683 /* Program L0s and L1 entrance latencies */ 684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 685 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; 686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); 687 val |= PORT_AFR_ENTER_ASPM; 688 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 689 } 690 691 static void init_debugfs(struct tegra_pcie_dw *pcie) 692 { 693 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, 694 aspm_state_cnt); 695 } 696 #else 697 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; } 698 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; } 699 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; } 700 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; } 701 #endif 702 703 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) 704 { 705 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 706 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 707 u32 val; 708 u16 val_w; 709 710 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 711 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 712 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 713 714 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 715 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN; 716 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 717 718 if (pcie->enable_cdm_check) { 719 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 720 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN; 721 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 722 723 val = appl_readl(pcie, APPL_INTR_EN_L1_18); 724 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR; 725 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR; 726 appl_writel(pcie, val, APPL_INTR_EN_L1_18); 727 } 728 729 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 730 PCI_EXP_LNKSTA); 731 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> 732 PCI_EXP_LNKSTA_NLW_SHIFT; 733 734 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 735 PCI_EXP_LNKCTL); 736 val_w |= PCI_EXP_LNKCTL_LBMIE; 737 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, 738 val_w); 739 } 740 741 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) 742 { 743 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 744 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 745 u32 val; 746 747 /* Enable legacy interrupt generation */ 748 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 749 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 750 val |= APPL_INTR_EN_L0_0_INT_INT_EN; 751 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 752 753 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); 754 val |= APPL_INTR_EN_L1_8_INTX_EN; 755 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; 756 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; 757 if (IS_ENABLED(CONFIG_PCIEAER)) 758 val |= APPL_INTR_EN_L1_8_AER_INT_EN; 759 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); 760 } 761 762 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) 763 { 764 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 765 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 766 u32 val; 767 768 /* Enable MSI interrupt generation */ 769 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 770 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; 771 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN; 772 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 773 } 774 775 static void tegra_pcie_enable_interrupts(struct pcie_port *pp) 776 { 777 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 778 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 779 780 /* Clear interrupt statuses before enabling interrupts */ 781 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 782 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 796 797 tegra_pcie_enable_system_interrupts(pp); 798 tegra_pcie_enable_legacy_interrupts(pp); 799 if (IS_ENABLED(CONFIG_PCI_MSI)) 800 tegra_pcie_enable_msi_interrupts(pp); 801 } 802 803 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) 804 { 805 struct dw_pcie *pci = &pcie->pci; 806 u32 val, offset, i; 807 808 /* Program init preset */ 809 for (i = 0; i < pcie->num_lanes; i++) { 810 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2)); 811 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; 812 val |= GEN3_GEN4_EQ_PRESET_INIT; 813 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; 814 val |= (GEN3_GEN4_EQ_PRESET_INIT << 815 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT); 816 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); 817 818 offset = dw_pcie_find_ext_capability(pci, 819 PCI_EXT_CAP_ID_PL_16GT) + 820 PCI_PL_16GT_LE_CTRL; 821 val = dw_pcie_readb_dbi(pci, offset + i); 822 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; 823 val |= GEN3_GEN4_EQ_PRESET_INIT; 824 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; 825 val |= (GEN3_GEN4_EQ_PRESET_INIT << 826 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT); 827 dw_pcie_writeb_dbi(pci, offset + i, val); 828 } 829 830 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 831 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 832 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 833 834 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 835 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 836 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 837 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 838 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 839 840 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 841 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 842 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); 843 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 844 845 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 846 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 847 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 848 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 849 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 850 851 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 852 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 853 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 854 } 855 856 static void tegra_pcie_prepare_host(struct pcie_port *pp) 857 { 858 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 859 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 860 u32 val; 861 862 if (!pcie->pcie_cap_base) 863 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 864 PCI_CAP_ID_EXP); 865 866 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 867 if (!pcie->supports_clkreq) { 868 disable_aspm_l11(pcie); 869 disable_aspm_l12(pcie); 870 } 871 872 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); 873 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); 874 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); 875 876 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); 877 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; 878 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; 879 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); 880 881 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 882 883 /* Enable as 0xFFFF0001 response for CRS */ 884 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); 885 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); 886 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << 887 AMBA_ERROR_RESPONSE_CRS_SHIFT); 888 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); 889 890 /* Configure Max lane width from DT */ 891 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); 892 val &= ~PCI_EXP_LNKCAP_MLW; 893 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); 894 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); 895 896 config_gen3_gen4_eq_presets(pcie); 897 898 init_host_aspm(pcie); 899 900 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 901 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 902 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 903 904 if (pcie->update_fc_fixup) { 905 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 906 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 907 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 908 } 909 910 dw_pcie_setup_rc(pp); 911 912 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 913 914 /* Assert RST */ 915 val = appl_readl(pcie, APPL_PINMUX); 916 val &= ~APPL_PINMUX_PEX_RST; 917 appl_writel(pcie, val, APPL_PINMUX); 918 919 usleep_range(100, 200); 920 921 /* Enable LTSSM */ 922 val = appl_readl(pcie, APPL_CTRL); 923 val |= APPL_CTRL_LTSSM_EN; 924 appl_writel(pcie, val, APPL_CTRL); 925 926 /* De-assert RST */ 927 val = appl_readl(pcie, APPL_PINMUX); 928 val |= APPL_PINMUX_PEX_RST; 929 appl_writel(pcie, val, APPL_PINMUX); 930 931 msleep(100); 932 } 933 934 static int tegra_pcie_dw_host_init(struct pcie_port *pp) 935 { 936 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 937 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 938 u32 val, tmp, offset, speed; 939 940 pp->bridge->ops = &tegra_pci_ops; 941 942 tegra_pcie_prepare_host(pp); 943 944 if (dw_pcie_wait_for_link(pci)) { 945 /* 946 * There are some endpoints which can't get the link up if 947 * root port has Data Link Feature (DLF) enabled. 948 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info 949 * on Scaled Flow Control and DLF. 950 * So, need to confirm that is indeed the case here and attempt 951 * link up once again with DLF disabled. 952 */ 953 val = appl_readl(pcie, APPL_DEBUG); 954 val &= APPL_DEBUG_LTSSM_STATE_MASK; 955 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; 956 tmp = appl_readl(pcie, APPL_LINK_STATUS); 957 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP; 958 if (!(val == 0x11 && !tmp)) { 959 /* Link is down for all good reasons */ 960 return 0; 961 } 962 963 dev_info(pci->dev, "Link is down in DLL"); 964 dev_info(pci->dev, "Trying again with DLFE disabled\n"); 965 /* Disable LTSSM */ 966 val = appl_readl(pcie, APPL_CTRL); 967 val &= ~APPL_CTRL_LTSSM_EN; 968 appl_writel(pcie, val, APPL_CTRL); 969 970 reset_control_assert(pcie->core_rst); 971 reset_control_deassert(pcie->core_rst); 972 973 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); 974 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); 975 val &= ~PCI_DLF_EXCHANGE_ENABLE; 976 dw_pcie_writel_dbi(pci, offset, val); 977 978 tegra_pcie_prepare_host(pp); 979 980 if (dw_pcie_wait_for_link(pci)) 981 return 0; 982 } 983 984 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 985 PCI_EXP_LNKSTA_CLS; 986 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 987 988 tegra_pcie_enable_interrupts(pp); 989 990 return 0; 991 } 992 993 static int tegra_pcie_dw_link_up(struct dw_pcie *pci) 994 { 995 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 996 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 997 998 return !!(val & PCI_EXP_LNKSTA_DLLLA); 999 } 1000 1001 static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 1002 { 1003 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1004 1005 enable_irq(pcie->pex_rst_irq); 1006 1007 return 0; 1008 } 1009 1010 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) 1011 { 1012 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1013 1014 disable_irq(pcie->pex_rst_irq); 1015 } 1016 1017 static const struct dw_pcie_ops tegra_dw_pcie_ops = { 1018 .link_up = tegra_pcie_dw_link_up, 1019 .start_link = tegra_pcie_dw_start_link, 1020 .stop_link = tegra_pcie_dw_stop_link, 1021 }; 1022 1023 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { 1024 .host_init = tegra_pcie_dw_host_init, 1025 }; 1026 1027 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) 1028 { 1029 unsigned int phy_count = pcie->phy_count; 1030 1031 while (phy_count--) { 1032 phy_power_off(pcie->phys[phy_count]); 1033 phy_exit(pcie->phys[phy_count]); 1034 } 1035 } 1036 1037 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) 1038 { 1039 unsigned int i; 1040 int ret; 1041 1042 for (i = 0; i < pcie->phy_count; i++) { 1043 ret = phy_init(pcie->phys[i]); 1044 if (ret < 0) 1045 goto phy_power_off; 1046 1047 ret = phy_power_on(pcie->phys[i]); 1048 if (ret < 0) 1049 goto phy_exit; 1050 } 1051 1052 return 0; 1053 1054 phy_power_off: 1055 while (i--) { 1056 phy_power_off(pcie->phys[i]); 1057 phy_exit: 1058 phy_exit(pcie->phys[i]); 1059 } 1060 1061 return ret; 1062 } 1063 1064 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) 1065 { 1066 struct platform_device *pdev = to_platform_device(pcie->dev); 1067 struct device_node *np = pcie->dev->of_node; 1068 int ret; 1069 1070 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 1071 if (!pcie->dbi_res) { 1072 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); 1073 return -ENODEV; 1074 } 1075 1076 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); 1077 if (ret < 0) { 1078 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); 1079 return ret; 1080 } 1081 1082 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", 1083 &pcie->aspm_pwr_on_t); 1084 if (ret < 0) 1085 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", 1086 ret); 1087 1088 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", 1089 &pcie->aspm_l0s_enter_lat); 1090 if (ret < 0) 1091 dev_info(pcie->dev, 1092 "Failed to read ASPM L0s Entrance latency: %d\n", ret); 1093 1094 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); 1095 if (ret < 0) { 1096 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); 1097 return ret; 1098 } 1099 1100 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); 1101 if (ret) { 1102 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); 1103 return ret; 1104 } 1105 1106 ret = of_property_count_strings(np, "phy-names"); 1107 if (ret < 0) { 1108 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", 1109 ret); 1110 return ret; 1111 } 1112 pcie->phy_count = ret; 1113 1114 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) 1115 pcie->update_fc_fixup = true; 1116 1117 pcie->supports_clkreq = 1118 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); 1119 1120 pcie->enable_cdm_check = 1121 of_property_read_bool(np, "snps,enable-cdm-check"); 1122 1123 if (pcie->mode == DW_PCIE_RC_TYPE) 1124 return 0; 1125 1126 /* Endpoint mode specific DT entries */ 1127 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); 1128 if (IS_ERR(pcie->pex_rst_gpiod)) { 1129 int err = PTR_ERR(pcie->pex_rst_gpiod); 1130 const char *level = KERN_ERR; 1131 1132 if (err == -EPROBE_DEFER) 1133 level = KERN_DEBUG; 1134 1135 dev_printk(level, pcie->dev, 1136 dev_fmt("Failed to get PERST GPIO: %d\n"), 1137 err); 1138 return err; 1139 } 1140 1141 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, 1142 "nvidia,refclk-select", 1143 GPIOD_OUT_HIGH); 1144 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { 1145 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); 1146 const char *level = KERN_ERR; 1147 1148 if (err == -EPROBE_DEFER) 1149 level = KERN_DEBUG; 1150 1151 dev_printk(level, pcie->dev, 1152 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"), 1153 err); 1154 pcie->pex_refclk_sel_gpiod = NULL; 1155 } 1156 1157 return 0; 1158 } 1159 1160 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, 1161 bool enable) 1162 { 1163 struct mrq_uphy_response resp; 1164 struct tegra_bpmp_message msg; 1165 struct mrq_uphy_request req; 1166 1167 /* Controller-5 doesn't need to have its state set by BPMP-FW */ 1168 if (pcie->cid == 5) 1169 return 0; 1170 1171 memset(&req, 0, sizeof(req)); 1172 memset(&resp, 0, sizeof(resp)); 1173 1174 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE; 1175 req.controller_state.pcie_controller = pcie->cid; 1176 req.controller_state.enable = enable; 1177 1178 memset(&msg, 0, sizeof(msg)); 1179 msg.mrq = MRQ_UPHY; 1180 msg.tx.data = &req; 1181 msg.tx.size = sizeof(req); 1182 msg.rx.data = &resp; 1183 msg.rx.size = sizeof(resp); 1184 1185 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1186 } 1187 1188 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, 1189 bool enable) 1190 { 1191 struct mrq_uphy_response resp; 1192 struct tegra_bpmp_message msg; 1193 struct mrq_uphy_request req; 1194 1195 memset(&req, 0, sizeof(req)); 1196 memset(&resp, 0, sizeof(resp)); 1197 1198 if (enable) { 1199 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT; 1200 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; 1201 } else { 1202 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF; 1203 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; 1204 } 1205 1206 memset(&msg, 0, sizeof(msg)); 1207 msg.mrq = MRQ_UPHY; 1208 msg.tx.data = &req; 1209 msg.tx.size = sizeof(req); 1210 msg.rx.data = &resp; 1211 msg.rx.size = sizeof(resp); 1212 1213 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1214 } 1215 1216 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) 1217 { 1218 struct pcie_port *pp = &pcie->pci.pp; 1219 struct pci_bus *child, *root_bus = NULL; 1220 struct pci_dev *pdev; 1221 1222 /* 1223 * link doesn't go into L2 state with some of the endpoints with Tegra 1224 * if they are not in D0 state. So, need to make sure that immediate 1225 * downstream devices are in D0 state before sending PME_TurnOff to put 1226 * link into L2 state. 1227 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, 1228 * 5.2 Link State Power Management (Page #428). 1229 */ 1230 1231 list_for_each_entry(child, &pp->bridge->bus->children, node) { 1232 /* Bring downstream devices to D0 if they are not already in */ 1233 if (child->parent == pp->bridge->bus) { 1234 root_bus = child; 1235 break; 1236 } 1237 } 1238 1239 if (!root_bus) { 1240 dev_err(pcie->dev, "Failed to find downstream devices\n"); 1241 return; 1242 } 1243 1244 list_for_each_entry(pdev, &root_bus->devices, bus_list) { 1245 if (PCI_SLOT(pdev->devfn) == 0) { 1246 if (pci_set_power_state(pdev, PCI_D0)) 1247 dev_err(pcie->dev, 1248 "Failed to transition %s to D0 state\n", 1249 dev_name(&pdev->dev)); 1250 } 1251 } 1252 } 1253 1254 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) 1255 { 1256 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); 1257 if (IS_ERR(pcie->slot_ctl_3v3)) { 1258 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) 1259 return PTR_ERR(pcie->slot_ctl_3v3); 1260 1261 pcie->slot_ctl_3v3 = NULL; 1262 } 1263 1264 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); 1265 if (IS_ERR(pcie->slot_ctl_12v)) { 1266 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) 1267 return PTR_ERR(pcie->slot_ctl_12v); 1268 1269 pcie->slot_ctl_12v = NULL; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) 1276 { 1277 int ret; 1278 1279 if (pcie->slot_ctl_3v3) { 1280 ret = regulator_enable(pcie->slot_ctl_3v3); 1281 if (ret < 0) { 1282 dev_err(pcie->dev, 1283 "Failed to enable 3.3V slot supply: %d\n", ret); 1284 return ret; 1285 } 1286 } 1287 1288 if (pcie->slot_ctl_12v) { 1289 ret = regulator_enable(pcie->slot_ctl_12v); 1290 if (ret < 0) { 1291 dev_err(pcie->dev, 1292 "Failed to enable 12V slot supply: %d\n", ret); 1293 goto fail_12v_enable; 1294 } 1295 } 1296 1297 /* 1298 * According to PCI Express Card Electromechanical Specification 1299 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) 1300 * should be a minimum of 100ms. 1301 */ 1302 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) 1303 msleep(100); 1304 1305 return 0; 1306 1307 fail_12v_enable: 1308 if (pcie->slot_ctl_3v3) 1309 regulator_disable(pcie->slot_ctl_3v3); 1310 return ret; 1311 } 1312 1313 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) 1314 { 1315 if (pcie->slot_ctl_12v) 1316 regulator_disable(pcie->slot_ctl_12v); 1317 if (pcie->slot_ctl_3v3) 1318 regulator_disable(pcie->slot_ctl_3v3); 1319 } 1320 1321 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, 1322 bool en_hw_hot_rst) 1323 { 1324 int ret; 1325 u32 val; 1326 1327 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true); 1328 if (ret) { 1329 dev_err(pcie->dev, 1330 "Failed to enable controller %u: %d\n", pcie->cid, ret); 1331 return ret; 1332 } 1333 1334 ret = tegra_pcie_enable_slot_regulators(pcie); 1335 if (ret < 0) 1336 goto fail_slot_reg_en; 1337 1338 ret = regulator_enable(pcie->pex_ctl_supply); 1339 if (ret < 0) { 1340 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); 1341 goto fail_reg_en; 1342 } 1343 1344 ret = clk_prepare_enable(pcie->core_clk); 1345 if (ret) { 1346 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); 1347 goto fail_core_clk; 1348 } 1349 1350 ret = reset_control_deassert(pcie->core_apb_rst); 1351 if (ret) { 1352 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", 1353 ret); 1354 goto fail_core_apb_rst; 1355 } 1356 1357 if (en_hw_hot_rst) { 1358 /* Enable HW_HOT_RST mode */ 1359 val = appl_readl(pcie, APPL_CTRL); 1360 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 1361 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 1362 val |= APPL_CTRL_HW_HOT_RST_EN; 1363 appl_writel(pcie, val, APPL_CTRL); 1364 } 1365 1366 ret = tegra_pcie_enable_phy(pcie); 1367 if (ret) { 1368 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); 1369 goto fail_phy; 1370 } 1371 1372 /* Update CFG base address */ 1373 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1374 APPL_CFG_BASE_ADDR); 1375 1376 /* Configure this core for RP mode operation */ 1377 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE); 1378 1379 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1380 1381 val = appl_readl(pcie, APPL_CTRL); 1382 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); 1383 1384 val = appl_readl(pcie, APPL_CFG_MISC); 1385 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1386 appl_writel(pcie, val, APPL_CFG_MISC); 1387 1388 if (!pcie->supports_clkreq) { 1389 val = appl_readl(pcie, APPL_PINMUX); 1390 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; 1391 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; 1392 appl_writel(pcie, val, APPL_PINMUX); 1393 } 1394 1395 /* Update iATU_DMA base address */ 1396 appl_writel(pcie, 1397 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1398 APPL_CFG_IATU_DMA_BASE_ADDR); 1399 1400 reset_control_deassert(pcie->core_rst); 1401 1402 return ret; 1403 1404 fail_phy: 1405 reset_control_assert(pcie->core_apb_rst); 1406 fail_core_apb_rst: 1407 clk_disable_unprepare(pcie->core_clk); 1408 fail_core_clk: 1409 regulator_disable(pcie->pex_ctl_supply); 1410 fail_reg_en: 1411 tegra_pcie_disable_slot_regulators(pcie); 1412 fail_slot_reg_en: 1413 tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1414 1415 return ret; 1416 } 1417 1418 static int __deinit_controller(struct tegra_pcie_dw *pcie) 1419 { 1420 int ret; 1421 1422 ret = reset_control_assert(pcie->core_rst); 1423 if (ret) { 1424 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", 1425 ret); 1426 return ret; 1427 } 1428 1429 tegra_pcie_disable_phy(pcie); 1430 1431 ret = reset_control_assert(pcie->core_apb_rst); 1432 if (ret) { 1433 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); 1434 return ret; 1435 } 1436 1437 clk_disable_unprepare(pcie->core_clk); 1438 1439 ret = regulator_disable(pcie->pex_ctl_supply); 1440 if (ret) { 1441 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); 1442 return ret; 1443 } 1444 1445 tegra_pcie_disable_slot_regulators(pcie); 1446 1447 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1448 if (ret) { 1449 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", 1450 pcie->cid, ret); 1451 return ret; 1452 } 1453 1454 return ret; 1455 } 1456 1457 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) 1458 { 1459 struct dw_pcie *pci = &pcie->pci; 1460 struct pcie_port *pp = &pci->pp; 1461 int ret; 1462 1463 ret = tegra_pcie_config_controller(pcie, false); 1464 if (ret < 0) 1465 return ret; 1466 1467 pp->ops = &tegra_pcie_dw_host_ops; 1468 1469 ret = dw_pcie_host_init(pp); 1470 if (ret < 0) { 1471 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); 1472 goto fail_host_init; 1473 } 1474 1475 return 0; 1476 1477 fail_host_init: 1478 return __deinit_controller(pcie); 1479 } 1480 1481 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) 1482 { 1483 u32 val; 1484 1485 if (!tegra_pcie_dw_link_up(&pcie->pci)) 1486 return 0; 1487 1488 val = appl_readl(pcie, APPL_RADM_STATUS); 1489 val |= APPL_PM_XMT_TURNOFF_STATE; 1490 appl_writel(pcie, val, APPL_RADM_STATUS); 1491 1492 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, 1493 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, 1494 1, PME_ACK_TIMEOUT); 1495 } 1496 1497 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) 1498 { 1499 u32 data; 1500 int err; 1501 1502 if (!tegra_pcie_dw_link_up(&pcie->pci)) { 1503 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); 1504 return; 1505 } 1506 1507 if (tegra_pcie_try_link_l2(pcie)) { 1508 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); 1509 /* 1510 * TX lane clock freq will reset to Gen1 only if link is in L2 1511 * or detect state. 1512 * So apply pex_rst to end point to force RP to go into detect 1513 * state 1514 */ 1515 data = appl_readl(pcie, APPL_PINMUX); 1516 data &= ~APPL_PINMUX_PEX_RST; 1517 appl_writel(pcie, data, APPL_PINMUX); 1518 1519 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, 1520 data, 1521 ((data & 1522 APPL_DEBUG_LTSSM_STATE_MASK) >> 1523 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1524 LTSSM_STATE_PRE_DETECT, 1525 1, LTSSM_TIMEOUT); 1526 if (err) { 1527 dev_info(pcie->dev, "Link didn't go to detect state\n"); 1528 } else { 1529 /* Disable LTSSM after link is in detect state */ 1530 data = appl_readl(pcie, APPL_CTRL); 1531 data &= ~APPL_CTRL_LTSSM_EN; 1532 appl_writel(pcie, data, APPL_CTRL); 1533 } 1534 } 1535 /* 1536 * DBI registers may not be accessible after this as PLL-E would be 1537 * down depending on how CLKREQ is pulled by end point 1538 */ 1539 data = appl_readl(pcie, APPL_PINMUX); 1540 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE); 1541 /* Cut REFCLK to slot */ 1542 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1543 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1544 appl_writel(pcie, data, APPL_PINMUX); 1545 } 1546 1547 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1548 { 1549 tegra_pcie_downstream_dev_to_D0(pcie); 1550 dw_pcie_host_deinit(&pcie->pci.pp); 1551 tegra_pcie_dw_pme_turnoff(pcie); 1552 1553 return __deinit_controller(pcie); 1554 } 1555 1556 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) 1557 { 1558 struct device *dev = pcie->dev; 1559 char *name; 1560 int ret; 1561 1562 pm_runtime_enable(dev); 1563 1564 ret = pm_runtime_get_sync(dev); 1565 if (ret < 0) { 1566 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1567 ret); 1568 goto fail_pm_get_sync; 1569 } 1570 1571 ret = pinctrl_pm_select_default_state(dev); 1572 if (ret < 0) { 1573 dev_err(dev, "Failed to configure sideband pins: %d\n", ret); 1574 goto fail_pm_get_sync; 1575 } 1576 1577 tegra_pcie_init_controller(pcie); 1578 1579 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); 1580 if (!pcie->link_state) { 1581 ret = -ENOMEDIUM; 1582 goto fail_host_init; 1583 } 1584 1585 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1586 if (!name) { 1587 ret = -ENOMEM; 1588 goto fail_host_init; 1589 } 1590 1591 pcie->debugfs = debugfs_create_dir(name, NULL); 1592 init_debugfs(pcie); 1593 1594 return ret; 1595 1596 fail_host_init: 1597 tegra_pcie_deinit_controller(pcie); 1598 fail_pm_get_sync: 1599 pm_runtime_put_sync(dev); 1600 pm_runtime_disable(dev); 1601 return ret; 1602 } 1603 1604 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) 1605 { 1606 u32 val; 1607 int ret; 1608 1609 if (pcie->ep_state == EP_STATE_DISABLED) 1610 return; 1611 1612 /* Disable LTSSM */ 1613 val = appl_readl(pcie, APPL_CTRL); 1614 val &= ~APPL_CTRL_LTSSM_EN; 1615 appl_writel(pcie, val, APPL_CTRL); 1616 1617 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, 1618 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> 1619 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1620 LTSSM_STATE_PRE_DETECT, 1621 1, LTSSM_TIMEOUT); 1622 if (ret) 1623 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); 1624 1625 reset_control_assert(pcie->core_rst); 1626 1627 tegra_pcie_disable_phy(pcie); 1628 1629 reset_control_assert(pcie->core_apb_rst); 1630 1631 clk_disable_unprepare(pcie->core_clk); 1632 1633 pm_runtime_put_sync(pcie->dev); 1634 1635 ret = tegra_pcie_bpmp_set_pll_state(pcie, false); 1636 if (ret) 1637 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); 1638 1639 pcie->ep_state = EP_STATE_DISABLED; 1640 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); 1641 } 1642 1643 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) 1644 { 1645 struct dw_pcie *pci = &pcie->pci; 1646 struct dw_pcie_ep *ep = &pci->ep; 1647 struct device *dev = pcie->dev; 1648 u32 val; 1649 int ret; 1650 1651 if (pcie->ep_state == EP_STATE_ENABLED) 1652 return; 1653 1654 ret = pm_runtime_get_sync(dev); 1655 if (ret < 0) { 1656 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1657 ret); 1658 return; 1659 } 1660 1661 ret = tegra_pcie_bpmp_set_pll_state(pcie, true); 1662 if (ret) { 1663 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret); 1664 goto fail_pll_init; 1665 } 1666 1667 ret = clk_prepare_enable(pcie->core_clk); 1668 if (ret) { 1669 dev_err(dev, "Failed to enable core clock: %d\n", ret); 1670 goto fail_core_clk_enable; 1671 } 1672 1673 ret = reset_control_deassert(pcie->core_apb_rst); 1674 if (ret) { 1675 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret); 1676 goto fail_core_apb_rst; 1677 } 1678 1679 ret = tegra_pcie_enable_phy(pcie); 1680 if (ret) { 1681 dev_err(dev, "Failed to enable PHY: %d\n", ret); 1682 goto fail_phy; 1683 } 1684 1685 /* Clear any stale interrupt statuses */ 1686 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 1687 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 1688 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 1689 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 1690 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 1691 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 1692 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 1696 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 1697 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 1698 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 1699 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 1700 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 1701 1702 /* configure this core for EP mode operation */ 1703 val = appl_readl(pcie, APPL_DM_TYPE); 1704 val &= ~APPL_DM_TYPE_MASK; 1705 val |= APPL_DM_TYPE_EP; 1706 appl_writel(pcie, val, APPL_DM_TYPE); 1707 1708 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1709 1710 val = appl_readl(pcie, APPL_CTRL); 1711 val |= APPL_CTRL_SYS_PRE_DET_STATE; 1712 val |= APPL_CTRL_HW_HOT_RST_EN; 1713 appl_writel(pcie, val, APPL_CTRL); 1714 1715 val = appl_readl(pcie, APPL_CFG_MISC); 1716 val |= APPL_CFG_MISC_SLV_EP_MODE; 1717 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1718 appl_writel(pcie, val, APPL_CFG_MISC); 1719 1720 val = appl_readl(pcie, APPL_PINMUX); 1721 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1722 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1723 appl_writel(pcie, val, APPL_PINMUX); 1724 1725 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1726 APPL_CFG_BASE_ADDR); 1727 1728 appl_writel(pcie, pcie->atu_dma_res->start & 1729 APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1730 APPL_CFG_IATU_DMA_BASE_ADDR); 1731 1732 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 1733 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 1734 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 1735 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; 1736 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 1737 1738 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 1739 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN; 1740 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; 1741 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 1742 1743 reset_control_deassert(pcie->core_rst); 1744 1745 if (pcie->update_fc_fixup) { 1746 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 1747 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 1748 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 1749 } 1750 1751 config_gen3_gen4_eq_presets(pcie); 1752 1753 init_host_aspm(pcie); 1754 1755 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 1756 if (!pcie->supports_clkreq) { 1757 disable_aspm_l11(pcie); 1758 disable_aspm_l12(pcie); 1759 } 1760 1761 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 1762 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 1763 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 1764 1765 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1766 PCI_CAP_ID_EXP); 1767 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 1768 1769 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); 1770 val |= MSIX_ADDR_MATCH_LOW_OFF_EN; 1771 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); 1772 val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); 1773 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); 1774 1775 ret = dw_pcie_ep_init_complete(ep); 1776 if (ret) { 1777 dev_err(dev, "Failed to complete initialization: %d\n", ret); 1778 goto fail_init_complete; 1779 } 1780 1781 dw_pcie_ep_init_notify(ep); 1782 1783 /* Enable LTSSM */ 1784 val = appl_readl(pcie, APPL_CTRL); 1785 val |= APPL_CTRL_LTSSM_EN; 1786 appl_writel(pcie, val, APPL_CTRL); 1787 1788 pcie->ep_state = EP_STATE_ENABLED; 1789 dev_dbg(dev, "Initialization of endpoint is completed\n"); 1790 1791 return; 1792 1793 fail_init_complete: 1794 reset_control_assert(pcie->core_rst); 1795 tegra_pcie_disable_phy(pcie); 1796 fail_phy: 1797 reset_control_assert(pcie->core_apb_rst); 1798 fail_core_apb_rst: 1799 clk_disable_unprepare(pcie->core_clk); 1800 fail_core_clk_enable: 1801 tegra_pcie_bpmp_set_pll_state(pcie, false); 1802 fail_pll_init: 1803 pm_runtime_put_sync(dev); 1804 } 1805 1806 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) 1807 { 1808 struct tegra_pcie_dw *pcie = arg; 1809 1810 if (gpiod_get_value(pcie->pex_rst_gpiod)) 1811 pex_ep_event_pex_rst_assert(pcie); 1812 else 1813 pex_ep_event_pex_rst_deassert(pcie); 1814 1815 return IRQ_HANDLED; 1816 } 1817 1818 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) 1819 { 1820 /* Tegra194 supports only INTA */ 1821 if (irq > 1) 1822 return -EINVAL; 1823 1824 appl_writel(pcie, 1, APPL_LEGACY_INTX); 1825 usleep_range(1000, 2000); 1826 appl_writel(pcie, 0, APPL_LEGACY_INTX); 1827 return 0; 1828 } 1829 1830 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) 1831 { 1832 if (unlikely(irq > 31)) 1833 return -EINVAL; 1834 1835 appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1); 1836 1837 return 0; 1838 } 1839 1840 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq) 1841 { 1842 struct dw_pcie_ep *ep = &pcie->pci.ep; 1843 1844 writel(irq, ep->msi_mem); 1845 1846 return 0; 1847 } 1848 1849 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1850 enum pci_epc_irq_type type, 1851 u16 interrupt_num) 1852 { 1853 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1854 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1855 1856 switch (type) { 1857 case PCI_EPC_IRQ_LEGACY: 1858 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); 1859 1860 case PCI_EPC_IRQ_MSI: 1861 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num); 1862 1863 case PCI_EPC_IRQ_MSIX: 1864 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num); 1865 1866 default: 1867 dev_err(pci->dev, "Unknown IRQ type\n"); 1868 return -EPERM; 1869 } 1870 1871 return 0; 1872 } 1873 1874 static const struct pci_epc_features tegra_pcie_epc_features = { 1875 .linkup_notifier = true, 1876 .core_init_notifier = true, 1877 .msi_capable = false, 1878 .msix_capable = false, 1879 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5, 1880 .bar_fixed_64bit = 1 << BAR_0, 1881 .bar_fixed_size[0] = SZ_1M, 1882 }; 1883 1884 static const struct pci_epc_features* 1885 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) 1886 { 1887 return &tegra_pcie_epc_features; 1888 } 1889 1890 static struct dw_pcie_ep_ops pcie_ep_ops = { 1891 .raise_irq = tegra_pcie_ep_raise_irq, 1892 .get_features = tegra_pcie_ep_get_features, 1893 }; 1894 1895 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, 1896 struct platform_device *pdev) 1897 { 1898 struct dw_pcie *pci = &pcie->pci; 1899 struct device *dev = pcie->dev; 1900 struct dw_pcie_ep *ep; 1901 char *name; 1902 int ret; 1903 1904 ep = &pci->ep; 1905 ep->ops = &pcie_ep_ops; 1906 1907 ep->page_size = SZ_64K; 1908 1909 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); 1910 if (ret < 0) { 1911 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n", 1912 ret); 1913 return ret; 1914 } 1915 1916 ret = gpiod_to_irq(pcie->pex_rst_gpiod); 1917 if (ret < 0) { 1918 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret); 1919 return ret; 1920 } 1921 pcie->pex_rst_irq = (unsigned int)ret; 1922 1923 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq", 1924 pcie->cid); 1925 if (!name) { 1926 dev_err(dev, "Failed to create PERST IRQ string\n"); 1927 return -ENOMEM; 1928 } 1929 1930 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); 1931 1932 pcie->ep_state = EP_STATE_DISABLED; 1933 1934 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, 1935 tegra_pcie_ep_pex_rst_irq, 1936 IRQF_TRIGGER_RISING | 1937 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1938 name, (void *)pcie); 1939 if (ret < 0) { 1940 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); 1941 return ret; 1942 } 1943 1944 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work", 1945 pcie->cid); 1946 if (!name) { 1947 dev_err(dev, "Failed to create PCIe EP work thread string\n"); 1948 return -ENOMEM; 1949 } 1950 1951 pm_runtime_enable(dev); 1952 1953 ret = dw_pcie_ep_init(ep); 1954 if (ret) { 1955 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n", 1956 ret); 1957 return ret; 1958 } 1959 1960 return 0; 1961 } 1962 1963 static int tegra_pcie_dw_probe(struct platform_device *pdev) 1964 { 1965 const struct tegra_pcie_dw_of_data *data; 1966 struct device *dev = &pdev->dev; 1967 struct resource *atu_dma_res; 1968 struct tegra_pcie_dw *pcie; 1969 struct pcie_port *pp; 1970 struct dw_pcie *pci; 1971 struct phy **phys; 1972 char *name; 1973 int ret; 1974 u32 i; 1975 1976 data = of_device_get_match_data(dev); 1977 1978 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1979 if (!pcie) 1980 return -ENOMEM; 1981 1982 pci = &pcie->pci; 1983 pci->dev = &pdev->dev; 1984 pci->ops = &tegra_dw_pcie_ops; 1985 pci->n_fts[0] = N_FTS_VAL; 1986 pci->n_fts[1] = FTS_VAL; 1987 1988 pp = &pci->pp; 1989 pp->num_vectors = MAX_MSI_IRQS; 1990 pcie->dev = &pdev->dev; 1991 pcie->mode = (enum dw_pcie_device_mode)data->mode; 1992 1993 ret = tegra_pcie_dw_parse_dt(pcie); 1994 if (ret < 0) { 1995 const char *level = KERN_ERR; 1996 1997 if (ret == -EPROBE_DEFER) 1998 level = KERN_DEBUG; 1999 2000 dev_printk(level, dev, 2001 dev_fmt("Failed to parse device tree: %d\n"), 2002 ret); 2003 return ret; 2004 } 2005 2006 ret = tegra_pcie_get_slot_regulators(pcie); 2007 if (ret < 0) { 2008 const char *level = KERN_ERR; 2009 2010 if (ret == -EPROBE_DEFER) 2011 level = KERN_DEBUG; 2012 2013 dev_printk(level, dev, 2014 dev_fmt("Failed to get slot regulators: %d\n"), 2015 ret); 2016 return ret; 2017 } 2018 2019 if (pcie->pex_refclk_sel_gpiod) 2020 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); 2021 2022 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); 2023 if (IS_ERR(pcie->pex_ctl_supply)) { 2024 ret = PTR_ERR(pcie->pex_ctl_supply); 2025 if (ret != -EPROBE_DEFER) 2026 dev_err(dev, "Failed to get regulator: %ld\n", 2027 PTR_ERR(pcie->pex_ctl_supply)); 2028 return ret; 2029 } 2030 2031 pcie->core_clk = devm_clk_get(dev, "core"); 2032 if (IS_ERR(pcie->core_clk)) { 2033 dev_err(dev, "Failed to get core clock: %ld\n", 2034 PTR_ERR(pcie->core_clk)); 2035 return PTR_ERR(pcie->core_clk); 2036 } 2037 2038 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2039 "appl"); 2040 if (!pcie->appl_res) { 2041 dev_err(dev, "Failed to find \"appl\" region\n"); 2042 return -ENODEV; 2043 } 2044 2045 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); 2046 if (IS_ERR(pcie->appl_base)) 2047 return PTR_ERR(pcie->appl_base); 2048 2049 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); 2050 if (IS_ERR(pcie->core_apb_rst)) { 2051 dev_err(dev, "Failed to get APB reset: %ld\n", 2052 PTR_ERR(pcie->core_apb_rst)); 2053 return PTR_ERR(pcie->core_apb_rst); 2054 } 2055 2056 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); 2057 if (!phys) 2058 return -ENOMEM; 2059 2060 for (i = 0; i < pcie->phy_count; i++) { 2061 name = kasprintf(GFP_KERNEL, "p2u-%u", i); 2062 if (!name) { 2063 dev_err(dev, "Failed to create P2U string\n"); 2064 return -ENOMEM; 2065 } 2066 phys[i] = devm_phy_get(dev, name); 2067 kfree(name); 2068 if (IS_ERR(phys[i])) { 2069 ret = PTR_ERR(phys[i]); 2070 if (ret != -EPROBE_DEFER) 2071 dev_err(dev, "Failed to get PHY: %d\n", ret); 2072 return ret; 2073 } 2074 } 2075 2076 pcie->phys = phys; 2077 2078 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2079 "atu_dma"); 2080 if (!atu_dma_res) { 2081 dev_err(dev, "Failed to find \"atu_dma\" region\n"); 2082 return -ENODEV; 2083 } 2084 pcie->atu_dma_res = atu_dma_res; 2085 2086 pci->atu_size = resource_size(atu_dma_res); 2087 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); 2088 if (IS_ERR(pci->atu_base)) 2089 return PTR_ERR(pci->atu_base); 2090 2091 pcie->core_rst = devm_reset_control_get(dev, "core"); 2092 if (IS_ERR(pcie->core_rst)) { 2093 dev_err(dev, "Failed to get core reset: %ld\n", 2094 PTR_ERR(pcie->core_rst)); 2095 return PTR_ERR(pcie->core_rst); 2096 } 2097 2098 pp->irq = platform_get_irq_byname(pdev, "intr"); 2099 if (pp->irq < 0) 2100 return pp->irq; 2101 2102 pcie->bpmp = tegra_bpmp_get(dev); 2103 if (IS_ERR(pcie->bpmp)) 2104 return PTR_ERR(pcie->bpmp); 2105 2106 platform_set_drvdata(pdev, pcie); 2107 2108 switch (pcie->mode) { 2109 case DW_PCIE_RC_TYPE: 2110 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, 2111 IRQF_SHARED, "tegra-pcie-intr", pcie); 2112 if (ret) { 2113 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2114 ret); 2115 goto fail; 2116 } 2117 2118 ret = tegra_pcie_config_rp(pcie); 2119 if (ret && ret != -ENOMEDIUM) 2120 goto fail; 2121 else 2122 return 0; 2123 break; 2124 2125 case DW_PCIE_EP_TYPE: 2126 ret = devm_request_threaded_irq(dev, pp->irq, 2127 tegra_pcie_ep_hard_irq, 2128 tegra_pcie_ep_irq_thread, 2129 IRQF_SHARED | IRQF_ONESHOT, 2130 "tegra-pcie-ep-intr", pcie); 2131 if (ret) { 2132 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2133 ret); 2134 goto fail; 2135 } 2136 2137 ret = tegra_pcie_config_ep(pcie, pdev); 2138 if (ret < 0) 2139 goto fail; 2140 break; 2141 2142 default: 2143 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); 2144 } 2145 2146 fail: 2147 tegra_bpmp_put(pcie->bpmp); 2148 return ret; 2149 } 2150 2151 static int tegra_pcie_dw_remove(struct platform_device *pdev) 2152 { 2153 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2154 2155 if (!pcie->link_state) 2156 return 0; 2157 2158 debugfs_remove_recursive(pcie->debugfs); 2159 tegra_pcie_deinit_controller(pcie); 2160 pm_runtime_put_sync(pcie->dev); 2161 pm_runtime_disable(pcie->dev); 2162 tegra_bpmp_put(pcie->bpmp); 2163 if (pcie->pex_refclk_sel_gpiod) 2164 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); 2165 2166 return 0; 2167 } 2168 2169 static int tegra_pcie_dw_suspend_late(struct device *dev) 2170 { 2171 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2172 u32 val; 2173 2174 if (!pcie->link_state) 2175 return 0; 2176 2177 /* Enable HW_HOT_RST mode */ 2178 val = appl_readl(pcie, APPL_CTRL); 2179 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2180 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2181 val |= APPL_CTRL_HW_HOT_RST_EN; 2182 appl_writel(pcie, val, APPL_CTRL); 2183 2184 return 0; 2185 } 2186 2187 static int tegra_pcie_dw_suspend_noirq(struct device *dev) 2188 { 2189 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2190 2191 if (!pcie->link_state) 2192 return 0; 2193 2194 /* Save MSI interrupt vector */ 2195 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, 2196 PORT_LOGIC_MSI_CTRL_INT_0_EN); 2197 tegra_pcie_downstream_dev_to_D0(pcie); 2198 tegra_pcie_dw_pme_turnoff(pcie); 2199 2200 return __deinit_controller(pcie); 2201 } 2202 2203 static int tegra_pcie_dw_resume_noirq(struct device *dev) 2204 { 2205 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2206 int ret; 2207 2208 if (!pcie->link_state) 2209 return 0; 2210 2211 ret = tegra_pcie_config_controller(pcie, true); 2212 if (ret < 0) 2213 return ret; 2214 2215 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); 2216 if (ret < 0) { 2217 dev_err(dev, "Failed to init host: %d\n", ret); 2218 goto fail_host_init; 2219 } 2220 2221 /* Restore MSI interrupt vector */ 2222 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, 2223 pcie->msi_ctrl_int); 2224 2225 return 0; 2226 2227 fail_host_init: 2228 return __deinit_controller(pcie); 2229 } 2230 2231 static int tegra_pcie_dw_resume_early(struct device *dev) 2232 { 2233 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2234 u32 val; 2235 2236 if (!pcie->link_state) 2237 return 0; 2238 2239 /* Disable HW_HOT_RST mode */ 2240 val = appl_readl(pcie, APPL_CTRL); 2241 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2242 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2243 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << 2244 APPL_CTRL_HW_HOT_RST_MODE_SHIFT; 2245 val &= ~APPL_CTRL_HW_HOT_RST_EN; 2246 appl_writel(pcie, val, APPL_CTRL); 2247 2248 return 0; 2249 } 2250 2251 static void tegra_pcie_dw_shutdown(struct platform_device *pdev) 2252 { 2253 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2254 2255 if (!pcie->link_state) 2256 return; 2257 2258 debugfs_remove_recursive(pcie->debugfs); 2259 tegra_pcie_downstream_dev_to_D0(pcie); 2260 2261 disable_irq(pcie->pci.pp.irq); 2262 if (IS_ENABLED(CONFIG_PCI_MSI)) 2263 disable_irq(pcie->pci.pp.msi_irq); 2264 2265 tegra_pcie_dw_pme_turnoff(pcie); 2266 __deinit_controller(pcie); 2267 } 2268 2269 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { 2270 .mode = DW_PCIE_RC_TYPE, 2271 }; 2272 2273 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = { 2274 .mode = DW_PCIE_EP_TYPE, 2275 }; 2276 2277 static const struct of_device_id tegra_pcie_dw_of_match[] = { 2278 { 2279 .compatible = "nvidia,tegra194-pcie", 2280 .data = &tegra_pcie_dw_rc_of_data, 2281 }, 2282 { 2283 .compatible = "nvidia,tegra194-pcie-ep", 2284 .data = &tegra_pcie_dw_ep_of_data, 2285 }, 2286 {}, 2287 }; 2288 2289 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = { 2290 .suspend_late = tegra_pcie_dw_suspend_late, 2291 .suspend_noirq = tegra_pcie_dw_suspend_noirq, 2292 .resume_noirq = tegra_pcie_dw_resume_noirq, 2293 .resume_early = tegra_pcie_dw_resume_early, 2294 }; 2295 2296 static struct platform_driver tegra_pcie_dw_driver = { 2297 .probe = tegra_pcie_dw_probe, 2298 .remove = tegra_pcie_dw_remove, 2299 .shutdown = tegra_pcie_dw_shutdown, 2300 .driver = { 2301 .name = "tegra194-pcie", 2302 .pm = &tegra_pcie_dw_pm_ops, 2303 .of_match_table = tegra_pcie_dw_of_match, 2304 }, 2305 }; 2306 module_platform_driver(tegra_pcie_dw_driver); 2307 2308 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); 2309 2310 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 2311 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); 2312 MODULE_LICENSE("GPL v2"); 2313