1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for Tegra194 SoC 4 * 5 * Copyright (C) 2019 NVIDIA Corporation. 6 * 7 * Author: Vidya Sagar <vidyas@nvidia.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/reset.h> 31 #include <linux/resource.h> 32 #include <linux/types.h> 33 #include "pcie-designware.h" 34 #include <soc/tegra/bpmp.h> 35 #include <soc/tegra/bpmp-abi.h> 36 #include "../../pci.h" 37 38 #define APPL_PINMUX 0x0 39 #define APPL_PINMUX_PEX_RST BIT(0) 40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) 41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) 42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) 43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) 44 45 #define APPL_CTRL 0x4 46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) 47 #define APPL_CTRL_LTSSM_EN BIT(7) 48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20) 49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) 50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22 51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 52 53 #define APPL_INTR_EN_L0_0 0x8 54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0) 55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4) 56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8) 57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15) 58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19) 59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30) 60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31) 61 62 #define APPL_INTR_STATUS_L0 0xC 63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0) 64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8) 65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15) 66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16) 67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18) 68 69 #define APPL_INTR_EN_L1_0_0 0x1C 70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1) 71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3) 72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30) 73 74 #define APPL_INTR_STATUS_L1_0_0 0x20 75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1) 76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3) 77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30) 78 79 #define APPL_INTR_STATUS_L1_1 0x2C 80 #define APPL_INTR_STATUS_L1_2 0x30 81 #define APPL_INTR_STATUS_L1_3 0x34 82 #define APPL_INTR_STATUS_L1_6 0x3C 83 #define APPL_INTR_STATUS_L1_7 0x40 84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1) 85 86 #define APPL_INTR_EN_L1_8_0 0x44 87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) 88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) 89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) 90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) 91 92 #define APPL_INTR_STATUS_L1_8_0 0x4C 93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6) 94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2) 95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3) 96 97 #define APPL_INTR_STATUS_L1_9 0x54 98 #define APPL_INTR_STATUS_L1_10 0x58 99 #define APPL_INTR_STATUS_L1_11 0x64 100 #define APPL_INTR_STATUS_L1_13 0x74 101 #define APPL_INTR_STATUS_L1_14 0x78 102 #define APPL_INTR_STATUS_L1_15 0x7C 103 #define APPL_INTR_STATUS_L1_17 0x88 104 105 #define APPL_INTR_EN_L1_18 0x90 106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2) 107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 109 110 #define APPL_INTR_STATUS_L1_18 0x94 111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2) 112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 114 115 #define APPL_MSI_CTRL_1 0xAC 116 117 #define APPL_MSI_CTRL_2 0xB0 118 119 #define APPL_LEGACY_INTX 0xB8 120 121 #define APPL_LTR_MSG_1 0xC4 122 #define LTR_MSG_REQ BIT(15) 123 #define LTR_MST_NO_SNOOP_SHIFT 16 124 125 #define APPL_LTR_MSG_2 0xC8 126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) 127 128 #define APPL_LINK_STATUS 0xCC 129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0) 130 131 #define APPL_DEBUG 0xD0 132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) 133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) 135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 136 #define LTSSM_STATE_PRE_DETECT 5 137 138 #define APPL_RADM_STATUS 0xE4 139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) 140 141 #define APPL_DM_TYPE 0x100 142 #define APPL_DM_TYPE_MASK GENMASK(3, 0) 143 #define APPL_DM_TYPE_RP 0x4 144 #define APPL_DM_TYPE_EP 0x0 145 146 #define APPL_CFG_BASE_ADDR 0x104 147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12) 148 149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108 150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18) 151 152 #define APPL_CFG_MISC 0x110 153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) 154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10) 155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10 156 #define APPL_CFG_MISC_ARCACHE_VAL 3 157 158 #define APPL_CFG_SLCG_OVERRIDE 0x114 159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0) 160 161 #define APPL_CAR_RESET_OVRD 0x12C 162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0) 163 164 #define IO_BASE_IO_DECODE BIT(0) 165 #define IO_BASE_IO_DECODE_BIT8 BIT(8) 166 167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0) 168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) 169 170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718 171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19) 172 173 #define EVENT_COUNTER_ALL_CLEAR 0x3 174 #define EVENT_COUNTER_ENABLE_ALL 0x7 175 #define EVENT_COUNTER_ENABLE_SHIFT 2 176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) 177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 180 #define EVENT_COUNTER_EVENT_L1 0x5 181 #define EVENT_COUNTER_EVENT_L1_1 0x7 182 #define EVENT_COUNTER_EVENT_L1_2 0x8 183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 184 #define EVENT_COUNTER_GROUP_5 0x5 185 186 #define N_FTS_VAL 52 187 #define FTS_VAL 52 188 189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 190 191 #define GEN3_EQ_CONTROL_OFF 0x8a8 192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8 193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) 194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) 195 196 #define GEN3_RELATED_OFF 0x890 197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) 198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 201 202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) 205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0 206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 208 209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940 210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) 211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) 212 213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944 214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0) 215 216 #define PORT_LOGIC_MSIX_DOORBELL 0x948 217 218 #define CAP_SPCIE_CAP_OFF 0x154 219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0) 220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) 221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 222 223 #define PME_ACK_TIMEOUT 10000 224 225 #define LTSSM_TIMEOUT 50000 /* 50ms */ 226 227 #define GEN3_GEN4_EQ_PRESET_INIT 5 228 229 #define GEN1_CORE_CLK_FREQ 62500000 230 #define GEN2_CORE_CLK_FREQ 125000000 231 #define GEN3_CORE_CLK_FREQ 250000000 232 #define GEN4_CORE_CLK_FREQ 500000000 233 234 #define LTR_MSG_TIMEOUT (100 * 1000) 235 236 #define PERST_DEBOUNCE_TIME (5 * 1000) 237 238 #define EP_STATE_DISABLED 0 239 #define EP_STATE_ENABLED 1 240 241 static const unsigned int pcie_gen_freq[] = { 242 GEN1_CORE_CLK_FREQ, 243 GEN2_CORE_CLK_FREQ, 244 GEN3_CORE_CLK_FREQ, 245 GEN4_CORE_CLK_FREQ 246 }; 247 248 static const u32 event_cntr_ctrl_offset[] = { 249 0x1d8, 250 0x1a8, 251 0x1a8, 252 0x1a8, 253 0x1c4, 254 0x1d8 255 }; 256 257 static const u32 event_cntr_data_offset[] = { 258 0x1dc, 259 0x1ac, 260 0x1ac, 261 0x1ac, 262 0x1c8, 263 0x1dc 264 }; 265 266 struct tegra_pcie_dw { 267 struct device *dev; 268 struct resource *appl_res; 269 struct resource *dbi_res; 270 struct resource *atu_dma_res; 271 void __iomem *appl_base; 272 struct clk *core_clk; 273 struct reset_control *core_apb_rst; 274 struct reset_control *core_rst; 275 struct dw_pcie pci; 276 struct tegra_bpmp *bpmp; 277 278 enum dw_pcie_device_mode mode; 279 280 bool supports_clkreq; 281 bool enable_cdm_check; 282 bool link_state; 283 bool update_fc_fixup; 284 u8 init_link_width; 285 u32 msi_ctrl_int; 286 u32 num_lanes; 287 u32 cid; 288 u32 cfg_link_cap_l1sub; 289 u32 pcie_cap_base; 290 u32 aspm_cmrt; 291 u32 aspm_pwr_on_t; 292 u32 aspm_l0s_enter_lat; 293 294 struct regulator *pex_ctl_supply; 295 struct regulator *slot_ctl_3v3; 296 struct regulator *slot_ctl_12v; 297 298 unsigned int phy_count; 299 struct phy **phys; 300 301 struct dentry *debugfs; 302 303 /* Endpoint mode specific */ 304 struct gpio_desc *pex_rst_gpiod; 305 struct gpio_desc *pex_refclk_sel_gpiod; 306 unsigned int pex_rst_irq; 307 int ep_state; 308 }; 309 310 struct tegra_pcie_dw_of_data { 311 enum dw_pcie_device_mode mode; 312 }; 313 314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) 315 { 316 return container_of(pci, struct tegra_pcie_dw, pci); 317 } 318 319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, 320 const u32 reg) 321 { 322 writel_relaxed(value, pcie->appl_base + reg); 323 } 324 325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) 326 { 327 return readl_relaxed(pcie->appl_base + reg); 328 } 329 330 struct tegra_pcie_soc { 331 enum dw_pcie_device_mode mode; 332 }; 333 334 static void apply_bad_link_workaround(struct pcie_port *pp) 335 { 336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 338 u32 current_link_width; 339 u16 val; 340 341 /* 342 * NOTE:- Since this scenario is uncommon and link as such is not 343 * stable anyway, not waiting to confirm if link is really 344 * transitioning to Gen-2 speed 345 */ 346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 347 if (val & PCI_EXP_LNKSTA_LBMS) { 348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> 349 PCI_EXP_LNKSTA_NLW_SHIFT; 350 if (pcie->init_link_width > current_link_width) { 351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); 352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 353 PCI_EXP_LNKCTL2); 354 val &= ~PCI_EXP_LNKCTL2_TLS; 355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT; 356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 357 PCI_EXP_LNKCTL2, val); 358 359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 360 PCI_EXP_LNKCTL); 361 val |= PCI_EXP_LNKCTL_RL; 362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 363 PCI_EXP_LNKCTL, val); 364 } 365 } 366 } 367 368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) 369 { 370 struct tegra_pcie_dw *pcie = arg; 371 struct dw_pcie *pci = &pcie->pci; 372 struct pcie_port *pp = &pci->pp; 373 u32 val, tmp; 374 u16 val_w; 375 376 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 377 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 378 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 379 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) { 380 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 381 382 /* SBR & Surprise Link Down WAR */ 383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 386 udelay(1); 387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 390 391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 392 val |= PORT_LOGIC_SPEED_CHANGE; 393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 394 } 395 } 396 397 if (val & APPL_INTR_STATUS_L0_INT_INT) { 398 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); 399 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) { 400 appl_writel(pcie, 401 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS, 402 APPL_INTR_STATUS_L1_8_0); 403 apply_bad_link_workaround(pp); 404 } 405 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { 406 appl_writel(pcie, 407 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, 408 APPL_INTR_STATUS_L1_8_0); 409 410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 411 PCI_EXP_LNKSTA); 412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & 413 PCI_EXP_LNKSTA_CLS); 414 } 415 } 416 417 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 418 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { 419 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18); 420 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 421 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { 422 dev_info(pci->dev, "CDM check complete\n"); 423 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE; 424 } 425 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) { 426 dev_err(pci->dev, "CDM comparison mismatch\n"); 427 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR; 428 } 429 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) { 430 dev_err(pci->dev, "CDM Logic error\n"); 431 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; 432 } 433 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp); 434 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); 435 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp); 436 } 437 438 return IRQ_HANDLED; 439 } 440 441 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) 442 { 443 u32 val; 444 445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 460 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2); 461 462 val = appl_readl(pcie, APPL_CTRL); 463 val |= APPL_CTRL_LTSSM_EN; 464 appl_writel(pcie, val, APPL_CTRL); 465 } 466 467 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) 468 { 469 struct tegra_pcie_dw *pcie = arg; 470 struct dw_pcie *pci = &pcie->pci; 471 u32 val, speed; 472 473 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 474 PCI_EXP_LNKSTA_CLS; 475 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 476 477 /* If EP doesn't advertise L1SS, just return */ 478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 479 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2))) 480 return IRQ_HANDLED; 481 482 /* Check if BME is set to '1' */ 483 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 484 if (val & PCI_COMMAND_MASTER) { 485 ktime_t timeout; 486 487 /* 110us for both snoop and no-snoop */ 488 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; 489 val |= (val << LTR_MST_NO_SNOOP_SHIFT); 490 appl_writel(pcie, val, APPL_LTR_MSG_1); 491 492 /* Send LTR upstream */ 493 val = appl_readl(pcie, APPL_LTR_MSG_2); 494 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; 495 appl_writel(pcie, val, APPL_LTR_MSG_2); 496 497 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT); 498 for (;;) { 499 val = appl_readl(pcie, APPL_LTR_MSG_2); 500 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)) 501 break; 502 if (ktime_after(ktime_get(), timeout)) 503 break; 504 usleep_range(1000, 1100); 505 } 506 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE) 507 dev_err(pcie->dev, "Failed to send LTR message\n"); 508 } 509 510 return IRQ_HANDLED; 511 } 512 513 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) 514 { 515 struct tegra_pcie_dw *pcie = arg; 516 struct dw_pcie_ep *ep = &pcie->pci.ep; 517 int spurious = 1; 518 u32 val, tmp; 519 520 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 521 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 522 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 523 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 524 525 if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) 526 pex_ep_event_hot_rst_done(pcie); 527 528 if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { 529 tmp = appl_readl(pcie, APPL_LINK_STATUS); 530 if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { 531 dev_dbg(pcie->dev, "Link is up with Host\n"); 532 dw_pcie_ep_linkup(ep); 533 } 534 } 535 536 spurious = 0; 537 } 538 539 if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { 540 val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); 541 appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); 542 543 if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) 544 return IRQ_WAKE_THREAD; 545 546 spurious = 0; 547 } 548 549 if (spurious) { 550 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", 551 val); 552 appl_writel(pcie, val, APPL_INTR_STATUS_L0); 553 } 554 555 return IRQ_HANDLED; 556 } 557 558 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, 559 int size, u32 *val) 560 { 561 /* 562 * This is an endpoint mode specific register happen to appear even 563 * when controller is operating in root port mode and system hangs 564 * when it is accessed with link being in ASPM-L1 state. 565 * So skip accessing it altogether 566 */ 567 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { 568 *val = 0x00000000; 569 return PCIBIOS_SUCCESSFUL; 570 } 571 572 return pci_generic_config_read(bus, devfn, where, size, val); 573 } 574 575 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, 576 int size, u32 val) 577 { 578 /* 579 * This is an endpoint mode specific register happen to appear even 580 * when controller is operating in root port mode and system hangs 581 * when it is accessed with link being in ASPM-L1 state. 582 * So skip accessing it altogether 583 */ 584 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) 585 return PCIBIOS_SUCCESSFUL; 586 587 return pci_generic_config_write(bus, devfn, where, size, val); 588 } 589 590 static struct pci_ops tegra_pci_ops = { 591 .map_bus = dw_pcie_own_conf_map_bus, 592 .read = tegra_pcie_dw_rd_own_conf, 593 .write = tegra_pcie_dw_wr_own_conf, 594 }; 595 596 #if defined(CONFIG_PCIEASPM) 597 static void disable_aspm_l11(struct tegra_pcie_dw *pcie) 598 { 599 u32 val; 600 601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 602 val &= ~PCI_L1SS_CAP_ASPM_L1_1; 603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 604 } 605 606 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) 607 { 608 u32 val; 609 610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 611 val &= ~PCI_L1SS_CAP_ASPM_L1_2; 612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 613 } 614 615 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) 616 { 617 u32 val; 618 619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); 620 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); 621 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 622 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT; 623 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); 626 627 return val; 628 } 629 630 static int aspm_state_cnt(struct seq_file *s, void *data) 631 { 632 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *) 633 dev_get_drvdata(s->private); 634 u32 val; 635 636 seq_printf(s, "Tx L0s entry count : %u\n", 637 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S)); 638 639 seq_printf(s, "Rx L0s entry count : %u\n", 640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S)); 641 642 seq_printf(s, "Link L1 entry count : %u\n", 643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1)); 644 645 seq_printf(s, "Link L1.1 entry count : %u\n", 646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1)); 647 648 seq_printf(s, "Link L1.2 entry count : %u\n", 649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2)); 650 651 /* Clear all counters */ 652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], 653 EVENT_COUNTER_ALL_CLEAR); 654 655 /* Re-enable counting */ 656 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 657 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 659 660 return 0; 661 } 662 663 static void init_host_aspm(struct tegra_pcie_dw *pcie) 664 { 665 struct dw_pcie *pci = &pcie->pci; 666 u32 val; 667 668 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; 670 671 /* Enable ASPM counters */ 672 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 673 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); 675 676 /* Program T_cmrt and T_pwr_on values */ 677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 678 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); 679 val |= (pcie->aspm_cmrt << 8); 680 val |= (pcie->aspm_pwr_on_t << 19); 681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); 682 683 /* Program L0s and L1 entrance latencies */ 684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 685 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; 686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); 687 val |= PORT_AFR_ENTER_ASPM; 688 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 689 } 690 691 static void init_debugfs(struct tegra_pcie_dw *pcie) 692 { 693 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, 694 aspm_state_cnt); 695 } 696 #else 697 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; } 698 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; } 699 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; } 700 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; } 701 #endif 702 703 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) 704 { 705 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 706 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 707 u32 val; 708 u16 val_w; 709 710 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 711 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 712 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 713 714 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 715 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN; 716 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 717 718 if (pcie->enable_cdm_check) { 719 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 720 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN; 721 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 722 723 val = appl_readl(pcie, APPL_INTR_EN_L1_18); 724 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR; 725 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR; 726 appl_writel(pcie, val, APPL_INTR_EN_L1_18); 727 } 728 729 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 730 PCI_EXP_LNKSTA); 731 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> 732 PCI_EXP_LNKSTA_NLW_SHIFT; 733 734 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 735 PCI_EXP_LNKCTL); 736 val_w |= PCI_EXP_LNKCTL_LBMIE; 737 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, 738 val_w); 739 } 740 741 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) 742 { 743 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 744 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 745 u32 val; 746 747 /* Enable legacy interrupt generation */ 748 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 749 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 750 val |= APPL_INTR_EN_L0_0_INT_INT_EN; 751 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 752 753 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); 754 val |= APPL_INTR_EN_L1_8_INTX_EN; 755 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; 756 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; 757 if (IS_ENABLED(CONFIG_PCIEAER)) 758 val |= APPL_INTR_EN_L1_8_AER_INT_EN; 759 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); 760 } 761 762 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) 763 { 764 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 765 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 766 u32 val; 767 768 dw_pcie_msi_init(pp); 769 770 /* Enable MSI interrupt generation */ 771 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 772 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; 773 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN; 774 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 775 } 776 777 static void tegra_pcie_enable_interrupts(struct pcie_port *pp) 778 { 779 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 780 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 781 782 /* Clear interrupt statuses before enabling interrupts */ 783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 796 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 797 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 798 799 tegra_pcie_enable_system_interrupts(pp); 800 tegra_pcie_enable_legacy_interrupts(pp); 801 if (IS_ENABLED(CONFIG_PCI_MSI)) 802 tegra_pcie_enable_msi_interrupts(pp); 803 } 804 805 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) 806 { 807 struct dw_pcie *pci = &pcie->pci; 808 u32 val, offset, i; 809 810 /* Program init preset */ 811 for (i = 0; i < pcie->num_lanes; i++) { 812 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2)); 813 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; 814 val |= GEN3_GEN4_EQ_PRESET_INIT; 815 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; 816 val |= (GEN3_GEN4_EQ_PRESET_INIT << 817 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT); 818 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); 819 820 offset = dw_pcie_find_ext_capability(pci, 821 PCI_EXT_CAP_ID_PL_16GT) + 822 PCI_PL_16GT_LE_CTRL; 823 val = dw_pcie_readb_dbi(pci, offset + i); 824 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; 825 val |= GEN3_GEN4_EQ_PRESET_INIT; 826 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; 827 val |= (GEN3_GEN4_EQ_PRESET_INIT << 828 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT); 829 dw_pcie_writeb_dbi(pci, offset + i, val); 830 } 831 832 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 833 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 834 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 835 836 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 837 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 838 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 839 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 840 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 841 842 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 843 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 844 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); 845 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 846 847 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 848 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 849 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 850 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 851 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 852 853 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 854 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 855 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 856 } 857 858 static void tegra_pcie_prepare_host(struct pcie_port *pp) 859 { 860 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 861 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 862 u32 val; 863 864 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); 865 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); 866 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); 867 868 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); 869 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; 870 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; 871 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); 872 873 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 874 875 /* Enable as 0xFFFF0001 response for CRS */ 876 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); 877 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); 878 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << 879 AMBA_ERROR_RESPONSE_CRS_SHIFT); 880 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); 881 882 /* Configure Max lane width from DT */ 883 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); 884 val &= ~PCI_EXP_LNKCAP_MLW; 885 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); 886 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); 887 888 config_gen3_gen4_eq_presets(pcie); 889 890 init_host_aspm(pcie); 891 892 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 893 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 894 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 895 896 if (pcie->update_fc_fixup) { 897 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 898 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 899 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 900 } 901 902 dw_pcie_setup_rc(pp); 903 904 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 905 906 /* Assert RST */ 907 val = appl_readl(pcie, APPL_PINMUX); 908 val &= ~APPL_PINMUX_PEX_RST; 909 appl_writel(pcie, val, APPL_PINMUX); 910 911 usleep_range(100, 200); 912 913 /* Enable LTSSM */ 914 val = appl_readl(pcie, APPL_CTRL); 915 val |= APPL_CTRL_LTSSM_EN; 916 appl_writel(pcie, val, APPL_CTRL); 917 918 /* De-assert RST */ 919 val = appl_readl(pcie, APPL_PINMUX); 920 val |= APPL_PINMUX_PEX_RST; 921 appl_writel(pcie, val, APPL_PINMUX); 922 923 msleep(100); 924 } 925 926 static int tegra_pcie_dw_host_init(struct pcie_port *pp) 927 { 928 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 929 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 930 u32 val, tmp, offset, speed; 931 932 pp->bridge->ops = &tegra_pci_ops; 933 934 tegra_pcie_prepare_host(pp); 935 936 if (dw_pcie_wait_for_link(pci)) { 937 /* 938 * There are some endpoints which can't get the link up if 939 * root port has Data Link Feature (DLF) enabled. 940 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info 941 * on Scaled Flow Control and DLF. 942 * So, need to confirm that is indeed the case here and attempt 943 * link up once again with DLF disabled. 944 */ 945 val = appl_readl(pcie, APPL_DEBUG); 946 val &= APPL_DEBUG_LTSSM_STATE_MASK; 947 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; 948 tmp = appl_readl(pcie, APPL_LINK_STATUS); 949 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP; 950 if (!(val == 0x11 && !tmp)) { 951 /* Link is down for all good reasons */ 952 return 0; 953 } 954 955 dev_info(pci->dev, "Link is down in DLL"); 956 dev_info(pci->dev, "Trying again with DLFE disabled\n"); 957 /* Disable LTSSM */ 958 val = appl_readl(pcie, APPL_CTRL); 959 val &= ~APPL_CTRL_LTSSM_EN; 960 appl_writel(pcie, val, APPL_CTRL); 961 962 reset_control_assert(pcie->core_rst); 963 reset_control_deassert(pcie->core_rst); 964 965 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); 966 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); 967 val &= ~PCI_DLF_EXCHANGE_ENABLE; 968 dw_pcie_writel_dbi(pci, offset, val); 969 970 tegra_pcie_prepare_host(pp); 971 972 if (dw_pcie_wait_for_link(pci)) 973 return 0; 974 } 975 976 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 977 PCI_EXP_LNKSTA_CLS; 978 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 979 980 tegra_pcie_enable_interrupts(pp); 981 982 return 0; 983 } 984 985 static int tegra_pcie_dw_link_up(struct dw_pcie *pci) 986 { 987 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 988 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 989 990 return !!(val & PCI_EXP_LNKSTA_DLLLA); 991 } 992 993 static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 994 { 995 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 996 997 enable_irq(pcie->pex_rst_irq); 998 999 return 0; 1000 } 1001 1002 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) 1003 { 1004 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1005 1006 disable_irq(pcie->pex_rst_irq); 1007 } 1008 1009 static const struct dw_pcie_ops tegra_dw_pcie_ops = { 1010 .link_up = tegra_pcie_dw_link_up, 1011 .start_link = tegra_pcie_dw_start_link, 1012 .stop_link = tegra_pcie_dw_stop_link, 1013 }; 1014 1015 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { 1016 .host_init = tegra_pcie_dw_host_init, 1017 }; 1018 1019 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) 1020 { 1021 unsigned int phy_count = pcie->phy_count; 1022 1023 while (phy_count--) { 1024 phy_power_off(pcie->phys[phy_count]); 1025 phy_exit(pcie->phys[phy_count]); 1026 } 1027 } 1028 1029 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) 1030 { 1031 unsigned int i; 1032 int ret; 1033 1034 for (i = 0; i < pcie->phy_count; i++) { 1035 ret = phy_init(pcie->phys[i]); 1036 if (ret < 0) 1037 goto phy_power_off; 1038 1039 ret = phy_power_on(pcie->phys[i]); 1040 if (ret < 0) 1041 goto phy_exit; 1042 } 1043 1044 return 0; 1045 1046 phy_power_off: 1047 while (i--) { 1048 phy_power_off(pcie->phys[i]); 1049 phy_exit: 1050 phy_exit(pcie->phys[i]); 1051 } 1052 1053 return ret; 1054 } 1055 1056 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) 1057 { 1058 struct device_node *np = pcie->dev->of_node; 1059 int ret; 1060 1061 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); 1062 if (ret < 0) { 1063 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); 1064 return ret; 1065 } 1066 1067 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", 1068 &pcie->aspm_pwr_on_t); 1069 if (ret < 0) 1070 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", 1071 ret); 1072 1073 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", 1074 &pcie->aspm_l0s_enter_lat); 1075 if (ret < 0) 1076 dev_info(pcie->dev, 1077 "Failed to read ASPM L0s Entrance latency: %d\n", ret); 1078 1079 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); 1080 if (ret < 0) { 1081 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); 1082 return ret; 1083 } 1084 1085 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); 1086 if (ret) { 1087 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); 1088 return ret; 1089 } 1090 1091 ret = of_property_count_strings(np, "phy-names"); 1092 if (ret < 0) { 1093 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", 1094 ret); 1095 return ret; 1096 } 1097 pcie->phy_count = ret; 1098 1099 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) 1100 pcie->update_fc_fixup = true; 1101 1102 pcie->supports_clkreq = 1103 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); 1104 1105 pcie->enable_cdm_check = 1106 of_property_read_bool(np, "snps,enable-cdm-check"); 1107 1108 if (pcie->mode == DW_PCIE_RC_TYPE) 1109 return 0; 1110 1111 /* Endpoint mode specific DT entries */ 1112 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); 1113 if (IS_ERR(pcie->pex_rst_gpiod)) { 1114 int err = PTR_ERR(pcie->pex_rst_gpiod); 1115 const char *level = KERN_ERR; 1116 1117 if (err == -EPROBE_DEFER) 1118 level = KERN_DEBUG; 1119 1120 dev_printk(level, pcie->dev, 1121 dev_fmt("Failed to get PERST GPIO: %d\n"), 1122 err); 1123 return err; 1124 } 1125 1126 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, 1127 "nvidia,refclk-select", 1128 GPIOD_OUT_HIGH); 1129 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { 1130 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); 1131 const char *level = KERN_ERR; 1132 1133 if (err == -EPROBE_DEFER) 1134 level = KERN_DEBUG; 1135 1136 dev_printk(level, pcie->dev, 1137 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"), 1138 err); 1139 pcie->pex_refclk_sel_gpiod = NULL; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, 1146 bool enable) 1147 { 1148 struct mrq_uphy_response resp; 1149 struct tegra_bpmp_message msg; 1150 struct mrq_uphy_request req; 1151 1152 /* Controller-5 doesn't need to have its state set by BPMP-FW */ 1153 if (pcie->cid == 5) 1154 return 0; 1155 1156 memset(&req, 0, sizeof(req)); 1157 memset(&resp, 0, sizeof(resp)); 1158 1159 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE; 1160 req.controller_state.pcie_controller = pcie->cid; 1161 req.controller_state.enable = enable; 1162 1163 memset(&msg, 0, sizeof(msg)); 1164 msg.mrq = MRQ_UPHY; 1165 msg.tx.data = &req; 1166 msg.tx.size = sizeof(req); 1167 msg.rx.data = &resp; 1168 msg.rx.size = sizeof(resp); 1169 1170 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1171 } 1172 1173 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, 1174 bool enable) 1175 { 1176 struct mrq_uphy_response resp; 1177 struct tegra_bpmp_message msg; 1178 struct mrq_uphy_request req; 1179 1180 memset(&req, 0, sizeof(req)); 1181 memset(&resp, 0, sizeof(resp)); 1182 1183 if (enable) { 1184 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT; 1185 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; 1186 } else { 1187 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF; 1188 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; 1189 } 1190 1191 memset(&msg, 0, sizeof(msg)); 1192 msg.mrq = MRQ_UPHY; 1193 msg.tx.data = &req; 1194 msg.tx.size = sizeof(req); 1195 msg.rx.data = &resp; 1196 msg.rx.size = sizeof(resp); 1197 1198 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1199 } 1200 1201 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) 1202 { 1203 struct pcie_port *pp = &pcie->pci.pp; 1204 struct pci_bus *child, *root_bus = NULL; 1205 struct pci_dev *pdev; 1206 1207 /* 1208 * link doesn't go into L2 state with some of the endpoints with Tegra 1209 * if they are not in D0 state. So, need to make sure that immediate 1210 * downstream devices are in D0 state before sending PME_TurnOff to put 1211 * link into L2 state. 1212 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, 1213 * 5.2 Link State Power Management (Page #428). 1214 */ 1215 1216 list_for_each_entry(child, &pp->bridge->bus->children, node) { 1217 /* Bring downstream devices to D0 if they are not already in */ 1218 if (child->parent == pp->bridge->bus) { 1219 root_bus = child; 1220 break; 1221 } 1222 } 1223 1224 if (!root_bus) { 1225 dev_err(pcie->dev, "Failed to find downstream devices\n"); 1226 return; 1227 } 1228 1229 list_for_each_entry(pdev, &root_bus->devices, bus_list) { 1230 if (PCI_SLOT(pdev->devfn) == 0) { 1231 if (pci_set_power_state(pdev, PCI_D0)) 1232 dev_err(pcie->dev, 1233 "Failed to transition %s to D0 state\n", 1234 dev_name(&pdev->dev)); 1235 } 1236 } 1237 } 1238 1239 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) 1240 { 1241 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); 1242 if (IS_ERR(pcie->slot_ctl_3v3)) { 1243 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) 1244 return PTR_ERR(pcie->slot_ctl_3v3); 1245 1246 pcie->slot_ctl_3v3 = NULL; 1247 } 1248 1249 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); 1250 if (IS_ERR(pcie->slot_ctl_12v)) { 1251 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) 1252 return PTR_ERR(pcie->slot_ctl_12v); 1253 1254 pcie->slot_ctl_12v = NULL; 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) 1261 { 1262 int ret; 1263 1264 if (pcie->slot_ctl_3v3) { 1265 ret = regulator_enable(pcie->slot_ctl_3v3); 1266 if (ret < 0) { 1267 dev_err(pcie->dev, 1268 "Failed to enable 3.3V slot supply: %d\n", ret); 1269 return ret; 1270 } 1271 } 1272 1273 if (pcie->slot_ctl_12v) { 1274 ret = regulator_enable(pcie->slot_ctl_12v); 1275 if (ret < 0) { 1276 dev_err(pcie->dev, 1277 "Failed to enable 12V slot supply: %d\n", ret); 1278 goto fail_12v_enable; 1279 } 1280 } 1281 1282 /* 1283 * According to PCI Express Card Electromechanical Specification 1284 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) 1285 * should be a minimum of 100ms. 1286 */ 1287 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) 1288 msleep(100); 1289 1290 return 0; 1291 1292 fail_12v_enable: 1293 if (pcie->slot_ctl_3v3) 1294 regulator_disable(pcie->slot_ctl_3v3); 1295 return ret; 1296 } 1297 1298 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) 1299 { 1300 if (pcie->slot_ctl_12v) 1301 regulator_disable(pcie->slot_ctl_12v); 1302 if (pcie->slot_ctl_3v3) 1303 regulator_disable(pcie->slot_ctl_3v3); 1304 } 1305 1306 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, 1307 bool en_hw_hot_rst) 1308 { 1309 int ret; 1310 u32 val; 1311 1312 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true); 1313 if (ret) { 1314 dev_err(pcie->dev, 1315 "Failed to enable controller %u: %d\n", pcie->cid, ret); 1316 return ret; 1317 } 1318 1319 ret = tegra_pcie_enable_slot_regulators(pcie); 1320 if (ret < 0) 1321 goto fail_slot_reg_en; 1322 1323 ret = regulator_enable(pcie->pex_ctl_supply); 1324 if (ret < 0) { 1325 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); 1326 goto fail_reg_en; 1327 } 1328 1329 ret = clk_prepare_enable(pcie->core_clk); 1330 if (ret) { 1331 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); 1332 goto fail_core_clk; 1333 } 1334 1335 ret = reset_control_deassert(pcie->core_apb_rst); 1336 if (ret) { 1337 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", 1338 ret); 1339 goto fail_core_apb_rst; 1340 } 1341 1342 if (en_hw_hot_rst) { 1343 /* Enable HW_HOT_RST mode */ 1344 val = appl_readl(pcie, APPL_CTRL); 1345 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 1346 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 1347 val |= APPL_CTRL_HW_HOT_RST_EN; 1348 appl_writel(pcie, val, APPL_CTRL); 1349 } 1350 1351 ret = tegra_pcie_enable_phy(pcie); 1352 if (ret) { 1353 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); 1354 goto fail_phy; 1355 } 1356 1357 /* Update CFG base address */ 1358 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1359 APPL_CFG_BASE_ADDR); 1360 1361 /* Configure this core for RP mode operation */ 1362 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE); 1363 1364 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1365 1366 val = appl_readl(pcie, APPL_CTRL); 1367 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); 1368 1369 val = appl_readl(pcie, APPL_CFG_MISC); 1370 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1371 appl_writel(pcie, val, APPL_CFG_MISC); 1372 1373 if (!pcie->supports_clkreq) { 1374 val = appl_readl(pcie, APPL_PINMUX); 1375 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; 1376 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; 1377 appl_writel(pcie, val, APPL_PINMUX); 1378 } 1379 1380 /* Update iATU_DMA base address */ 1381 appl_writel(pcie, 1382 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1383 APPL_CFG_IATU_DMA_BASE_ADDR); 1384 1385 reset_control_deassert(pcie->core_rst); 1386 1387 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1388 PCI_CAP_ID_EXP); 1389 1390 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ 1391 if (!pcie->supports_clkreq) { 1392 disable_aspm_l11(pcie); 1393 disable_aspm_l12(pcie); 1394 } 1395 1396 return ret; 1397 1398 fail_phy: 1399 reset_control_assert(pcie->core_apb_rst); 1400 fail_core_apb_rst: 1401 clk_disable_unprepare(pcie->core_clk); 1402 fail_core_clk: 1403 regulator_disable(pcie->pex_ctl_supply); 1404 fail_reg_en: 1405 tegra_pcie_disable_slot_regulators(pcie); 1406 fail_slot_reg_en: 1407 tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1408 1409 return ret; 1410 } 1411 1412 static int __deinit_controller(struct tegra_pcie_dw *pcie) 1413 { 1414 int ret; 1415 1416 ret = reset_control_assert(pcie->core_rst); 1417 if (ret) { 1418 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", 1419 ret); 1420 return ret; 1421 } 1422 1423 tegra_pcie_disable_phy(pcie); 1424 1425 ret = reset_control_assert(pcie->core_apb_rst); 1426 if (ret) { 1427 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); 1428 return ret; 1429 } 1430 1431 clk_disable_unprepare(pcie->core_clk); 1432 1433 ret = regulator_disable(pcie->pex_ctl_supply); 1434 if (ret) { 1435 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); 1436 return ret; 1437 } 1438 1439 tegra_pcie_disable_slot_regulators(pcie); 1440 1441 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1442 if (ret) { 1443 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", 1444 pcie->cid, ret); 1445 return ret; 1446 } 1447 1448 return ret; 1449 } 1450 1451 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) 1452 { 1453 struct dw_pcie *pci = &pcie->pci; 1454 struct pcie_port *pp = &pci->pp; 1455 int ret; 1456 1457 ret = tegra_pcie_config_controller(pcie, false); 1458 if (ret < 0) 1459 return ret; 1460 1461 pp->ops = &tegra_pcie_dw_host_ops; 1462 1463 ret = dw_pcie_host_init(pp); 1464 if (ret < 0) { 1465 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); 1466 goto fail_host_init; 1467 } 1468 1469 return 0; 1470 1471 fail_host_init: 1472 return __deinit_controller(pcie); 1473 } 1474 1475 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) 1476 { 1477 u32 val; 1478 1479 if (!tegra_pcie_dw_link_up(&pcie->pci)) 1480 return 0; 1481 1482 val = appl_readl(pcie, APPL_RADM_STATUS); 1483 val |= APPL_PM_XMT_TURNOFF_STATE; 1484 appl_writel(pcie, val, APPL_RADM_STATUS); 1485 1486 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, 1487 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, 1488 1, PME_ACK_TIMEOUT); 1489 } 1490 1491 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) 1492 { 1493 u32 data; 1494 int err; 1495 1496 if (!tegra_pcie_dw_link_up(&pcie->pci)) { 1497 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); 1498 return; 1499 } 1500 1501 if (tegra_pcie_try_link_l2(pcie)) { 1502 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); 1503 /* 1504 * TX lane clock freq will reset to Gen1 only if link is in L2 1505 * or detect state. 1506 * So apply pex_rst to end point to force RP to go into detect 1507 * state 1508 */ 1509 data = appl_readl(pcie, APPL_PINMUX); 1510 data &= ~APPL_PINMUX_PEX_RST; 1511 appl_writel(pcie, data, APPL_PINMUX); 1512 1513 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, 1514 data, 1515 ((data & 1516 APPL_DEBUG_LTSSM_STATE_MASK) >> 1517 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1518 LTSSM_STATE_PRE_DETECT, 1519 1, LTSSM_TIMEOUT); 1520 if (err) { 1521 dev_info(pcie->dev, "Link didn't go to detect state\n"); 1522 } else { 1523 /* Disable LTSSM after link is in detect state */ 1524 data = appl_readl(pcie, APPL_CTRL); 1525 data &= ~APPL_CTRL_LTSSM_EN; 1526 appl_writel(pcie, data, APPL_CTRL); 1527 } 1528 } 1529 /* 1530 * DBI registers may not be accessible after this as PLL-E would be 1531 * down depending on how CLKREQ is pulled by end point 1532 */ 1533 data = appl_readl(pcie, APPL_PINMUX); 1534 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE); 1535 /* Cut REFCLK to slot */ 1536 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1537 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1538 appl_writel(pcie, data, APPL_PINMUX); 1539 } 1540 1541 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1542 { 1543 tegra_pcie_downstream_dev_to_D0(pcie); 1544 dw_pcie_host_deinit(&pcie->pci.pp); 1545 tegra_pcie_dw_pme_turnoff(pcie); 1546 1547 return __deinit_controller(pcie); 1548 } 1549 1550 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) 1551 { 1552 struct pcie_port *pp = &pcie->pci.pp; 1553 struct device *dev = pcie->dev; 1554 char *name; 1555 int ret; 1556 1557 pm_runtime_enable(dev); 1558 1559 ret = pm_runtime_get_sync(dev); 1560 if (ret < 0) { 1561 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1562 ret); 1563 goto fail_pm_get_sync; 1564 } 1565 1566 ret = pinctrl_pm_select_default_state(dev); 1567 if (ret < 0) { 1568 dev_err(dev, "Failed to configure sideband pins: %d\n", ret); 1569 goto fail_pm_get_sync; 1570 } 1571 1572 tegra_pcie_init_controller(pcie); 1573 1574 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); 1575 if (!pcie->link_state) { 1576 ret = -ENOMEDIUM; 1577 goto fail_host_init; 1578 } 1579 1580 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1581 if (!name) { 1582 ret = -ENOMEM; 1583 goto fail_host_init; 1584 } 1585 1586 pcie->debugfs = debugfs_create_dir(name, NULL); 1587 init_debugfs(pcie); 1588 1589 return ret; 1590 1591 fail_host_init: 1592 tegra_pcie_deinit_controller(pcie); 1593 fail_pm_get_sync: 1594 pm_runtime_put_sync(dev); 1595 pm_runtime_disable(dev); 1596 return ret; 1597 } 1598 1599 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) 1600 { 1601 u32 val; 1602 int ret; 1603 1604 if (pcie->ep_state == EP_STATE_DISABLED) 1605 return; 1606 1607 /* Disable LTSSM */ 1608 val = appl_readl(pcie, APPL_CTRL); 1609 val &= ~APPL_CTRL_LTSSM_EN; 1610 appl_writel(pcie, val, APPL_CTRL); 1611 1612 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, 1613 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> 1614 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1615 LTSSM_STATE_PRE_DETECT, 1616 1, LTSSM_TIMEOUT); 1617 if (ret) 1618 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); 1619 1620 reset_control_assert(pcie->core_rst); 1621 1622 tegra_pcie_disable_phy(pcie); 1623 1624 reset_control_assert(pcie->core_apb_rst); 1625 1626 clk_disable_unprepare(pcie->core_clk); 1627 1628 pm_runtime_put_sync(pcie->dev); 1629 1630 ret = tegra_pcie_bpmp_set_pll_state(pcie, false); 1631 if (ret) 1632 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); 1633 1634 pcie->ep_state = EP_STATE_DISABLED; 1635 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); 1636 } 1637 1638 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) 1639 { 1640 struct dw_pcie *pci = &pcie->pci; 1641 struct dw_pcie_ep *ep = &pci->ep; 1642 struct device *dev = pcie->dev; 1643 u32 val; 1644 int ret; 1645 1646 if (pcie->ep_state == EP_STATE_ENABLED) 1647 return; 1648 1649 ret = pm_runtime_get_sync(dev); 1650 if (ret < 0) { 1651 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1652 ret); 1653 return; 1654 } 1655 1656 ret = tegra_pcie_bpmp_set_pll_state(pcie, true); 1657 if (ret) { 1658 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret); 1659 goto fail_pll_init; 1660 } 1661 1662 ret = clk_prepare_enable(pcie->core_clk); 1663 if (ret) { 1664 dev_err(dev, "Failed to enable core clock: %d\n", ret); 1665 goto fail_core_clk_enable; 1666 } 1667 1668 ret = reset_control_deassert(pcie->core_apb_rst); 1669 if (ret) { 1670 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret); 1671 goto fail_core_apb_rst; 1672 } 1673 1674 ret = tegra_pcie_enable_phy(pcie); 1675 if (ret) { 1676 dev_err(dev, "Failed to enable PHY: %d\n", ret); 1677 goto fail_phy; 1678 } 1679 1680 /* Clear any stale interrupt statuses */ 1681 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 1682 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 1683 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 1684 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 1685 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 1686 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 1687 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 1688 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 1689 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 1690 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 1691 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 1692 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 1696 1697 /* configure this core for EP mode operation */ 1698 val = appl_readl(pcie, APPL_DM_TYPE); 1699 val &= ~APPL_DM_TYPE_MASK; 1700 val |= APPL_DM_TYPE_EP; 1701 appl_writel(pcie, val, APPL_DM_TYPE); 1702 1703 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1704 1705 val = appl_readl(pcie, APPL_CTRL); 1706 val |= APPL_CTRL_SYS_PRE_DET_STATE; 1707 val |= APPL_CTRL_HW_HOT_RST_EN; 1708 appl_writel(pcie, val, APPL_CTRL); 1709 1710 val = appl_readl(pcie, APPL_CFG_MISC); 1711 val |= APPL_CFG_MISC_SLV_EP_MODE; 1712 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1713 appl_writel(pcie, val, APPL_CFG_MISC); 1714 1715 val = appl_readl(pcie, APPL_PINMUX); 1716 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1717 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1718 appl_writel(pcie, val, APPL_PINMUX); 1719 1720 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1721 APPL_CFG_BASE_ADDR); 1722 1723 appl_writel(pcie, pcie->atu_dma_res->start & 1724 APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1725 APPL_CFG_IATU_DMA_BASE_ADDR); 1726 1727 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 1728 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 1729 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 1730 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; 1731 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 1732 1733 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 1734 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN; 1735 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; 1736 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 1737 1738 reset_control_deassert(pcie->core_rst); 1739 1740 if (pcie->update_fc_fixup) { 1741 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 1742 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 1743 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 1744 } 1745 1746 config_gen3_gen4_eq_presets(pcie); 1747 1748 init_host_aspm(pcie); 1749 1750 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 1751 if (!pcie->supports_clkreq) { 1752 disable_aspm_l11(pcie); 1753 disable_aspm_l12(pcie); 1754 } 1755 1756 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 1757 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 1758 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 1759 1760 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1761 PCI_CAP_ID_EXP); 1762 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 1763 1764 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); 1765 val |= MSIX_ADDR_MATCH_LOW_OFF_EN; 1766 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); 1767 val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); 1768 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); 1769 1770 ret = dw_pcie_ep_init_complete(ep); 1771 if (ret) { 1772 dev_err(dev, "Failed to complete initialization: %d\n", ret); 1773 goto fail_init_complete; 1774 } 1775 1776 dw_pcie_ep_init_notify(ep); 1777 1778 /* Enable LTSSM */ 1779 val = appl_readl(pcie, APPL_CTRL); 1780 val |= APPL_CTRL_LTSSM_EN; 1781 appl_writel(pcie, val, APPL_CTRL); 1782 1783 pcie->ep_state = EP_STATE_ENABLED; 1784 dev_dbg(dev, "Initialization of endpoint is completed\n"); 1785 1786 return; 1787 1788 fail_init_complete: 1789 reset_control_assert(pcie->core_rst); 1790 tegra_pcie_disable_phy(pcie); 1791 fail_phy: 1792 reset_control_assert(pcie->core_apb_rst); 1793 fail_core_apb_rst: 1794 clk_disable_unprepare(pcie->core_clk); 1795 fail_core_clk_enable: 1796 tegra_pcie_bpmp_set_pll_state(pcie, false); 1797 fail_pll_init: 1798 pm_runtime_put_sync(dev); 1799 } 1800 1801 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) 1802 { 1803 struct tegra_pcie_dw *pcie = arg; 1804 1805 if (gpiod_get_value(pcie->pex_rst_gpiod)) 1806 pex_ep_event_pex_rst_assert(pcie); 1807 else 1808 pex_ep_event_pex_rst_deassert(pcie); 1809 1810 return IRQ_HANDLED; 1811 } 1812 1813 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) 1814 { 1815 /* Tegra194 supports only INTA */ 1816 if (irq > 1) 1817 return -EINVAL; 1818 1819 appl_writel(pcie, 1, APPL_LEGACY_INTX); 1820 usleep_range(1000, 2000); 1821 appl_writel(pcie, 0, APPL_LEGACY_INTX); 1822 return 0; 1823 } 1824 1825 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) 1826 { 1827 if (unlikely(irq > 31)) 1828 return -EINVAL; 1829 1830 appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1); 1831 1832 return 0; 1833 } 1834 1835 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq) 1836 { 1837 struct dw_pcie_ep *ep = &pcie->pci.ep; 1838 1839 writel(irq, ep->msi_mem); 1840 1841 return 0; 1842 } 1843 1844 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1845 enum pci_epc_irq_type type, 1846 u16 interrupt_num) 1847 { 1848 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1849 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1850 1851 switch (type) { 1852 case PCI_EPC_IRQ_LEGACY: 1853 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); 1854 1855 case PCI_EPC_IRQ_MSI: 1856 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num); 1857 1858 case PCI_EPC_IRQ_MSIX: 1859 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num); 1860 1861 default: 1862 dev_err(pci->dev, "Unknown IRQ type\n"); 1863 return -EPERM; 1864 } 1865 1866 return 0; 1867 } 1868 1869 static const struct pci_epc_features tegra_pcie_epc_features = { 1870 .linkup_notifier = true, 1871 .core_init_notifier = true, 1872 .msi_capable = false, 1873 .msix_capable = false, 1874 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5, 1875 .bar_fixed_64bit = 1 << BAR_0, 1876 .bar_fixed_size[0] = SZ_1M, 1877 }; 1878 1879 static const struct pci_epc_features* 1880 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) 1881 { 1882 return &tegra_pcie_epc_features; 1883 } 1884 1885 static struct dw_pcie_ep_ops pcie_ep_ops = { 1886 .raise_irq = tegra_pcie_ep_raise_irq, 1887 .get_features = tegra_pcie_ep_get_features, 1888 }; 1889 1890 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, 1891 struct platform_device *pdev) 1892 { 1893 struct dw_pcie *pci = &pcie->pci; 1894 struct device *dev = pcie->dev; 1895 struct dw_pcie_ep *ep; 1896 char *name; 1897 int ret; 1898 1899 ep = &pci->ep; 1900 ep->ops = &pcie_ep_ops; 1901 1902 ep->page_size = SZ_64K; 1903 1904 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); 1905 if (ret < 0) { 1906 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n", 1907 ret); 1908 return ret; 1909 } 1910 1911 ret = gpiod_to_irq(pcie->pex_rst_gpiod); 1912 if (ret < 0) { 1913 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret); 1914 return ret; 1915 } 1916 pcie->pex_rst_irq = (unsigned int)ret; 1917 1918 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq", 1919 pcie->cid); 1920 if (!name) { 1921 dev_err(dev, "Failed to create PERST IRQ string\n"); 1922 return -ENOMEM; 1923 } 1924 1925 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); 1926 1927 pcie->ep_state = EP_STATE_DISABLED; 1928 1929 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, 1930 tegra_pcie_ep_pex_rst_irq, 1931 IRQF_TRIGGER_RISING | 1932 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1933 name, (void *)pcie); 1934 if (ret < 0) { 1935 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); 1936 return ret; 1937 } 1938 1939 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work", 1940 pcie->cid); 1941 if (!name) { 1942 dev_err(dev, "Failed to create PCIe EP work thread string\n"); 1943 return -ENOMEM; 1944 } 1945 1946 pm_runtime_enable(dev); 1947 1948 ret = dw_pcie_ep_init(ep); 1949 if (ret) { 1950 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n", 1951 ret); 1952 return ret; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static int tegra_pcie_dw_probe(struct platform_device *pdev) 1959 { 1960 const struct tegra_pcie_dw_of_data *data; 1961 struct device *dev = &pdev->dev; 1962 struct resource *atu_dma_res; 1963 struct tegra_pcie_dw *pcie; 1964 struct pcie_port *pp; 1965 struct dw_pcie *pci; 1966 struct phy **phys; 1967 char *name; 1968 int ret; 1969 u32 i; 1970 1971 data = of_device_get_match_data(dev); 1972 1973 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1974 if (!pcie) 1975 return -ENOMEM; 1976 1977 pci = &pcie->pci; 1978 pci->dev = &pdev->dev; 1979 pci->ops = &tegra_dw_pcie_ops; 1980 pci->n_fts[0] = N_FTS_VAL; 1981 pci->n_fts[1] = FTS_VAL; 1982 1983 pp = &pci->pp; 1984 pp->num_vectors = MAX_MSI_IRQS; 1985 pcie->dev = &pdev->dev; 1986 pcie->mode = (enum dw_pcie_device_mode)data->mode; 1987 1988 ret = tegra_pcie_dw_parse_dt(pcie); 1989 if (ret < 0) { 1990 const char *level = KERN_ERR; 1991 1992 if (ret == -EPROBE_DEFER) 1993 level = KERN_DEBUG; 1994 1995 dev_printk(level, dev, 1996 dev_fmt("Failed to parse device tree: %d\n"), 1997 ret); 1998 return ret; 1999 } 2000 2001 ret = tegra_pcie_get_slot_regulators(pcie); 2002 if (ret < 0) { 2003 const char *level = KERN_ERR; 2004 2005 if (ret == -EPROBE_DEFER) 2006 level = KERN_DEBUG; 2007 2008 dev_printk(level, dev, 2009 dev_fmt("Failed to get slot regulators: %d\n"), 2010 ret); 2011 return ret; 2012 } 2013 2014 if (pcie->pex_refclk_sel_gpiod) 2015 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); 2016 2017 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); 2018 if (IS_ERR(pcie->pex_ctl_supply)) { 2019 ret = PTR_ERR(pcie->pex_ctl_supply); 2020 if (ret != -EPROBE_DEFER) 2021 dev_err(dev, "Failed to get regulator: %ld\n", 2022 PTR_ERR(pcie->pex_ctl_supply)); 2023 return ret; 2024 } 2025 2026 pcie->core_clk = devm_clk_get(dev, "core"); 2027 if (IS_ERR(pcie->core_clk)) { 2028 dev_err(dev, "Failed to get core clock: %ld\n", 2029 PTR_ERR(pcie->core_clk)); 2030 return PTR_ERR(pcie->core_clk); 2031 } 2032 2033 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2034 "appl"); 2035 if (!pcie->appl_res) { 2036 dev_err(dev, "Failed to find \"appl\" region\n"); 2037 return -ENODEV; 2038 } 2039 2040 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); 2041 if (IS_ERR(pcie->appl_base)) 2042 return PTR_ERR(pcie->appl_base); 2043 2044 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); 2045 if (IS_ERR(pcie->core_apb_rst)) { 2046 dev_err(dev, "Failed to get APB reset: %ld\n", 2047 PTR_ERR(pcie->core_apb_rst)); 2048 return PTR_ERR(pcie->core_apb_rst); 2049 } 2050 2051 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); 2052 if (!phys) 2053 return -ENOMEM; 2054 2055 for (i = 0; i < pcie->phy_count; i++) { 2056 name = kasprintf(GFP_KERNEL, "p2u-%u", i); 2057 if (!name) { 2058 dev_err(dev, "Failed to create P2U string\n"); 2059 return -ENOMEM; 2060 } 2061 phys[i] = devm_phy_get(dev, name); 2062 kfree(name); 2063 if (IS_ERR(phys[i])) { 2064 ret = PTR_ERR(phys[i]); 2065 if (ret != -EPROBE_DEFER) 2066 dev_err(dev, "Failed to get PHY: %d\n", ret); 2067 return ret; 2068 } 2069 } 2070 2071 pcie->phys = phys; 2072 2073 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2074 "atu_dma"); 2075 if (!atu_dma_res) { 2076 dev_err(dev, "Failed to find \"atu_dma\" region\n"); 2077 return -ENODEV; 2078 } 2079 pcie->atu_dma_res = atu_dma_res; 2080 2081 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); 2082 if (IS_ERR(pci->atu_base)) 2083 return PTR_ERR(pci->atu_base); 2084 2085 pcie->core_rst = devm_reset_control_get(dev, "core"); 2086 if (IS_ERR(pcie->core_rst)) { 2087 dev_err(dev, "Failed to get core reset: %ld\n", 2088 PTR_ERR(pcie->core_rst)); 2089 return PTR_ERR(pcie->core_rst); 2090 } 2091 2092 pp->irq = platform_get_irq_byname(pdev, "intr"); 2093 if (pp->irq < 0) 2094 return pp->irq; 2095 2096 pcie->bpmp = tegra_bpmp_get(dev); 2097 if (IS_ERR(pcie->bpmp)) 2098 return PTR_ERR(pcie->bpmp); 2099 2100 platform_set_drvdata(pdev, pcie); 2101 2102 switch (pcie->mode) { 2103 case DW_PCIE_RC_TYPE: 2104 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, 2105 IRQF_SHARED, "tegra-pcie-intr", pcie); 2106 if (ret) { 2107 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2108 ret); 2109 goto fail; 2110 } 2111 2112 ret = tegra_pcie_config_rp(pcie); 2113 if (ret && ret != -ENOMEDIUM) 2114 goto fail; 2115 else 2116 return 0; 2117 break; 2118 2119 case DW_PCIE_EP_TYPE: 2120 ret = devm_request_threaded_irq(dev, pp->irq, 2121 tegra_pcie_ep_hard_irq, 2122 tegra_pcie_ep_irq_thread, 2123 IRQF_SHARED | IRQF_ONESHOT, 2124 "tegra-pcie-ep-intr", pcie); 2125 if (ret) { 2126 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2127 ret); 2128 goto fail; 2129 } 2130 2131 ret = tegra_pcie_config_ep(pcie, pdev); 2132 if (ret < 0) 2133 goto fail; 2134 break; 2135 2136 default: 2137 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); 2138 } 2139 2140 fail: 2141 tegra_bpmp_put(pcie->bpmp); 2142 return ret; 2143 } 2144 2145 static int tegra_pcie_dw_remove(struct platform_device *pdev) 2146 { 2147 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2148 2149 if (!pcie->link_state) 2150 return 0; 2151 2152 debugfs_remove_recursive(pcie->debugfs); 2153 tegra_pcie_deinit_controller(pcie); 2154 pm_runtime_put_sync(pcie->dev); 2155 pm_runtime_disable(pcie->dev); 2156 tegra_bpmp_put(pcie->bpmp); 2157 if (pcie->pex_refclk_sel_gpiod) 2158 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); 2159 2160 return 0; 2161 } 2162 2163 static int tegra_pcie_dw_suspend_late(struct device *dev) 2164 { 2165 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2166 u32 val; 2167 2168 if (!pcie->link_state) 2169 return 0; 2170 2171 /* Enable HW_HOT_RST mode */ 2172 val = appl_readl(pcie, APPL_CTRL); 2173 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2174 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2175 val |= APPL_CTRL_HW_HOT_RST_EN; 2176 appl_writel(pcie, val, APPL_CTRL); 2177 2178 return 0; 2179 } 2180 2181 static int tegra_pcie_dw_suspend_noirq(struct device *dev) 2182 { 2183 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2184 2185 if (!pcie->link_state) 2186 return 0; 2187 2188 /* Save MSI interrupt vector */ 2189 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, 2190 PORT_LOGIC_MSI_CTRL_INT_0_EN); 2191 tegra_pcie_downstream_dev_to_D0(pcie); 2192 tegra_pcie_dw_pme_turnoff(pcie); 2193 2194 return __deinit_controller(pcie); 2195 } 2196 2197 static int tegra_pcie_dw_resume_noirq(struct device *dev) 2198 { 2199 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2200 int ret; 2201 2202 if (!pcie->link_state) 2203 return 0; 2204 2205 ret = tegra_pcie_config_controller(pcie, true); 2206 if (ret < 0) 2207 return ret; 2208 2209 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); 2210 if (ret < 0) { 2211 dev_err(dev, "Failed to init host: %d\n", ret); 2212 goto fail_host_init; 2213 } 2214 2215 /* Restore MSI interrupt vector */ 2216 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, 2217 pcie->msi_ctrl_int); 2218 2219 return 0; 2220 2221 fail_host_init: 2222 return __deinit_controller(pcie); 2223 } 2224 2225 static int tegra_pcie_dw_resume_early(struct device *dev) 2226 { 2227 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2228 u32 val; 2229 2230 if (!pcie->link_state) 2231 return 0; 2232 2233 /* Disable HW_HOT_RST mode */ 2234 val = appl_readl(pcie, APPL_CTRL); 2235 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2236 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2237 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << 2238 APPL_CTRL_HW_HOT_RST_MODE_SHIFT; 2239 val &= ~APPL_CTRL_HW_HOT_RST_EN; 2240 appl_writel(pcie, val, APPL_CTRL); 2241 2242 return 0; 2243 } 2244 2245 static void tegra_pcie_dw_shutdown(struct platform_device *pdev) 2246 { 2247 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2248 2249 if (!pcie->link_state) 2250 return; 2251 2252 debugfs_remove_recursive(pcie->debugfs); 2253 tegra_pcie_downstream_dev_to_D0(pcie); 2254 2255 disable_irq(pcie->pci.pp.irq); 2256 if (IS_ENABLED(CONFIG_PCI_MSI)) 2257 disable_irq(pcie->pci.pp.msi_irq); 2258 2259 tegra_pcie_dw_pme_turnoff(pcie); 2260 __deinit_controller(pcie); 2261 } 2262 2263 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { 2264 .mode = DW_PCIE_RC_TYPE, 2265 }; 2266 2267 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = { 2268 .mode = DW_PCIE_EP_TYPE, 2269 }; 2270 2271 static const struct of_device_id tegra_pcie_dw_of_match[] = { 2272 { 2273 .compatible = "nvidia,tegra194-pcie", 2274 .data = &tegra_pcie_dw_rc_of_data, 2275 }, 2276 { 2277 .compatible = "nvidia,tegra194-pcie-ep", 2278 .data = &tegra_pcie_dw_ep_of_data, 2279 }, 2280 {}, 2281 }; 2282 2283 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = { 2284 .suspend_late = tegra_pcie_dw_suspend_late, 2285 .suspend_noirq = tegra_pcie_dw_suspend_noirq, 2286 .resume_noirq = tegra_pcie_dw_resume_noirq, 2287 .resume_early = tegra_pcie_dw_resume_early, 2288 }; 2289 2290 static struct platform_driver tegra_pcie_dw_driver = { 2291 .probe = tegra_pcie_dw_probe, 2292 .remove = tegra_pcie_dw_remove, 2293 .shutdown = tegra_pcie_dw_shutdown, 2294 .driver = { 2295 .name = "tegra194-pcie", 2296 .pm = &tegra_pcie_dw_pm_ops, 2297 .of_match_table = tegra_pcie_dw_of_match, 2298 }, 2299 }; 2300 module_platform_driver(tegra_pcie_dw_driver); 2301 2302 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); 2303 2304 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 2305 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); 2306 MODULE_LICENSE("GPL v2"); 2307