1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for Tegra194 SoC 4 * 5 * Copyright (C) 2019 NVIDIA Corporation. 6 * 7 * Author: Vidya Sagar <vidyas@nvidia.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/reset.h> 31 #include <linux/resource.h> 32 #include <linux/types.h> 33 #include "pcie-designware.h" 34 #include <soc/tegra/bpmp.h> 35 #include <soc/tegra/bpmp-abi.h> 36 #include "../../pci.h" 37 38 #define APPL_PINMUX 0x0 39 #define APPL_PINMUX_PEX_RST BIT(0) 40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) 41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) 42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) 43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) 44 45 #define APPL_CTRL 0x4 46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) 47 #define APPL_CTRL_LTSSM_EN BIT(7) 48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20) 49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) 50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22 51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 52 53 #define APPL_INTR_EN_L0_0 0x8 54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0) 55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4) 56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8) 57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15) 58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19) 59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30) 60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31) 61 62 #define APPL_INTR_STATUS_L0 0xC 63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0) 64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8) 65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15) 66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16) 67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18) 68 69 #define APPL_INTR_EN_L1_0_0 0x1C 70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1) 71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3) 72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30) 73 74 #define APPL_INTR_STATUS_L1_0_0 0x20 75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1) 76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3) 77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30) 78 79 #define APPL_INTR_STATUS_L1_1 0x2C 80 #define APPL_INTR_STATUS_L1_2 0x30 81 #define APPL_INTR_STATUS_L1_3 0x34 82 #define APPL_INTR_STATUS_L1_6 0x3C 83 #define APPL_INTR_STATUS_L1_7 0x40 84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1) 85 86 #define APPL_INTR_EN_L1_8_0 0x44 87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) 88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) 89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) 90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) 91 92 #define APPL_INTR_STATUS_L1_8_0 0x4C 93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6) 94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2) 95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3) 96 97 #define APPL_INTR_STATUS_L1_9 0x54 98 #define APPL_INTR_STATUS_L1_10 0x58 99 #define APPL_INTR_STATUS_L1_11 0x64 100 #define APPL_INTR_STATUS_L1_13 0x74 101 #define APPL_INTR_STATUS_L1_14 0x78 102 #define APPL_INTR_STATUS_L1_15 0x7C 103 #define APPL_INTR_STATUS_L1_17 0x88 104 105 #define APPL_INTR_EN_L1_18 0x90 106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2) 107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 109 110 #define APPL_INTR_STATUS_L1_18 0x94 111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2) 112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) 113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) 114 115 #define APPL_MSI_CTRL_1 0xAC 116 117 #define APPL_MSI_CTRL_2 0xB0 118 119 #define APPL_LEGACY_INTX 0xB8 120 121 #define APPL_LTR_MSG_1 0xC4 122 #define LTR_MSG_REQ BIT(15) 123 #define LTR_MST_NO_SNOOP_SHIFT 16 124 125 #define APPL_LTR_MSG_2 0xC8 126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) 127 128 #define APPL_LINK_STATUS 0xCC 129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0) 130 131 #define APPL_DEBUG 0xD0 132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) 133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) 135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 136 #define LTSSM_STATE_PRE_DETECT 5 137 138 #define APPL_RADM_STATUS 0xE4 139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) 140 141 #define APPL_DM_TYPE 0x100 142 #define APPL_DM_TYPE_MASK GENMASK(3, 0) 143 #define APPL_DM_TYPE_RP 0x4 144 #define APPL_DM_TYPE_EP 0x0 145 146 #define APPL_CFG_BASE_ADDR 0x104 147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12) 148 149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108 150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18) 151 152 #define APPL_CFG_MISC 0x110 153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) 154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10) 155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10 156 #define APPL_CFG_MISC_ARCACHE_VAL 3 157 158 #define APPL_CFG_SLCG_OVERRIDE 0x114 159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0) 160 161 #define APPL_CAR_RESET_OVRD 0x12C 162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0) 163 164 #define IO_BASE_IO_DECODE BIT(0) 165 #define IO_BASE_IO_DECODE_BIT8 BIT(8) 166 167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0) 168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) 169 170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718 171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19) 172 173 #define EVENT_COUNTER_ALL_CLEAR 0x3 174 #define EVENT_COUNTER_ENABLE_ALL 0x7 175 #define EVENT_COUNTER_ENABLE_SHIFT 2 176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) 177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 180 #define EVENT_COUNTER_EVENT_L1 0x5 181 #define EVENT_COUNTER_EVENT_L1_1 0x7 182 #define EVENT_COUNTER_EVENT_L1_2 0x8 183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 184 #define EVENT_COUNTER_GROUP_5 0x5 185 186 #define N_FTS_VAL 52 187 #define FTS_VAL 52 188 189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 190 191 #define GEN3_EQ_CONTROL_OFF 0x8a8 192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8 193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) 194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) 195 196 #define GEN3_RELATED_OFF 0x890 197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) 198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 201 202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) 205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0 206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 208 209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940 210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) 211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) 212 213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944 214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0) 215 216 #define PORT_LOGIC_MSIX_DOORBELL 0x948 217 218 #define CAP_SPCIE_CAP_OFF 0x154 219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0) 220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) 221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 222 223 #define PME_ACK_TIMEOUT 10000 224 225 #define LTSSM_TIMEOUT 50000 /* 50ms */ 226 227 #define GEN3_GEN4_EQ_PRESET_INIT 5 228 229 #define GEN1_CORE_CLK_FREQ 62500000 230 #define GEN2_CORE_CLK_FREQ 125000000 231 #define GEN3_CORE_CLK_FREQ 250000000 232 #define GEN4_CORE_CLK_FREQ 500000000 233 234 #define LTR_MSG_TIMEOUT (100 * 1000) 235 236 #define PERST_DEBOUNCE_TIME (5 * 1000) 237 238 #define EP_STATE_DISABLED 0 239 #define EP_STATE_ENABLED 1 240 241 static const unsigned int pcie_gen_freq[] = { 242 GEN1_CORE_CLK_FREQ, 243 GEN2_CORE_CLK_FREQ, 244 GEN3_CORE_CLK_FREQ, 245 GEN4_CORE_CLK_FREQ 246 }; 247 248 static const u32 event_cntr_ctrl_offset[] = { 249 0x1d8, 250 0x1a8, 251 0x1a8, 252 0x1a8, 253 0x1c4, 254 0x1d8 255 }; 256 257 static const u32 event_cntr_data_offset[] = { 258 0x1dc, 259 0x1ac, 260 0x1ac, 261 0x1ac, 262 0x1c8, 263 0x1dc 264 }; 265 266 struct tegra_pcie_dw { 267 struct device *dev; 268 struct resource *appl_res; 269 struct resource *dbi_res; 270 struct resource *atu_dma_res; 271 void __iomem *appl_base; 272 struct clk *core_clk; 273 struct reset_control *core_apb_rst; 274 struct reset_control *core_rst; 275 struct dw_pcie pci; 276 struct tegra_bpmp *bpmp; 277 278 enum dw_pcie_device_mode mode; 279 280 bool supports_clkreq; 281 bool enable_cdm_check; 282 bool link_state; 283 bool update_fc_fixup; 284 u8 init_link_width; 285 u32 msi_ctrl_int; 286 u32 num_lanes; 287 u32 cid; 288 u32 cfg_link_cap_l1sub; 289 u32 pcie_cap_base; 290 u32 aspm_cmrt; 291 u32 aspm_pwr_on_t; 292 u32 aspm_l0s_enter_lat; 293 294 struct regulator *pex_ctl_supply; 295 struct regulator *slot_ctl_3v3; 296 struct regulator *slot_ctl_12v; 297 298 unsigned int phy_count; 299 struct phy **phys; 300 301 struct dentry *debugfs; 302 303 /* Endpoint mode specific */ 304 struct gpio_desc *pex_rst_gpiod; 305 struct gpio_desc *pex_refclk_sel_gpiod; 306 unsigned int pex_rst_irq; 307 int ep_state; 308 }; 309 310 struct tegra_pcie_dw_of_data { 311 enum dw_pcie_device_mode mode; 312 }; 313 314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) 315 { 316 return container_of(pci, struct tegra_pcie_dw, pci); 317 } 318 319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, 320 const u32 reg) 321 { 322 writel_relaxed(value, pcie->appl_base + reg); 323 } 324 325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) 326 { 327 return readl_relaxed(pcie->appl_base + reg); 328 } 329 330 struct tegra_pcie_soc { 331 enum dw_pcie_device_mode mode; 332 }; 333 334 static void apply_bad_link_workaround(struct pcie_port *pp) 335 { 336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 338 u32 current_link_width; 339 u16 val; 340 341 /* 342 * NOTE:- Since this scenario is uncommon and link as such is not 343 * stable anyway, not waiting to confirm if link is really 344 * transitioning to Gen-2 speed 345 */ 346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 347 if (val & PCI_EXP_LNKSTA_LBMS) { 348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> 349 PCI_EXP_LNKSTA_NLW_SHIFT; 350 if (pcie->init_link_width > current_link_width) { 351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); 352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 353 PCI_EXP_LNKCTL2); 354 val &= ~PCI_EXP_LNKCTL2_TLS; 355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT; 356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 357 PCI_EXP_LNKCTL2, val); 358 359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 360 PCI_EXP_LNKCTL); 361 val |= PCI_EXP_LNKCTL_RL; 362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + 363 PCI_EXP_LNKCTL, val); 364 } 365 } 366 } 367 368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) 369 { 370 struct tegra_pcie_dw *pcie = arg; 371 struct dw_pcie *pci = &pcie->pci; 372 struct pcie_port *pp = &pci->pp; 373 u32 val, tmp; 374 u16 val_w; 375 376 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 377 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 378 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 379 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) { 380 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 381 382 /* SBR & Surprise Link Down WAR */ 383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 386 udelay(1); 387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD); 388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; 389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); 390 391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 392 val |= PORT_LOGIC_SPEED_CHANGE; 393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 394 } 395 } 396 397 if (val & APPL_INTR_STATUS_L0_INT_INT) { 398 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); 399 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) { 400 appl_writel(pcie, 401 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS, 402 APPL_INTR_STATUS_L1_8_0); 403 apply_bad_link_workaround(pp); 404 } 405 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { 406 appl_writel(pcie, 407 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, 408 APPL_INTR_STATUS_L1_8_0); 409 410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + 411 PCI_EXP_LNKSTA); 412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & 413 PCI_EXP_LNKSTA_CLS); 414 } 415 } 416 417 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 418 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { 419 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18); 420 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 421 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { 422 dev_info(pci->dev, "CDM check complete\n"); 423 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE; 424 } 425 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) { 426 dev_err(pci->dev, "CDM comparison mismatch\n"); 427 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR; 428 } 429 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) { 430 dev_err(pci->dev, "CDM Logic error\n"); 431 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; 432 } 433 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp); 434 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); 435 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp); 436 } 437 438 return IRQ_HANDLED; 439 } 440 441 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) 442 { 443 u32 val; 444 445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 460 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2); 461 462 val = appl_readl(pcie, APPL_CTRL); 463 val |= APPL_CTRL_LTSSM_EN; 464 appl_writel(pcie, val, APPL_CTRL); 465 } 466 467 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) 468 { 469 struct tegra_pcie_dw *pcie = arg; 470 struct dw_pcie *pci = &pcie->pci; 471 u32 val, speed; 472 473 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 474 PCI_EXP_LNKSTA_CLS; 475 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 476 477 /* If EP doesn't advertise L1SS, just return */ 478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 479 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2))) 480 return IRQ_HANDLED; 481 482 /* Check if BME is set to '1' */ 483 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 484 if (val & PCI_COMMAND_MASTER) { 485 ktime_t timeout; 486 487 /* 110us for both snoop and no-snoop */ 488 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; 489 val |= (val << LTR_MST_NO_SNOOP_SHIFT); 490 appl_writel(pcie, val, APPL_LTR_MSG_1); 491 492 /* Send LTR upstream */ 493 val = appl_readl(pcie, APPL_LTR_MSG_2); 494 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; 495 appl_writel(pcie, val, APPL_LTR_MSG_2); 496 497 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT); 498 for (;;) { 499 val = appl_readl(pcie, APPL_LTR_MSG_2); 500 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)) 501 break; 502 if (ktime_after(ktime_get(), timeout)) 503 break; 504 usleep_range(1000, 1100); 505 } 506 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE) 507 dev_err(pcie->dev, "Failed to send LTR message\n"); 508 } 509 510 return IRQ_HANDLED; 511 } 512 513 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) 514 { 515 struct tegra_pcie_dw *pcie = arg; 516 struct dw_pcie_ep *ep = &pcie->pci.ep; 517 int spurious = 1; 518 u32 val, tmp; 519 520 val = appl_readl(pcie, APPL_INTR_STATUS_L0); 521 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { 522 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); 523 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); 524 525 if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) 526 pex_ep_event_hot_rst_done(pcie); 527 528 if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { 529 tmp = appl_readl(pcie, APPL_LINK_STATUS); 530 if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { 531 dev_dbg(pcie->dev, "Link is up with Host\n"); 532 dw_pcie_ep_linkup(ep); 533 } 534 } 535 536 spurious = 0; 537 } 538 539 if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { 540 val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); 541 appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); 542 543 if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) 544 return IRQ_WAKE_THREAD; 545 546 spurious = 0; 547 } 548 549 if (spurious) { 550 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", 551 val); 552 appl_writel(pcie, val, APPL_INTR_STATUS_L0); 553 } 554 555 return IRQ_HANDLED; 556 } 557 558 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, 559 int size, u32 *val) 560 { 561 /* 562 * This is an endpoint mode specific register happen to appear even 563 * when controller is operating in root port mode and system hangs 564 * when it is accessed with link being in ASPM-L1 state. 565 * So skip accessing it altogether 566 */ 567 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { 568 *val = 0x00000000; 569 return PCIBIOS_SUCCESSFUL; 570 } 571 572 return pci_generic_config_read(bus, devfn, where, size, val); 573 } 574 575 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, 576 int size, u32 val) 577 { 578 /* 579 * This is an endpoint mode specific register happen to appear even 580 * when controller is operating in root port mode and system hangs 581 * when it is accessed with link being in ASPM-L1 state. 582 * So skip accessing it altogether 583 */ 584 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) 585 return PCIBIOS_SUCCESSFUL; 586 587 return pci_generic_config_write(bus, devfn, where, size, val); 588 } 589 590 static struct pci_ops tegra_pci_ops = { 591 .map_bus = dw_pcie_own_conf_map_bus, 592 .read = tegra_pcie_dw_rd_own_conf, 593 .write = tegra_pcie_dw_wr_own_conf, 594 }; 595 596 #if defined(CONFIG_PCIEASPM) 597 static void disable_aspm_l11(struct tegra_pcie_dw *pcie) 598 { 599 u32 val; 600 601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 602 val &= ~PCI_L1SS_CAP_ASPM_L1_1; 603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 604 } 605 606 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) 607 { 608 u32 val; 609 610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); 611 val &= ~PCI_L1SS_CAP_ASPM_L1_2; 612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); 613 } 614 615 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) 616 { 617 u32 val; 618 619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); 620 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); 621 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 622 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT; 623 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); 626 627 return val; 628 } 629 630 static int aspm_state_cnt(struct seq_file *s, void *data) 631 { 632 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *) 633 dev_get_drvdata(s->private); 634 u32 val; 635 636 seq_printf(s, "Tx L0s entry count : %u\n", 637 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S)); 638 639 seq_printf(s, "Rx L0s entry count : %u\n", 640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S)); 641 642 seq_printf(s, "Link L1 entry count : %u\n", 643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1)); 644 645 seq_printf(s, "Link L1.1 entry count : %u\n", 646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1)); 647 648 seq_printf(s, "Link L1.2 entry count : %u\n", 649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2)); 650 651 /* Clear all counters */ 652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], 653 EVENT_COUNTER_ALL_CLEAR); 654 655 /* Re-enable counting */ 656 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 657 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); 659 660 return 0; 661 } 662 663 static void init_host_aspm(struct tegra_pcie_dw *pcie) 664 { 665 struct dw_pcie *pci = &pcie->pci; 666 u32 val; 667 668 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; 670 671 /* Enable ASPM counters */ 672 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; 673 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; 674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); 675 676 /* Program T_cmrt and T_pwr_on values */ 677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); 678 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); 679 val |= (pcie->aspm_cmrt << 8); 680 val |= (pcie->aspm_pwr_on_t << 19); 681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); 682 683 /* Program L0s and L1 entrance latencies */ 684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 685 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; 686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); 687 val |= PORT_AFR_ENTER_ASPM; 688 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 689 } 690 691 static void init_debugfs(struct tegra_pcie_dw *pcie) 692 { 693 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, 694 aspm_state_cnt); 695 } 696 #else 697 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; } 698 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; } 699 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; } 700 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; } 701 #endif 702 703 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) 704 { 705 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 706 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 707 u32 val; 708 u16 val_w; 709 710 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 711 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 712 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 713 714 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 715 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN; 716 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 717 718 if (pcie->enable_cdm_check) { 719 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 720 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN; 721 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 722 723 val = appl_readl(pcie, APPL_INTR_EN_L1_18); 724 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR; 725 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR; 726 appl_writel(pcie, val, APPL_INTR_EN_L1_18); 727 } 728 729 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 730 PCI_EXP_LNKSTA); 731 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> 732 PCI_EXP_LNKSTA_NLW_SHIFT; 733 734 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 735 PCI_EXP_LNKCTL); 736 val_w |= PCI_EXP_LNKCTL_LBMIE; 737 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, 738 val_w); 739 } 740 741 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) 742 { 743 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 744 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 745 u32 val; 746 747 /* Enable legacy interrupt generation */ 748 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 749 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 750 val |= APPL_INTR_EN_L0_0_INT_INT_EN; 751 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 752 753 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); 754 val |= APPL_INTR_EN_L1_8_INTX_EN; 755 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; 756 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; 757 if (IS_ENABLED(CONFIG_PCIEAER)) 758 val |= APPL_INTR_EN_L1_8_AER_INT_EN; 759 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); 760 } 761 762 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) 763 { 764 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 765 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 766 u32 val; 767 768 /* Enable MSI interrupt generation */ 769 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 770 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; 771 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN; 772 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 773 } 774 775 static void tegra_pcie_enable_interrupts(struct pcie_port *pp) 776 { 777 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 778 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 779 780 /* Clear interrupt statuses before enabling interrupts */ 781 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 782 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 796 797 tegra_pcie_enable_system_interrupts(pp); 798 tegra_pcie_enable_legacy_interrupts(pp); 799 if (IS_ENABLED(CONFIG_PCI_MSI)) 800 tegra_pcie_enable_msi_interrupts(pp); 801 } 802 803 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) 804 { 805 struct dw_pcie *pci = &pcie->pci; 806 u32 val, offset, i; 807 808 /* Program init preset */ 809 for (i = 0; i < pcie->num_lanes; i++) { 810 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2)); 811 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; 812 val |= GEN3_GEN4_EQ_PRESET_INIT; 813 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; 814 val |= (GEN3_GEN4_EQ_PRESET_INIT << 815 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT); 816 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); 817 818 offset = dw_pcie_find_ext_capability(pci, 819 PCI_EXT_CAP_ID_PL_16GT) + 820 PCI_PL_16GT_LE_CTRL; 821 val = dw_pcie_readb_dbi(pci, offset + i); 822 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; 823 val |= GEN3_GEN4_EQ_PRESET_INIT; 824 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; 825 val |= (GEN3_GEN4_EQ_PRESET_INIT << 826 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT); 827 dw_pcie_writeb_dbi(pci, offset + i, val); 828 } 829 830 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 831 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 832 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 833 834 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 835 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 836 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 837 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 838 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 839 840 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 841 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 842 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); 843 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 844 845 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 846 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 847 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 848 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 849 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 850 851 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 852 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 853 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 854 } 855 856 static void tegra_pcie_prepare_host(struct pcie_port *pp) 857 { 858 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 859 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 860 u32 val; 861 862 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); 863 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); 864 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); 865 866 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); 867 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; 868 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; 869 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); 870 871 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 872 873 /* Enable as 0xFFFF0001 response for CRS */ 874 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); 875 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); 876 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << 877 AMBA_ERROR_RESPONSE_CRS_SHIFT); 878 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); 879 880 /* Configure Max lane width from DT */ 881 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); 882 val &= ~PCI_EXP_LNKCAP_MLW; 883 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); 884 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); 885 886 config_gen3_gen4_eq_presets(pcie); 887 888 init_host_aspm(pcie); 889 890 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 891 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 892 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 893 894 if (pcie->update_fc_fixup) { 895 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 896 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 897 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 898 } 899 900 dw_pcie_setup_rc(pp); 901 902 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 903 904 /* Assert RST */ 905 val = appl_readl(pcie, APPL_PINMUX); 906 val &= ~APPL_PINMUX_PEX_RST; 907 appl_writel(pcie, val, APPL_PINMUX); 908 909 usleep_range(100, 200); 910 911 /* Enable LTSSM */ 912 val = appl_readl(pcie, APPL_CTRL); 913 val |= APPL_CTRL_LTSSM_EN; 914 appl_writel(pcie, val, APPL_CTRL); 915 916 /* De-assert RST */ 917 val = appl_readl(pcie, APPL_PINMUX); 918 val |= APPL_PINMUX_PEX_RST; 919 appl_writel(pcie, val, APPL_PINMUX); 920 921 msleep(100); 922 } 923 924 static int tegra_pcie_dw_host_init(struct pcie_port *pp) 925 { 926 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 927 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 928 u32 val, tmp, offset, speed; 929 930 pp->bridge->ops = &tegra_pci_ops; 931 932 tegra_pcie_prepare_host(pp); 933 934 if (dw_pcie_wait_for_link(pci)) { 935 /* 936 * There are some endpoints which can't get the link up if 937 * root port has Data Link Feature (DLF) enabled. 938 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info 939 * on Scaled Flow Control and DLF. 940 * So, need to confirm that is indeed the case here and attempt 941 * link up once again with DLF disabled. 942 */ 943 val = appl_readl(pcie, APPL_DEBUG); 944 val &= APPL_DEBUG_LTSSM_STATE_MASK; 945 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; 946 tmp = appl_readl(pcie, APPL_LINK_STATUS); 947 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP; 948 if (!(val == 0x11 && !tmp)) { 949 /* Link is down for all good reasons */ 950 return 0; 951 } 952 953 dev_info(pci->dev, "Link is down in DLL"); 954 dev_info(pci->dev, "Trying again with DLFE disabled\n"); 955 /* Disable LTSSM */ 956 val = appl_readl(pcie, APPL_CTRL); 957 val &= ~APPL_CTRL_LTSSM_EN; 958 appl_writel(pcie, val, APPL_CTRL); 959 960 reset_control_assert(pcie->core_rst); 961 reset_control_deassert(pcie->core_rst); 962 963 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); 964 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); 965 val &= ~PCI_DLF_EXCHANGE_ENABLE; 966 dw_pcie_writel_dbi(pci, offset, val); 967 968 tegra_pcie_prepare_host(pp); 969 970 if (dw_pcie_wait_for_link(pci)) 971 return 0; 972 } 973 974 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 975 PCI_EXP_LNKSTA_CLS; 976 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 977 978 tegra_pcie_enable_interrupts(pp); 979 980 return 0; 981 } 982 983 static int tegra_pcie_dw_link_up(struct dw_pcie *pci) 984 { 985 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 986 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 987 988 return !!(val & PCI_EXP_LNKSTA_DLLLA); 989 } 990 991 static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 992 { 993 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 994 995 enable_irq(pcie->pex_rst_irq); 996 997 return 0; 998 } 999 1000 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) 1001 { 1002 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1003 1004 disable_irq(pcie->pex_rst_irq); 1005 } 1006 1007 static const struct dw_pcie_ops tegra_dw_pcie_ops = { 1008 .link_up = tegra_pcie_dw_link_up, 1009 .start_link = tegra_pcie_dw_start_link, 1010 .stop_link = tegra_pcie_dw_stop_link, 1011 }; 1012 1013 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { 1014 .host_init = tegra_pcie_dw_host_init, 1015 }; 1016 1017 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) 1018 { 1019 unsigned int phy_count = pcie->phy_count; 1020 1021 while (phy_count--) { 1022 phy_power_off(pcie->phys[phy_count]); 1023 phy_exit(pcie->phys[phy_count]); 1024 } 1025 } 1026 1027 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) 1028 { 1029 unsigned int i; 1030 int ret; 1031 1032 for (i = 0; i < pcie->phy_count; i++) { 1033 ret = phy_init(pcie->phys[i]); 1034 if (ret < 0) 1035 goto phy_power_off; 1036 1037 ret = phy_power_on(pcie->phys[i]); 1038 if (ret < 0) 1039 goto phy_exit; 1040 } 1041 1042 return 0; 1043 1044 phy_power_off: 1045 while (i--) { 1046 phy_power_off(pcie->phys[i]); 1047 phy_exit: 1048 phy_exit(pcie->phys[i]); 1049 } 1050 1051 return ret; 1052 } 1053 1054 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) 1055 { 1056 struct device_node *np = pcie->dev->of_node; 1057 int ret; 1058 1059 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); 1060 if (ret < 0) { 1061 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); 1062 return ret; 1063 } 1064 1065 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", 1066 &pcie->aspm_pwr_on_t); 1067 if (ret < 0) 1068 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", 1069 ret); 1070 1071 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", 1072 &pcie->aspm_l0s_enter_lat); 1073 if (ret < 0) 1074 dev_info(pcie->dev, 1075 "Failed to read ASPM L0s Entrance latency: %d\n", ret); 1076 1077 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); 1078 if (ret < 0) { 1079 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); 1080 return ret; 1081 } 1082 1083 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); 1084 if (ret) { 1085 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); 1086 return ret; 1087 } 1088 1089 ret = of_property_count_strings(np, "phy-names"); 1090 if (ret < 0) { 1091 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", 1092 ret); 1093 return ret; 1094 } 1095 pcie->phy_count = ret; 1096 1097 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) 1098 pcie->update_fc_fixup = true; 1099 1100 pcie->supports_clkreq = 1101 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); 1102 1103 pcie->enable_cdm_check = 1104 of_property_read_bool(np, "snps,enable-cdm-check"); 1105 1106 if (pcie->mode == DW_PCIE_RC_TYPE) 1107 return 0; 1108 1109 /* Endpoint mode specific DT entries */ 1110 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); 1111 if (IS_ERR(pcie->pex_rst_gpiod)) { 1112 int err = PTR_ERR(pcie->pex_rst_gpiod); 1113 const char *level = KERN_ERR; 1114 1115 if (err == -EPROBE_DEFER) 1116 level = KERN_DEBUG; 1117 1118 dev_printk(level, pcie->dev, 1119 dev_fmt("Failed to get PERST GPIO: %d\n"), 1120 err); 1121 return err; 1122 } 1123 1124 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, 1125 "nvidia,refclk-select", 1126 GPIOD_OUT_HIGH); 1127 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { 1128 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); 1129 const char *level = KERN_ERR; 1130 1131 if (err == -EPROBE_DEFER) 1132 level = KERN_DEBUG; 1133 1134 dev_printk(level, pcie->dev, 1135 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"), 1136 err); 1137 pcie->pex_refclk_sel_gpiod = NULL; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, 1144 bool enable) 1145 { 1146 struct mrq_uphy_response resp; 1147 struct tegra_bpmp_message msg; 1148 struct mrq_uphy_request req; 1149 1150 /* Controller-5 doesn't need to have its state set by BPMP-FW */ 1151 if (pcie->cid == 5) 1152 return 0; 1153 1154 memset(&req, 0, sizeof(req)); 1155 memset(&resp, 0, sizeof(resp)); 1156 1157 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE; 1158 req.controller_state.pcie_controller = pcie->cid; 1159 req.controller_state.enable = enable; 1160 1161 memset(&msg, 0, sizeof(msg)); 1162 msg.mrq = MRQ_UPHY; 1163 msg.tx.data = &req; 1164 msg.tx.size = sizeof(req); 1165 msg.rx.data = &resp; 1166 msg.rx.size = sizeof(resp); 1167 1168 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1169 } 1170 1171 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, 1172 bool enable) 1173 { 1174 struct mrq_uphy_response resp; 1175 struct tegra_bpmp_message msg; 1176 struct mrq_uphy_request req; 1177 1178 memset(&req, 0, sizeof(req)); 1179 memset(&resp, 0, sizeof(resp)); 1180 1181 if (enable) { 1182 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT; 1183 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; 1184 } else { 1185 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF; 1186 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; 1187 } 1188 1189 memset(&msg, 0, sizeof(msg)); 1190 msg.mrq = MRQ_UPHY; 1191 msg.tx.data = &req; 1192 msg.tx.size = sizeof(req); 1193 msg.rx.data = &resp; 1194 msg.rx.size = sizeof(resp); 1195 1196 return tegra_bpmp_transfer(pcie->bpmp, &msg); 1197 } 1198 1199 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) 1200 { 1201 struct pcie_port *pp = &pcie->pci.pp; 1202 struct pci_bus *child, *root_bus = NULL; 1203 struct pci_dev *pdev; 1204 1205 /* 1206 * link doesn't go into L2 state with some of the endpoints with Tegra 1207 * if they are not in D0 state. So, need to make sure that immediate 1208 * downstream devices are in D0 state before sending PME_TurnOff to put 1209 * link into L2 state. 1210 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, 1211 * 5.2 Link State Power Management (Page #428). 1212 */ 1213 1214 list_for_each_entry(child, &pp->bridge->bus->children, node) { 1215 /* Bring downstream devices to D0 if they are not already in */ 1216 if (child->parent == pp->bridge->bus) { 1217 root_bus = child; 1218 break; 1219 } 1220 } 1221 1222 if (!root_bus) { 1223 dev_err(pcie->dev, "Failed to find downstream devices\n"); 1224 return; 1225 } 1226 1227 list_for_each_entry(pdev, &root_bus->devices, bus_list) { 1228 if (PCI_SLOT(pdev->devfn) == 0) { 1229 if (pci_set_power_state(pdev, PCI_D0)) 1230 dev_err(pcie->dev, 1231 "Failed to transition %s to D0 state\n", 1232 dev_name(&pdev->dev)); 1233 } 1234 } 1235 } 1236 1237 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) 1238 { 1239 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); 1240 if (IS_ERR(pcie->slot_ctl_3v3)) { 1241 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) 1242 return PTR_ERR(pcie->slot_ctl_3v3); 1243 1244 pcie->slot_ctl_3v3 = NULL; 1245 } 1246 1247 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); 1248 if (IS_ERR(pcie->slot_ctl_12v)) { 1249 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) 1250 return PTR_ERR(pcie->slot_ctl_12v); 1251 1252 pcie->slot_ctl_12v = NULL; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) 1259 { 1260 int ret; 1261 1262 if (pcie->slot_ctl_3v3) { 1263 ret = regulator_enable(pcie->slot_ctl_3v3); 1264 if (ret < 0) { 1265 dev_err(pcie->dev, 1266 "Failed to enable 3.3V slot supply: %d\n", ret); 1267 return ret; 1268 } 1269 } 1270 1271 if (pcie->slot_ctl_12v) { 1272 ret = regulator_enable(pcie->slot_ctl_12v); 1273 if (ret < 0) { 1274 dev_err(pcie->dev, 1275 "Failed to enable 12V slot supply: %d\n", ret); 1276 goto fail_12v_enable; 1277 } 1278 } 1279 1280 /* 1281 * According to PCI Express Card Electromechanical Specification 1282 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) 1283 * should be a minimum of 100ms. 1284 */ 1285 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) 1286 msleep(100); 1287 1288 return 0; 1289 1290 fail_12v_enable: 1291 if (pcie->slot_ctl_3v3) 1292 regulator_disable(pcie->slot_ctl_3v3); 1293 return ret; 1294 } 1295 1296 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) 1297 { 1298 if (pcie->slot_ctl_12v) 1299 regulator_disable(pcie->slot_ctl_12v); 1300 if (pcie->slot_ctl_3v3) 1301 regulator_disable(pcie->slot_ctl_3v3); 1302 } 1303 1304 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, 1305 bool en_hw_hot_rst) 1306 { 1307 int ret; 1308 u32 val; 1309 1310 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true); 1311 if (ret) { 1312 dev_err(pcie->dev, 1313 "Failed to enable controller %u: %d\n", pcie->cid, ret); 1314 return ret; 1315 } 1316 1317 ret = tegra_pcie_enable_slot_regulators(pcie); 1318 if (ret < 0) 1319 goto fail_slot_reg_en; 1320 1321 ret = regulator_enable(pcie->pex_ctl_supply); 1322 if (ret < 0) { 1323 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); 1324 goto fail_reg_en; 1325 } 1326 1327 ret = clk_prepare_enable(pcie->core_clk); 1328 if (ret) { 1329 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); 1330 goto fail_core_clk; 1331 } 1332 1333 ret = reset_control_deassert(pcie->core_apb_rst); 1334 if (ret) { 1335 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", 1336 ret); 1337 goto fail_core_apb_rst; 1338 } 1339 1340 if (en_hw_hot_rst) { 1341 /* Enable HW_HOT_RST mode */ 1342 val = appl_readl(pcie, APPL_CTRL); 1343 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 1344 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 1345 val |= APPL_CTRL_HW_HOT_RST_EN; 1346 appl_writel(pcie, val, APPL_CTRL); 1347 } 1348 1349 ret = tegra_pcie_enable_phy(pcie); 1350 if (ret) { 1351 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); 1352 goto fail_phy; 1353 } 1354 1355 /* Update CFG base address */ 1356 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1357 APPL_CFG_BASE_ADDR); 1358 1359 /* Configure this core for RP mode operation */ 1360 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE); 1361 1362 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1363 1364 val = appl_readl(pcie, APPL_CTRL); 1365 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); 1366 1367 val = appl_readl(pcie, APPL_CFG_MISC); 1368 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1369 appl_writel(pcie, val, APPL_CFG_MISC); 1370 1371 if (!pcie->supports_clkreq) { 1372 val = appl_readl(pcie, APPL_PINMUX); 1373 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; 1374 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; 1375 appl_writel(pcie, val, APPL_PINMUX); 1376 } 1377 1378 /* Update iATU_DMA base address */ 1379 appl_writel(pcie, 1380 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1381 APPL_CFG_IATU_DMA_BASE_ADDR); 1382 1383 reset_control_deassert(pcie->core_rst); 1384 1385 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1386 PCI_CAP_ID_EXP); 1387 1388 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ 1389 if (!pcie->supports_clkreq) { 1390 disable_aspm_l11(pcie); 1391 disable_aspm_l12(pcie); 1392 } 1393 1394 return ret; 1395 1396 fail_phy: 1397 reset_control_assert(pcie->core_apb_rst); 1398 fail_core_apb_rst: 1399 clk_disable_unprepare(pcie->core_clk); 1400 fail_core_clk: 1401 regulator_disable(pcie->pex_ctl_supply); 1402 fail_reg_en: 1403 tegra_pcie_disable_slot_regulators(pcie); 1404 fail_slot_reg_en: 1405 tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1406 1407 return ret; 1408 } 1409 1410 static int __deinit_controller(struct tegra_pcie_dw *pcie) 1411 { 1412 int ret; 1413 1414 ret = reset_control_assert(pcie->core_rst); 1415 if (ret) { 1416 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", 1417 ret); 1418 return ret; 1419 } 1420 1421 tegra_pcie_disable_phy(pcie); 1422 1423 ret = reset_control_assert(pcie->core_apb_rst); 1424 if (ret) { 1425 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); 1426 return ret; 1427 } 1428 1429 clk_disable_unprepare(pcie->core_clk); 1430 1431 ret = regulator_disable(pcie->pex_ctl_supply); 1432 if (ret) { 1433 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); 1434 return ret; 1435 } 1436 1437 tegra_pcie_disable_slot_regulators(pcie); 1438 1439 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1440 if (ret) { 1441 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", 1442 pcie->cid, ret); 1443 return ret; 1444 } 1445 1446 return ret; 1447 } 1448 1449 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) 1450 { 1451 struct dw_pcie *pci = &pcie->pci; 1452 struct pcie_port *pp = &pci->pp; 1453 int ret; 1454 1455 ret = tegra_pcie_config_controller(pcie, false); 1456 if (ret < 0) 1457 return ret; 1458 1459 pp->ops = &tegra_pcie_dw_host_ops; 1460 1461 ret = dw_pcie_host_init(pp); 1462 if (ret < 0) { 1463 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); 1464 goto fail_host_init; 1465 } 1466 1467 return 0; 1468 1469 fail_host_init: 1470 return __deinit_controller(pcie); 1471 } 1472 1473 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) 1474 { 1475 u32 val; 1476 1477 if (!tegra_pcie_dw_link_up(&pcie->pci)) 1478 return 0; 1479 1480 val = appl_readl(pcie, APPL_RADM_STATUS); 1481 val |= APPL_PM_XMT_TURNOFF_STATE; 1482 appl_writel(pcie, val, APPL_RADM_STATUS); 1483 1484 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, 1485 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, 1486 1, PME_ACK_TIMEOUT); 1487 } 1488 1489 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) 1490 { 1491 u32 data; 1492 int err; 1493 1494 if (!tegra_pcie_dw_link_up(&pcie->pci)) { 1495 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); 1496 return; 1497 } 1498 1499 if (tegra_pcie_try_link_l2(pcie)) { 1500 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); 1501 /* 1502 * TX lane clock freq will reset to Gen1 only if link is in L2 1503 * or detect state. 1504 * So apply pex_rst to end point to force RP to go into detect 1505 * state 1506 */ 1507 data = appl_readl(pcie, APPL_PINMUX); 1508 data &= ~APPL_PINMUX_PEX_RST; 1509 appl_writel(pcie, data, APPL_PINMUX); 1510 1511 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, 1512 data, 1513 ((data & 1514 APPL_DEBUG_LTSSM_STATE_MASK) >> 1515 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1516 LTSSM_STATE_PRE_DETECT, 1517 1, LTSSM_TIMEOUT); 1518 if (err) { 1519 dev_info(pcie->dev, "Link didn't go to detect state\n"); 1520 } else { 1521 /* Disable LTSSM after link is in detect state */ 1522 data = appl_readl(pcie, APPL_CTRL); 1523 data &= ~APPL_CTRL_LTSSM_EN; 1524 appl_writel(pcie, data, APPL_CTRL); 1525 } 1526 } 1527 /* 1528 * DBI registers may not be accessible after this as PLL-E would be 1529 * down depending on how CLKREQ is pulled by end point 1530 */ 1531 data = appl_readl(pcie, APPL_PINMUX); 1532 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE); 1533 /* Cut REFCLK to slot */ 1534 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1535 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1536 appl_writel(pcie, data, APPL_PINMUX); 1537 } 1538 1539 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1540 { 1541 tegra_pcie_downstream_dev_to_D0(pcie); 1542 dw_pcie_host_deinit(&pcie->pci.pp); 1543 tegra_pcie_dw_pme_turnoff(pcie); 1544 1545 return __deinit_controller(pcie); 1546 } 1547 1548 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) 1549 { 1550 struct device *dev = pcie->dev; 1551 char *name; 1552 int ret; 1553 1554 pm_runtime_enable(dev); 1555 1556 ret = pm_runtime_get_sync(dev); 1557 if (ret < 0) { 1558 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1559 ret); 1560 goto fail_pm_get_sync; 1561 } 1562 1563 ret = pinctrl_pm_select_default_state(dev); 1564 if (ret < 0) { 1565 dev_err(dev, "Failed to configure sideband pins: %d\n", ret); 1566 goto fail_pm_get_sync; 1567 } 1568 1569 tegra_pcie_init_controller(pcie); 1570 1571 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); 1572 if (!pcie->link_state) { 1573 ret = -ENOMEDIUM; 1574 goto fail_host_init; 1575 } 1576 1577 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1578 if (!name) { 1579 ret = -ENOMEM; 1580 goto fail_host_init; 1581 } 1582 1583 pcie->debugfs = debugfs_create_dir(name, NULL); 1584 init_debugfs(pcie); 1585 1586 return ret; 1587 1588 fail_host_init: 1589 tegra_pcie_deinit_controller(pcie); 1590 fail_pm_get_sync: 1591 pm_runtime_put_sync(dev); 1592 pm_runtime_disable(dev); 1593 return ret; 1594 } 1595 1596 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) 1597 { 1598 u32 val; 1599 int ret; 1600 1601 if (pcie->ep_state == EP_STATE_DISABLED) 1602 return; 1603 1604 /* Disable LTSSM */ 1605 val = appl_readl(pcie, APPL_CTRL); 1606 val &= ~APPL_CTRL_LTSSM_EN; 1607 appl_writel(pcie, val, APPL_CTRL); 1608 1609 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, 1610 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> 1611 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1612 LTSSM_STATE_PRE_DETECT, 1613 1, LTSSM_TIMEOUT); 1614 if (ret) 1615 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); 1616 1617 reset_control_assert(pcie->core_rst); 1618 1619 tegra_pcie_disable_phy(pcie); 1620 1621 reset_control_assert(pcie->core_apb_rst); 1622 1623 clk_disable_unprepare(pcie->core_clk); 1624 1625 pm_runtime_put_sync(pcie->dev); 1626 1627 ret = tegra_pcie_bpmp_set_pll_state(pcie, false); 1628 if (ret) 1629 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); 1630 1631 pcie->ep_state = EP_STATE_DISABLED; 1632 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); 1633 } 1634 1635 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) 1636 { 1637 struct dw_pcie *pci = &pcie->pci; 1638 struct dw_pcie_ep *ep = &pci->ep; 1639 struct device *dev = pcie->dev; 1640 u32 val; 1641 int ret; 1642 1643 if (pcie->ep_state == EP_STATE_ENABLED) 1644 return; 1645 1646 ret = pm_runtime_get_sync(dev); 1647 if (ret < 0) { 1648 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", 1649 ret); 1650 return; 1651 } 1652 1653 ret = tegra_pcie_bpmp_set_pll_state(pcie, true); 1654 if (ret) { 1655 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret); 1656 goto fail_pll_init; 1657 } 1658 1659 ret = clk_prepare_enable(pcie->core_clk); 1660 if (ret) { 1661 dev_err(dev, "Failed to enable core clock: %d\n", ret); 1662 goto fail_core_clk_enable; 1663 } 1664 1665 ret = reset_control_deassert(pcie->core_apb_rst); 1666 if (ret) { 1667 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret); 1668 goto fail_core_apb_rst; 1669 } 1670 1671 ret = tegra_pcie_enable_phy(pcie); 1672 if (ret) { 1673 dev_err(dev, "Failed to enable PHY: %d\n", ret); 1674 goto fail_phy; 1675 } 1676 1677 /* Clear any stale interrupt statuses */ 1678 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); 1679 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); 1680 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); 1681 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); 1682 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); 1683 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); 1684 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); 1685 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); 1686 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); 1687 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); 1688 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); 1689 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); 1690 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); 1691 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); 1692 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); 1693 1694 /* configure this core for EP mode operation */ 1695 val = appl_readl(pcie, APPL_DM_TYPE); 1696 val &= ~APPL_DM_TYPE_MASK; 1697 val |= APPL_DM_TYPE_EP; 1698 appl_writel(pcie, val, APPL_DM_TYPE); 1699 1700 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); 1701 1702 val = appl_readl(pcie, APPL_CTRL); 1703 val |= APPL_CTRL_SYS_PRE_DET_STATE; 1704 val |= APPL_CTRL_HW_HOT_RST_EN; 1705 appl_writel(pcie, val, APPL_CTRL); 1706 1707 val = appl_readl(pcie, APPL_CFG_MISC); 1708 val |= APPL_CFG_MISC_SLV_EP_MODE; 1709 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); 1710 appl_writel(pcie, val, APPL_CFG_MISC); 1711 1712 val = appl_readl(pcie, APPL_PINMUX); 1713 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN; 1714 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE; 1715 appl_writel(pcie, val, APPL_PINMUX); 1716 1717 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, 1718 APPL_CFG_BASE_ADDR); 1719 1720 appl_writel(pcie, pcie->atu_dma_res->start & 1721 APPL_CFG_IATU_DMA_BASE_ADDR_MASK, 1722 APPL_CFG_IATU_DMA_BASE_ADDR); 1723 1724 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 1725 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; 1726 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; 1727 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; 1728 appl_writel(pcie, val, APPL_INTR_EN_L0_0); 1729 1730 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); 1731 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN; 1732 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; 1733 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 1734 1735 reset_control_deassert(pcie->core_rst); 1736 1737 if (pcie->update_fc_fixup) { 1738 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); 1739 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 1740 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 1741 } 1742 1743 config_gen3_gen4_eq_presets(pcie); 1744 1745 init_host_aspm(pcie); 1746 1747 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 1748 if (!pcie->supports_clkreq) { 1749 disable_aspm_l11(pcie); 1750 disable_aspm_l12(pcie); 1751 } 1752 1753 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 1754 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 1755 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 1756 1757 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1758 PCI_CAP_ID_EXP); 1759 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 1760 1761 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); 1762 val |= MSIX_ADDR_MATCH_LOW_OFF_EN; 1763 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); 1764 val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); 1765 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); 1766 1767 ret = dw_pcie_ep_init_complete(ep); 1768 if (ret) { 1769 dev_err(dev, "Failed to complete initialization: %d\n", ret); 1770 goto fail_init_complete; 1771 } 1772 1773 dw_pcie_ep_init_notify(ep); 1774 1775 /* Enable LTSSM */ 1776 val = appl_readl(pcie, APPL_CTRL); 1777 val |= APPL_CTRL_LTSSM_EN; 1778 appl_writel(pcie, val, APPL_CTRL); 1779 1780 pcie->ep_state = EP_STATE_ENABLED; 1781 dev_dbg(dev, "Initialization of endpoint is completed\n"); 1782 1783 return; 1784 1785 fail_init_complete: 1786 reset_control_assert(pcie->core_rst); 1787 tegra_pcie_disable_phy(pcie); 1788 fail_phy: 1789 reset_control_assert(pcie->core_apb_rst); 1790 fail_core_apb_rst: 1791 clk_disable_unprepare(pcie->core_clk); 1792 fail_core_clk_enable: 1793 tegra_pcie_bpmp_set_pll_state(pcie, false); 1794 fail_pll_init: 1795 pm_runtime_put_sync(dev); 1796 } 1797 1798 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) 1799 { 1800 struct tegra_pcie_dw *pcie = arg; 1801 1802 if (gpiod_get_value(pcie->pex_rst_gpiod)) 1803 pex_ep_event_pex_rst_assert(pcie); 1804 else 1805 pex_ep_event_pex_rst_deassert(pcie); 1806 1807 return IRQ_HANDLED; 1808 } 1809 1810 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) 1811 { 1812 /* Tegra194 supports only INTA */ 1813 if (irq > 1) 1814 return -EINVAL; 1815 1816 appl_writel(pcie, 1, APPL_LEGACY_INTX); 1817 usleep_range(1000, 2000); 1818 appl_writel(pcie, 0, APPL_LEGACY_INTX); 1819 return 0; 1820 } 1821 1822 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) 1823 { 1824 if (unlikely(irq > 31)) 1825 return -EINVAL; 1826 1827 appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1); 1828 1829 return 0; 1830 } 1831 1832 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq) 1833 { 1834 struct dw_pcie_ep *ep = &pcie->pci.ep; 1835 1836 writel(irq, ep->msi_mem); 1837 1838 return 0; 1839 } 1840 1841 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1842 enum pci_epc_irq_type type, 1843 u16 interrupt_num) 1844 { 1845 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1846 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1847 1848 switch (type) { 1849 case PCI_EPC_IRQ_LEGACY: 1850 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); 1851 1852 case PCI_EPC_IRQ_MSI: 1853 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num); 1854 1855 case PCI_EPC_IRQ_MSIX: 1856 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num); 1857 1858 default: 1859 dev_err(pci->dev, "Unknown IRQ type\n"); 1860 return -EPERM; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static const struct pci_epc_features tegra_pcie_epc_features = { 1867 .linkup_notifier = true, 1868 .core_init_notifier = true, 1869 .msi_capable = false, 1870 .msix_capable = false, 1871 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5, 1872 .bar_fixed_64bit = 1 << BAR_0, 1873 .bar_fixed_size[0] = SZ_1M, 1874 }; 1875 1876 static const struct pci_epc_features* 1877 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) 1878 { 1879 return &tegra_pcie_epc_features; 1880 } 1881 1882 static struct dw_pcie_ep_ops pcie_ep_ops = { 1883 .raise_irq = tegra_pcie_ep_raise_irq, 1884 .get_features = tegra_pcie_ep_get_features, 1885 }; 1886 1887 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, 1888 struct platform_device *pdev) 1889 { 1890 struct dw_pcie *pci = &pcie->pci; 1891 struct device *dev = pcie->dev; 1892 struct dw_pcie_ep *ep; 1893 char *name; 1894 int ret; 1895 1896 ep = &pci->ep; 1897 ep->ops = &pcie_ep_ops; 1898 1899 ep->page_size = SZ_64K; 1900 1901 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); 1902 if (ret < 0) { 1903 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n", 1904 ret); 1905 return ret; 1906 } 1907 1908 ret = gpiod_to_irq(pcie->pex_rst_gpiod); 1909 if (ret < 0) { 1910 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret); 1911 return ret; 1912 } 1913 pcie->pex_rst_irq = (unsigned int)ret; 1914 1915 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq", 1916 pcie->cid); 1917 if (!name) { 1918 dev_err(dev, "Failed to create PERST IRQ string\n"); 1919 return -ENOMEM; 1920 } 1921 1922 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); 1923 1924 pcie->ep_state = EP_STATE_DISABLED; 1925 1926 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, 1927 tegra_pcie_ep_pex_rst_irq, 1928 IRQF_TRIGGER_RISING | 1929 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1930 name, (void *)pcie); 1931 if (ret < 0) { 1932 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); 1933 return ret; 1934 } 1935 1936 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work", 1937 pcie->cid); 1938 if (!name) { 1939 dev_err(dev, "Failed to create PCIe EP work thread string\n"); 1940 return -ENOMEM; 1941 } 1942 1943 pm_runtime_enable(dev); 1944 1945 ret = dw_pcie_ep_init(ep); 1946 if (ret) { 1947 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n", 1948 ret); 1949 return ret; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int tegra_pcie_dw_probe(struct platform_device *pdev) 1956 { 1957 const struct tegra_pcie_dw_of_data *data; 1958 struct device *dev = &pdev->dev; 1959 struct resource *atu_dma_res; 1960 struct tegra_pcie_dw *pcie; 1961 struct pcie_port *pp; 1962 struct dw_pcie *pci; 1963 struct phy **phys; 1964 char *name; 1965 int ret; 1966 u32 i; 1967 1968 data = of_device_get_match_data(dev); 1969 1970 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1971 if (!pcie) 1972 return -ENOMEM; 1973 1974 pci = &pcie->pci; 1975 pci->dev = &pdev->dev; 1976 pci->ops = &tegra_dw_pcie_ops; 1977 pci->n_fts[0] = N_FTS_VAL; 1978 pci->n_fts[1] = FTS_VAL; 1979 1980 pp = &pci->pp; 1981 pp->num_vectors = MAX_MSI_IRQS; 1982 pcie->dev = &pdev->dev; 1983 pcie->mode = (enum dw_pcie_device_mode)data->mode; 1984 1985 ret = tegra_pcie_dw_parse_dt(pcie); 1986 if (ret < 0) { 1987 const char *level = KERN_ERR; 1988 1989 if (ret == -EPROBE_DEFER) 1990 level = KERN_DEBUG; 1991 1992 dev_printk(level, dev, 1993 dev_fmt("Failed to parse device tree: %d\n"), 1994 ret); 1995 return ret; 1996 } 1997 1998 ret = tegra_pcie_get_slot_regulators(pcie); 1999 if (ret < 0) { 2000 const char *level = KERN_ERR; 2001 2002 if (ret == -EPROBE_DEFER) 2003 level = KERN_DEBUG; 2004 2005 dev_printk(level, dev, 2006 dev_fmt("Failed to get slot regulators: %d\n"), 2007 ret); 2008 return ret; 2009 } 2010 2011 if (pcie->pex_refclk_sel_gpiod) 2012 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); 2013 2014 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); 2015 if (IS_ERR(pcie->pex_ctl_supply)) { 2016 ret = PTR_ERR(pcie->pex_ctl_supply); 2017 if (ret != -EPROBE_DEFER) 2018 dev_err(dev, "Failed to get regulator: %ld\n", 2019 PTR_ERR(pcie->pex_ctl_supply)); 2020 return ret; 2021 } 2022 2023 pcie->core_clk = devm_clk_get(dev, "core"); 2024 if (IS_ERR(pcie->core_clk)) { 2025 dev_err(dev, "Failed to get core clock: %ld\n", 2026 PTR_ERR(pcie->core_clk)); 2027 return PTR_ERR(pcie->core_clk); 2028 } 2029 2030 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2031 "appl"); 2032 if (!pcie->appl_res) { 2033 dev_err(dev, "Failed to find \"appl\" region\n"); 2034 return -ENODEV; 2035 } 2036 2037 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); 2038 if (IS_ERR(pcie->appl_base)) 2039 return PTR_ERR(pcie->appl_base); 2040 2041 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); 2042 if (IS_ERR(pcie->core_apb_rst)) { 2043 dev_err(dev, "Failed to get APB reset: %ld\n", 2044 PTR_ERR(pcie->core_apb_rst)); 2045 return PTR_ERR(pcie->core_apb_rst); 2046 } 2047 2048 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); 2049 if (!phys) 2050 return -ENOMEM; 2051 2052 for (i = 0; i < pcie->phy_count; i++) { 2053 name = kasprintf(GFP_KERNEL, "p2u-%u", i); 2054 if (!name) { 2055 dev_err(dev, "Failed to create P2U string\n"); 2056 return -ENOMEM; 2057 } 2058 phys[i] = devm_phy_get(dev, name); 2059 kfree(name); 2060 if (IS_ERR(phys[i])) { 2061 ret = PTR_ERR(phys[i]); 2062 if (ret != -EPROBE_DEFER) 2063 dev_err(dev, "Failed to get PHY: %d\n", ret); 2064 return ret; 2065 } 2066 } 2067 2068 pcie->phys = phys; 2069 2070 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2071 "atu_dma"); 2072 if (!atu_dma_res) { 2073 dev_err(dev, "Failed to find \"atu_dma\" region\n"); 2074 return -ENODEV; 2075 } 2076 pcie->atu_dma_res = atu_dma_res; 2077 2078 pci->atu_size = resource_size(atu_dma_res); 2079 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); 2080 if (IS_ERR(pci->atu_base)) 2081 return PTR_ERR(pci->atu_base); 2082 2083 pcie->core_rst = devm_reset_control_get(dev, "core"); 2084 if (IS_ERR(pcie->core_rst)) { 2085 dev_err(dev, "Failed to get core reset: %ld\n", 2086 PTR_ERR(pcie->core_rst)); 2087 return PTR_ERR(pcie->core_rst); 2088 } 2089 2090 pp->irq = platform_get_irq_byname(pdev, "intr"); 2091 if (pp->irq < 0) 2092 return pp->irq; 2093 2094 pcie->bpmp = tegra_bpmp_get(dev); 2095 if (IS_ERR(pcie->bpmp)) 2096 return PTR_ERR(pcie->bpmp); 2097 2098 platform_set_drvdata(pdev, pcie); 2099 2100 switch (pcie->mode) { 2101 case DW_PCIE_RC_TYPE: 2102 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, 2103 IRQF_SHARED, "tegra-pcie-intr", pcie); 2104 if (ret) { 2105 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2106 ret); 2107 goto fail; 2108 } 2109 2110 ret = tegra_pcie_config_rp(pcie); 2111 if (ret && ret != -ENOMEDIUM) 2112 goto fail; 2113 else 2114 return 0; 2115 break; 2116 2117 case DW_PCIE_EP_TYPE: 2118 ret = devm_request_threaded_irq(dev, pp->irq, 2119 tegra_pcie_ep_hard_irq, 2120 tegra_pcie_ep_irq_thread, 2121 IRQF_SHARED | IRQF_ONESHOT, 2122 "tegra-pcie-ep-intr", pcie); 2123 if (ret) { 2124 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, 2125 ret); 2126 goto fail; 2127 } 2128 2129 ret = tegra_pcie_config_ep(pcie, pdev); 2130 if (ret < 0) 2131 goto fail; 2132 break; 2133 2134 default: 2135 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); 2136 } 2137 2138 fail: 2139 tegra_bpmp_put(pcie->bpmp); 2140 return ret; 2141 } 2142 2143 static int tegra_pcie_dw_remove(struct platform_device *pdev) 2144 { 2145 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2146 2147 if (!pcie->link_state) 2148 return 0; 2149 2150 debugfs_remove_recursive(pcie->debugfs); 2151 tegra_pcie_deinit_controller(pcie); 2152 pm_runtime_put_sync(pcie->dev); 2153 pm_runtime_disable(pcie->dev); 2154 tegra_bpmp_put(pcie->bpmp); 2155 if (pcie->pex_refclk_sel_gpiod) 2156 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); 2157 2158 return 0; 2159 } 2160 2161 static int tegra_pcie_dw_suspend_late(struct device *dev) 2162 { 2163 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2164 u32 val; 2165 2166 if (!pcie->link_state) 2167 return 0; 2168 2169 /* Enable HW_HOT_RST mode */ 2170 val = appl_readl(pcie, APPL_CTRL); 2171 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2172 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2173 val |= APPL_CTRL_HW_HOT_RST_EN; 2174 appl_writel(pcie, val, APPL_CTRL); 2175 2176 return 0; 2177 } 2178 2179 static int tegra_pcie_dw_suspend_noirq(struct device *dev) 2180 { 2181 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2182 2183 if (!pcie->link_state) 2184 return 0; 2185 2186 /* Save MSI interrupt vector */ 2187 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, 2188 PORT_LOGIC_MSI_CTRL_INT_0_EN); 2189 tegra_pcie_downstream_dev_to_D0(pcie); 2190 tegra_pcie_dw_pme_turnoff(pcie); 2191 2192 return __deinit_controller(pcie); 2193 } 2194 2195 static int tegra_pcie_dw_resume_noirq(struct device *dev) 2196 { 2197 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2198 int ret; 2199 2200 if (!pcie->link_state) 2201 return 0; 2202 2203 ret = tegra_pcie_config_controller(pcie, true); 2204 if (ret < 0) 2205 return ret; 2206 2207 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); 2208 if (ret < 0) { 2209 dev_err(dev, "Failed to init host: %d\n", ret); 2210 goto fail_host_init; 2211 } 2212 2213 /* Restore MSI interrupt vector */ 2214 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, 2215 pcie->msi_ctrl_int); 2216 2217 return 0; 2218 2219 fail_host_init: 2220 return __deinit_controller(pcie); 2221 } 2222 2223 static int tegra_pcie_dw_resume_early(struct device *dev) 2224 { 2225 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); 2226 u32 val; 2227 2228 if (!pcie->link_state) 2229 return 0; 2230 2231 /* Disable HW_HOT_RST mode */ 2232 val = appl_readl(pcie, APPL_CTRL); 2233 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << 2234 APPL_CTRL_HW_HOT_RST_MODE_SHIFT); 2235 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << 2236 APPL_CTRL_HW_HOT_RST_MODE_SHIFT; 2237 val &= ~APPL_CTRL_HW_HOT_RST_EN; 2238 appl_writel(pcie, val, APPL_CTRL); 2239 2240 return 0; 2241 } 2242 2243 static void tegra_pcie_dw_shutdown(struct platform_device *pdev) 2244 { 2245 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); 2246 2247 if (!pcie->link_state) 2248 return; 2249 2250 debugfs_remove_recursive(pcie->debugfs); 2251 tegra_pcie_downstream_dev_to_D0(pcie); 2252 2253 disable_irq(pcie->pci.pp.irq); 2254 if (IS_ENABLED(CONFIG_PCI_MSI)) 2255 disable_irq(pcie->pci.pp.msi_irq); 2256 2257 tegra_pcie_dw_pme_turnoff(pcie); 2258 __deinit_controller(pcie); 2259 } 2260 2261 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { 2262 .mode = DW_PCIE_RC_TYPE, 2263 }; 2264 2265 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = { 2266 .mode = DW_PCIE_EP_TYPE, 2267 }; 2268 2269 static const struct of_device_id tegra_pcie_dw_of_match[] = { 2270 { 2271 .compatible = "nvidia,tegra194-pcie", 2272 .data = &tegra_pcie_dw_rc_of_data, 2273 }, 2274 { 2275 .compatible = "nvidia,tegra194-pcie-ep", 2276 .data = &tegra_pcie_dw_ep_of_data, 2277 }, 2278 {}, 2279 }; 2280 2281 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = { 2282 .suspend_late = tegra_pcie_dw_suspend_late, 2283 .suspend_noirq = tegra_pcie_dw_suspend_noirq, 2284 .resume_noirq = tegra_pcie_dw_resume_noirq, 2285 .resume_early = tegra_pcie_dw_resume_early, 2286 }; 2287 2288 static struct platform_driver tegra_pcie_dw_driver = { 2289 .probe = tegra_pcie_dw_probe, 2290 .remove = tegra_pcie_dw_remove, 2291 .shutdown = tegra_pcie_dw_shutdown, 2292 .driver = { 2293 .name = "tegra194-pcie", 2294 .pm = &tegra_pcie_dw_pm_ops, 2295 .of_match_table = tegra_pcie_dw_of_match, 2296 }, 2297 }; 2298 module_platform_driver(tegra_pcie_dw_driver); 2299 2300 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); 2301 2302 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 2303 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); 2304 MODULE_LICENSE("GPL v2"); 2305