16e0832faSShawn Lin // SPDX-License-Identifier: GPL-2.0 26e0832faSShawn Lin /* 36e0832faSShawn Lin * Qualcomm PCIe root complex driver 46e0832faSShawn Lin * 56e0832faSShawn Lin * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 66e0832faSShawn Lin * Copyright 2015 Linaro Limited. 76e0832faSShawn Lin * 86e0832faSShawn Lin * Author: Stanimir Varbanov <svarbanov@mm-sol.com> 96e0832faSShawn Lin */ 106e0832faSShawn Lin 116e0832faSShawn Lin #include <linux/clk.h> 124c939882SManivannan Sadhasivam #include <linux/crc8.h> 1305f46464SManivannan Sadhasivam #include <linux/debugfs.h> 146e0832faSShawn Lin #include <linux/delay.h> 156e0832faSShawn Lin #include <linux/gpio/consumer.h> 16c4860af8SJohan Hovold #include <linux/interconnect.h> 176e0832faSShawn Lin #include <linux/interrupt.h> 186e0832faSShawn Lin #include <linux/io.h> 196e0832faSShawn Lin #include <linux/iopoll.h> 206e0832faSShawn Lin #include <linux/kernel.h> 216e0832faSShawn Lin #include <linux/init.h> 22*c925cfafSRob Herring #include <linux/of.h> 236e0832faSShawn Lin #include <linux/of_gpio.h> 246e0832faSShawn Lin #include <linux/pci.h> 256e0832faSShawn Lin #include <linux/pm_runtime.h> 266e0832faSShawn Lin #include <linux/platform_device.h> 27f90747d1SDmitry Baryshkov #include <linux/phy/pcie.h> 286e0832faSShawn Lin #include <linux/phy/phy.h> 296e0832faSShawn Lin #include <linux/regulator/consumer.h> 306e0832faSShawn Lin #include <linux/reset.h> 316e0832faSShawn Lin #include <linux/slab.h> 326e0832faSShawn Lin #include <linux/types.h> 336e0832faSShawn Lin 3451ed2c2bSSham Muthayyan #include "../../pci.h" 356e0832faSShawn Lin #include "pcie-designware.h" 366e0832faSShawn Lin 37769e49d8SManivannan Sadhasivam /* PARF registers */ 3839171b33SManivannan Sadhasivam #define PARF_SYS_CTRL 0x00 39769e49d8SManivannan Sadhasivam #define PARF_PM_CTRL 0x20 40769e49d8SManivannan Sadhasivam #define PARF_PCS_DEEMPH 0x34 41769e49d8SManivannan Sadhasivam #define PARF_PCS_SWING 0x38 42769e49d8SManivannan Sadhasivam #define PARF_PHY_CTRL 0x40 4394ebd232SManivannan Sadhasivam #define PARF_PHY_REFCLK 0x4c 44769e49d8SManivannan Sadhasivam #define PARF_CONFIG_BITS 0x50 45769e49d8SManivannan Sadhasivam #define PARF_DBI_BASE_ADDR 0x168 4694ebd232SManivannan Sadhasivam #define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ 47769e49d8SManivannan Sadhasivam #define PARF_MHI_CLOCK_RESET_CTRL 0x174 48769e49d8SManivannan Sadhasivam #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 4994ebd232SManivannan Sadhasivam #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 5094ebd232SManivannan Sadhasivam #define PARF_Q2A_FLUSH 0x1ac 5194ebd232SManivannan Sadhasivam #define PARF_LTSSM 0x1b0 52769e49d8SManivannan Sadhasivam #define PARF_SID_OFFSET 0x234 5394ebd232SManivannan Sadhasivam #define PARF_BDF_TRANSLATE_CFG 0x24c 54769e49d8SManivannan Sadhasivam #define PARF_SLV_ADDR_SPACE_SIZE 0x358 55769e49d8SManivannan Sadhasivam #define PARF_DEVICE_TYPE 0x1000 56769e49d8SManivannan Sadhasivam #define PARF_BDF_TO_SID_TABLE_N 0x2000 57769e49d8SManivannan Sadhasivam 58769e49d8SManivannan Sadhasivam /* ELBI registers */ 59769e49d8SManivannan Sadhasivam #define ELBI_SYS_CTRL 0x04 60769e49d8SManivannan Sadhasivam 61769e49d8SManivannan Sadhasivam /* DBI registers */ 62769e49d8SManivannan Sadhasivam #define AXI_MSTR_RESP_COMP_CTRL0 0x818 63769e49d8SManivannan Sadhasivam #define AXI_MSTR_RESP_COMP_CTRL1 0x81c 64769e49d8SManivannan Sadhasivam 6505f46464SManivannan Sadhasivam /* MHI registers */ 6605f46464SManivannan Sadhasivam #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 6705f46464SManivannan Sadhasivam #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 6805f46464SManivannan Sadhasivam #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 6905f46464SManivannan Sadhasivam #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 7005f46464SManivannan Sadhasivam #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 7105f46464SManivannan Sadhasivam 72769e49d8SManivannan Sadhasivam /* PARF_SYS_CTRL register fields */ 7317804668SManivannan Sadhasivam #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 746e0832faSShawn Lin #define MST_WAKEUP_EN BIT(13) 756e0832faSShawn Lin #define SLV_WAKEUP_EN BIT(12) 766e0832faSShawn Lin #define MSTR_ACLK_CGC_DIS BIT(10) 776e0832faSShawn Lin #define SLV_ACLK_CGC_DIS BIT(9) 786e0832faSShawn Lin #define CORE_CLK_CGC_DIS BIT(6) 796e0832faSShawn Lin #define AUX_PWR_DET BIT(4) 806e0832faSShawn Lin #define L23_CLK_RMV_DIS BIT(2) 816e0832faSShawn Lin #define L1_CLK_RMV_DIS BIT(1) 826e0832faSShawn Lin 83769e49d8SManivannan Sadhasivam /* PARF_PM_CTRL register fields */ 845147ba8aSKrishna chaitanya chundru #define REQ_NOT_ENTR_L1 BIT(5) 855147ba8aSKrishna chaitanya chundru 86769e49d8SManivannan Sadhasivam /* PARF_PCS_DEEMPH register fields */ 8757eddec8SManivannan Sadhasivam #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) 8857eddec8SManivannan Sadhasivam #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) 8957eddec8SManivannan Sadhasivam #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) 90769e49d8SManivannan Sadhasivam 91769e49d8SManivannan Sadhasivam /* PARF_PCS_SWING register fields */ 9257eddec8SManivannan Sadhasivam #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) 9357eddec8SManivannan Sadhasivam #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) 94769e49d8SManivannan Sadhasivam 95769e49d8SManivannan Sadhasivam /* PARF_PHY_CTRL register fields */ 96de3c4bf6SAnsuel Smith #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) 9757eddec8SManivannan Sadhasivam #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) 9817804668SManivannan Sadhasivam #define PHY_TEST_PWR_DOWN BIT(0) 99de3c4bf6SAnsuel Smith 100769e49d8SManivannan Sadhasivam /* PARF_PHY_REFCLK register fields */ 101de3c4bf6SAnsuel Smith #define PHY_REFCLK_SSP_EN BIT(16) 102de3c4bf6SAnsuel Smith #define PHY_REFCLK_USE_PAD BIT(12) 103de3c4bf6SAnsuel Smith 104769e49d8SManivannan Sadhasivam /* PARF_CONFIG_BITS register fields */ 10557eddec8SManivannan Sadhasivam #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) 106769e49d8SManivannan Sadhasivam 107769e49d8SManivannan Sadhasivam /* PARF_SLV_ADDR_SPACE_SIZE register value */ 108769e49d8SManivannan Sadhasivam #define SLV_ADDR_SPACE_SZ 0x10000000 109769e49d8SManivannan Sadhasivam 110769e49d8SManivannan Sadhasivam /* PARF_MHI_CLOCK_RESET_CTRL register fields */ 1110cf7c2efSSelvam Sathappan Periakaruppan #define AHB_CLK_EN BIT(0) 1120cf7c2efSSelvam Sathappan Periakaruppan #define MSTR_AXI_CLK_EN BIT(1) 1130cf7c2efSSelvam Sathappan Periakaruppan #define BYPASS BIT(4) 1140cf7c2efSSelvam Sathappan Periakaruppan 11517804668SManivannan Sadhasivam /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 11617804668SManivannan Sadhasivam #define EN BIT(31) 11717804668SManivannan Sadhasivam 11817804668SManivannan Sadhasivam /* PARF_LTSSM register fields */ 11917804668SManivannan Sadhasivam #define LTSSM_EN BIT(8) 12017804668SManivannan Sadhasivam 121769e49d8SManivannan Sadhasivam /* PARF_DEVICE_TYPE register fields */ 122769e49d8SManivannan Sadhasivam #define DEVICE_TYPE_RC 0x4 1236e0832faSShawn Lin 124769e49d8SManivannan Sadhasivam /* ELBI_SYS_CTRL register fields */ 12539171b33SManivannan Sadhasivam #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) 1266e0832faSShawn Lin 127769e49d8SManivannan Sadhasivam /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ 1286e0832faSShawn Lin #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 1296e0832faSShawn Lin #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 130769e49d8SManivannan Sadhasivam 131769e49d8SManivannan Sadhasivam /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ 1326e0832faSShawn Lin #define CFG_BRIDGE_SB_INIT BIT(0) 1336e0832faSShawn Lin 134769e49d8SManivannan Sadhasivam /* PCI_EXP_SLTCAP register fields */ 135769e49d8SManivannan Sadhasivam #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) 136769e49d8SManivannan Sadhasivam #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) 1379a765805SBaruch Siach #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ 1389a765805SBaruch Siach PCI_EXP_SLTCAP_PCP | \ 1399a765805SBaruch Siach PCI_EXP_SLTCAP_MRLSP | \ 1409a765805SBaruch Siach PCI_EXP_SLTCAP_AIP | \ 1419a765805SBaruch Siach PCI_EXP_SLTCAP_PIP | \ 1429a765805SBaruch Siach PCI_EXP_SLTCAP_HPS | \ 1439a765805SBaruch Siach PCI_EXP_SLTCAP_EIP | \ 1449a765805SBaruch Siach PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ 1459a765805SBaruch Siach PCIE_CAP_SLOT_POWER_LIMIT_SCALE) 1466e0832faSShawn Lin 1476e0832faSShawn Lin #define PERST_DELAY_US 1000 148ed8cc3b1SBjorn Andersson 1494c939882SManivannan Sadhasivam #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 1504c939882SManivannan Sadhasivam 1515d4ffe5eSManivannan Sadhasivam #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 1526e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 { 1535d4ffe5eSManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; 1546e0832faSShawn Lin struct reset_control *core; 1556e0832faSShawn Lin struct regulator *vdda; 1566e0832faSShawn Lin }; 1576e0832faSShawn Lin 158383215ddSManivannan Sadhasivam #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 159383215ddSManivannan Sadhasivam #define QCOM_PCIE_2_1_0_MAX_RESETS 6 160383215ddSManivannan Sadhasivam #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 161383215ddSManivannan Sadhasivam struct qcom_pcie_resources_2_1_0 { 162383215ddSManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; 163383215ddSManivannan Sadhasivam struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; 164383215ddSManivannan Sadhasivam int num_resets; 165383215ddSManivannan Sadhasivam struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; 166383215ddSManivannan Sadhasivam }; 167383215ddSManivannan Sadhasivam 1685329bcc4SManivannan Sadhasivam #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 1696e0832faSShawn Lin #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 1706e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 { 1715329bcc4SManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; 1726e0832faSShawn Lin struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; 1736e0832faSShawn Lin }; 1746e0832faSShawn Lin 175b699ed9bSManivannan Sadhasivam #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 176157feccaSManivannan Sadhasivam #define QCOM_PCIE_2_3_3_MAX_RESETS 7 177b699ed9bSManivannan Sadhasivam struct qcom_pcie_resources_2_3_3 { 178b699ed9bSManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; 179157feccaSManivannan Sadhasivam struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; 180b699ed9bSManivannan Sadhasivam }; 181b699ed9bSManivannan Sadhasivam 18267021ae0SBjorn Andersson #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 183fb0eacb2SManivannan Sadhasivam #define QCOM_PCIE_2_4_0_MAX_RESETS 12 1846e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 { 1855aa18097SBjorn Andersson struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; 1865aa18097SBjorn Andersson int num_clks; 187fb0eacb2SManivannan Sadhasivam struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; 188fb0eacb2SManivannan Sadhasivam int num_resets; 1896e0832faSShawn Lin }; 1906e0832faSShawn Lin 1916276a403SAbel Vesa #define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 192656a0882SManivannan Sadhasivam #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 193ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 { 194656a0882SManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; 1957081556fSDmitry Baryshkov int num_clks; 196656a0882SManivannan Sadhasivam struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; 1976276a403SAbel Vesa struct reset_control *rst; 198ed8cc3b1SBjorn Andersson }; 199ed8cc3b1SBjorn Andersson 200656a0882SManivannan Sadhasivam #define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 2010cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 { 202656a0882SManivannan Sadhasivam struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; 2030cf7c2efSSelvam Sathappan Periakaruppan struct reset_control *rst; 2046e0832faSShawn Lin }; 2056e0832faSShawn Lin 2066e0832faSShawn Lin union qcom_pcie_resources { 2076e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 v1_0_0; 2086e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 v2_1_0; 2096e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 v2_3_2; 2106e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 v2_3_3; 2116e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 v2_4_0; 212ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 v2_7_0; 2130cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 v2_9_0; 2146e0832faSShawn Lin }; 2156e0832faSShawn Lin 2166e0832faSShawn Lin struct qcom_pcie; 2176e0832faSShawn Lin 2186e0832faSShawn Lin struct qcom_pcie_ops { 2196e0832faSShawn Lin int (*get_resources)(struct qcom_pcie *pcie); 2206e0832faSShawn Lin int (*init)(struct qcom_pcie *pcie); 2216e0832faSShawn Lin int (*post_init)(struct qcom_pcie *pcie); 2226e0832faSShawn Lin void (*deinit)(struct qcom_pcie *pcie); 2236e0832faSShawn Lin void (*ltssm_enable)(struct qcom_pcie *pcie); 2244c939882SManivannan Sadhasivam int (*config_sid)(struct qcom_pcie *pcie); 2256e0832faSShawn Lin }; 2266e0832faSShawn Lin 227b89ff410SPrasad Malisetty struct qcom_pcie_cfg { 228b89ff410SPrasad Malisetty const struct qcom_pcie_ops *ops; 229b89ff410SPrasad Malisetty }; 230b89ff410SPrasad Malisetty 2316e0832faSShawn Lin struct qcom_pcie { 2326e0832faSShawn Lin struct dw_pcie *pci; 2336e0832faSShawn Lin void __iomem *parf; /* DT parf */ 2346e0832faSShawn Lin void __iomem *elbi; /* DT elbi */ 23505f46464SManivannan Sadhasivam void __iomem *mhi; 2366e0832faSShawn Lin union qcom_pcie_resources res; 2376e0832faSShawn Lin struct phy *phy; 2386e0832faSShawn Lin struct gpio_desc *reset; 239c4860af8SJohan Hovold struct icc_path *icc_mem; 240f94c35e0SDmitry Baryshkov const struct qcom_pcie_cfg *cfg; 24105f46464SManivannan Sadhasivam struct dentry *debugfs; 242ad9b9b6eSManivannan Sadhasivam bool suspended; 2436e0832faSShawn Lin }; 2446e0832faSShawn Lin 2456e0832faSShawn Lin #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) 2466e0832faSShawn Lin 2476e0832faSShawn Lin static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 2486e0832faSShawn Lin { 2496e0832faSShawn Lin gpiod_set_value_cansleep(pcie->reset, 1); 2506e0832faSShawn Lin usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 2516e0832faSShawn Lin } 2526e0832faSShawn Lin 2536e0832faSShawn Lin static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) 2546e0832faSShawn Lin { 25564adde31SNiklas Cassel /* Ensure that PERST has been asserted for at least 100 ms */ 25664adde31SNiklas Cassel msleep(100); 2576e0832faSShawn Lin gpiod_set_value_cansleep(pcie->reset, 0); 2586e0832faSShawn Lin usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 2596e0832faSShawn Lin } 2606e0832faSShawn Lin 261886a9c13SRob Herring static int qcom_pcie_start_link(struct dw_pcie *pci) 2626e0832faSShawn Lin { 263886a9c13SRob Herring struct qcom_pcie *pcie = to_qcom_pcie(pci); 2646e0832faSShawn Lin 2656e0832faSShawn Lin /* Enable Link Training state machine */ 266f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->ltssm_enable) 267f94c35e0SDmitry Baryshkov pcie->cfg->ops->ltssm_enable(pcie); 2686e0832faSShawn Lin 269886a9c13SRob Herring return 0; 2706e0832faSShawn Lin } 2716e0832faSShawn Lin 272a54db86dSManivannan Sadhasivam static void qcom_pcie_clear_hpc(struct dw_pcie *pci) 273a54db86dSManivannan Sadhasivam { 274a54db86dSManivannan Sadhasivam u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 275a54db86dSManivannan Sadhasivam u32 val; 276a54db86dSManivannan Sadhasivam 277a54db86dSManivannan Sadhasivam dw_pcie_dbi_ro_wr_en(pci); 278a54db86dSManivannan Sadhasivam 279a54db86dSManivannan Sadhasivam val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); 280a54db86dSManivannan Sadhasivam val &= ~PCI_EXP_SLTCAP_HPC; 281a54db86dSManivannan Sadhasivam writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); 282a54db86dSManivannan Sadhasivam 283a54db86dSManivannan Sadhasivam dw_pcie_dbi_ro_wr_dis(pci); 284a54db86dSManivannan Sadhasivam } 285a54db86dSManivannan Sadhasivam 2866e0832faSShawn Lin static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 2876e0832faSShawn Lin { 2886e0832faSShawn Lin u32 val; 2896e0832faSShawn Lin 2906e0832faSShawn Lin /* enable link training */ 29139171b33SManivannan Sadhasivam val = readl(pcie->elbi + ELBI_SYS_CTRL); 29239171b33SManivannan Sadhasivam val |= ELBI_SYS_CTRL_LT_ENABLE; 29339171b33SManivannan Sadhasivam writel(val, pcie->elbi + ELBI_SYS_CTRL); 2946e0832faSShawn Lin } 2956e0832faSShawn Lin 2966e0832faSShawn Lin static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 2976e0832faSShawn Lin { 2986e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 2996e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 3006e0832faSShawn Lin struct device *dev = pci->dev; 301383215ddSManivannan Sadhasivam bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); 3026e0832faSShawn Lin int ret; 3036e0832faSShawn Lin 3046e0832faSShawn Lin res->supplies[0].supply = "vdda"; 3056e0832faSShawn Lin res->supplies[1].supply = "vdda_phy"; 3066e0832faSShawn Lin res->supplies[2].supply = "vdda_refclk"; 3076e0832faSShawn Lin ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 3086e0832faSShawn Lin res->supplies); 3096e0832faSShawn Lin if (ret) 3106e0832faSShawn Lin return ret; 3116e0832faSShawn Lin 3126a114526SAnsuel Smith res->clks[0].id = "iface"; 3136a114526SAnsuel Smith res->clks[1].id = "core"; 3146a114526SAnsuel Smith res->clks[2].id = "phy"; 3156a114526SAnsuel Smith res->clks[3].id = "aux"; 3166a114526SAnsuel Smith res->clks[4].id = "ref"; 3176e0832faSShawn Lin 3186a114526SAnsuel Smith /* iface, core, phy are required */ 3196a114526SAnsuel Smith ret = devm_clk_bulk_get(dev, 3, res->clks); 3206a114526SAnsuel Smith if (ret < 0) 3216a114526SAnsuel Smith return ret; 3226e0832faSShawn Lin 3236a114526SAnsuel Smith /* aux, ref are optional */ 3246a114526SAnsuel Smith ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); 3256a114526SAnsuel Smith if (ret < 0) 3266a114526SAnsuel Smith return ret; 3278b6f0330SAnsuel Smith 328383215ddSManivannan Sadhasivam res->resets[0].id = "pci"; 329383215ddSManivannan Sadhasivam res->resets[1].id = "axi"; 330383215ddSManivannan Sadhasivam res->resets[2].id = "ahb"; 331383215ddSManivannan Sadhasivam res->resets[3].id = "por"; 332383215ddSManivannan Sadhasivam res->resets[4].id = "phy"; 333383215ddSManivannan Sadhasivam res->resets[5].id = "ext"; 3346e0832faSShawn Lin 335383215ddSManivannan Sadhasivam /* ext is optional on APQ8016 */ 336383215ddSManivannan Sadhasivam res->num_resets = is_apq ? 5 : 6; 337383215ddSManivannan Sadhasivam ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 338383215ddSManivannan Sadhasivam if (ret < 0) 339383215ddSManivannan Sadhasivam return ret; 3406e0832faSShawn Lin 341383215ddSManivannan Sadhasivam return 0; 3426e0832faSShawn Lin } 3436e0832faSShawn Lin 3446e0832faSShawn Lin static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 3456e0832faSShawn Lin { 3466e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 3476e0832faSShawn Lin 3486a114526SAnsuel Smith clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 349383215ddSManivannan Sadhasivam reset_control_bulk_assert(res->num_resets, res->resets); 350d3d4d028SAnsuel Smith 35139171b33SManivannan Sadhasivam writel(1, pcie->parf + PARF_PHY_CTRL); 352d3d4d028SAnsuel Smith 3536e0832faSShawn Lin regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 3546e0832faSShawn Lin } 3556e0832faSShawn Lin 3566e0832faSShawn Lin static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 3576e0832faSShawn Lin { 3586e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 3596e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 3606e0832faSShawn Lin struct device *dev = pci->dev; 3616e0832faSShawn Lin int ret; 3626e0832faSShawn Lin 363d3d4d028SAnsuel Smith /* reset the PCIe interface as uboot can leave it undefined state */ 364383215ddSManivannan Sadhasivam ret = reset_control_bulk_assert(res->num_resets, res->resets); 365383215ddSManivannan Sadhasivam if (ret < 0) { 366383215ddSManivannan Sadhasivam dev_err(dev, "cannot assert resets\n"); 367383215ddSManivannan Sadhasivam return ret; 368383215ddSManivannan Sadhasivam } 369d3d4d028SAnsuel Smith 3706e0832faSShawn Lin ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 3716e0832faSShawn Lin if (ret < 0) { 3726e0832faSShawn Lin dev_err(dev, "cannot enable regulators\n"); 3736e0832faSShawn Lin return ret; 3746e0832faSShawn Lin } 3756e0832faSShawn Lin 376383215ddSManivannan Sadhasivam ret = reset_control_bulk_deassert(res->num_resets, res->resets); 377383215ddSManivannan Sadhasivam if (ret < 0) { 378383215ddSManivannan Sadhasivam dev_err(dev, "cannot deassert resets\n"); 379383215ddSManivannan Sadhasivam regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 380383215ddSManivannan Sadhasivam return ret; 3816a114526SAnsuel Smith } 3826a114526SAnsuel Smith 38336d9018dSRobert Marko return 0; 38436d9018dSRobert Marko } 38536d9018dSRobert Marko 38636d9018dSRobert Marko static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) 38736d9018dSRobert Marko { 38836d9018dSRobert Marko struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 38936d9018dSRobert Marko struct dw_pcie *pci = pcie->pci; 39036d9018dSRobert Marko struct device *dev = pci->dev; 39136d9018dSRobert Marko struct device_node *node = dev->of_node; 39236d9018dSRobert Marko u32 val; 39336d9018dSRobert Marko int ret; 3946a114526SAnsuel Smith 3956e0832faSShawn Lin /* enable PCIe clocks and resets */ 39639171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 39717804668SManivannan Sadhasivam val &= ~PHY_TEST_PWR_DOWN; 39839171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 3996e0832faSShawn Lin 40038f897aeSChristian Marangi ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 40138f897aeSChristian Marangi if (ret) 40236d9018dSRobert Marko return ret; 40338f897aeSChristian Marangi 4048df093feSAnsuel Smith if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || 4058df093feSAnsuel Smith of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { 4065149901eSAnsuel Smith writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | 4075149901eSAnsuel Smith PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | 4085149901eSAnsuel Smith PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), 40939171b33SManivannan Sadhasivam pcie->parf + PARF_PCS_DEEMPH); 4105149901eSAnsuel Smith writel(PCS_SWING_TX_SWING_FULL(120) | 4115149901eSAnsuel Smith PCS_SWING_TX_SWING_LOW(120), 41239171b33SManivannan Sadhasivam pcie->parf + PARF_PCS_SWING); 41339171b33SManivannan Sadhasivam writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); 4145149901eSAnsuel Smith } 4155149901eSAnsuel Smith 416de3c4bf6SAnsuel Smith if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { 417de3c4bf6SAnsuel Smith /* set TX termination offset */ 41839171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 419de3c4bf6SAnsuel Smith val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; 420de3c4bf6SAnsuel Smith val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); 42139171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 422de3c4bf6SAnsuel Smith } 423de3c4bf6SAnsuel Smith 4246e0832faSShawn Lin /* enable external reference clock */ 42539171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_REFCLK); 4262cfef197SAnsuel Smith /* USE_PAD is required only for ipq806x */ 4272cfef197SAnsuel Smith if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) 428de3c4bf6SAnsuel Smith val &= ~PHY_REFCLK_USE_PAD; 429de3c4bf6SAnsuel Smith val |= PHY_REFCLK_SSP_EN; 43039171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_REFCLK); 4316e0832faSShawn Lin 4326e0832faSShawn Lin /* wait for clock acquisition */ 4336e0832faSShawn Lin usleep_range(1000, 1500); 4346e0832faSShawn Lin 4356e0832faSShawn Lin /* Set the Max TLP size to 2K, instead of using default of 4K */ 4366e0832faSShawn Lin writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, 43739171b33SManivannan Sadhasivam pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); 4386e0832faSShawn Lin writel(CFG_BRIDGE_SB_INIT, 43939171b33SManivannan Sadhasivam pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); 4406e0832faSShawn Lin 4411fdecc5bSManivannan Sadhasivam qcom_pcie_clear_hpc(pcie->pci); 4421fdecc5bSManivannan Sadhasivam 4436e0832faSShawn Lin return 0; 4446e0832faSShawn Lin } 4456e0832faSShawn Lin 4466e0832faSShawn Lin static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) 4476e0832faSShawn Lin { 4486e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 4496e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 4506e0832faSShawn Lin struct device *dev = pci->dev; 4515d4ffe5eSManivannan Sadhasivam int ret; 4526e0832faSShawn Lin 4536e0832faSShawn Lin res->vdda = devm_regulator_get(dev, "vdda"); 4546e0832faSShawn Lin if (IS_ERR(res->vdda)) 4556e0832faSShawn Lin return PTR_ERR(res->vdda); 4566e0832faSShawn Lin 4575d4ffe5eSManivannan Sadhasivam res->clks[0].id = "iface"; 4585d4ffe5eSManivannan Sadhasivam res->clks[1].id = "aux"; 4595d4ffe5eSManivannan Sadhasivam res->clks[2].id = "master_bus"; 4605d4ffe5eSManivannan Sadhasivam res->clks[3].id = "slave_bus"; 4616e0832faSShawn Lin 4625d4ffe5eSManivannan Sadhasivam ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 4635d4ffe5eSManivannan Sadhasivam if (ret < 0) 4645d4ffe5eSManivannan Sadhasivam return ret; 4656e0832faSShawn Lin 4666e0832faSShawn Lin res->core = devm_reset_control_get_exclusive(dev, "core"); 4676e0832faSShawn Lin return PTR_ERR_OR_ZERO(res->core); 4686e0832faSShawn Lin } 4696e0832faSShawn Lin 4706e0832faSShawn Lin static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) 4716e0832faSShawn Lin { 4726e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 4736e0832faSShawn Lin 4746e0832faSShawn Lin reset_control_assert(res->core); 4755d4ffe5eSManivannan Sadhasivam clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 4766e0832faSShawn Lin regulator_disable(res->vdda); 4776e0832faSShawn Lin } 4786e0832faSShawn Lin 4796e0832faSShawn Lin static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) 4806e0832faSShawn Lin { 4816e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 4826e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 4836e0832faSShawn Lin struct device *dev = pci->dev; 4846e0832faSShawn Lin int ret; 4856e0832faSShawn Lin 4866e0832faSShawn Lin ret = reset_control_deassert(res->core); 4876e0832faSShawn Lin if (ret) { 4886e0832faSShawn Lin dev_err(dev, "cannot deassert core reset\n"); 4896e0832faSShawn Lin return ret; 4906e0832faSShawn Lin } 4916e0832faSShawn Lin 4925d4ffe5eSManivannan Sadhasivam ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 4936e0832faSShawn Lin if (ret) { 4945d4ffe5eSManivannan Sadhasivam dev_err(dev, "cannot prepare/enable clocks\n"); 4955d4ffe5eSManivannan Sadhasivam goto err_assert_reset; 4966e0832faSShawn Lin } 4976e0832faSShawn Lin 4986e0832faSShawn Lin ret = regulator_enable(res->vdda); 4996e0832faSShawn Lin if (ret) { 5006e0832faSShawn Lin dev_err(dev, "cannot enable vdda regulator\n"); 5015d4ffe5eSManivannan Sadhasivam goto err_disable_clks; 5026e0832faSShawn Lin } 5036e0832faSShawn Lin 5046e0832faSShawn Lin return 0; 5055d4ffe5eSManivannan Sadhasivam 5065d4ffe5eSManivannan Sadhasivam err_disable_clks: 5075d4ffe5eSManivannan Sadhasivam clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 5085d4ffe5eSManivannan Sadhasivam err_assert_reset: 5096e0832faSShawn Lin reset_control_assert(res->core); 5106e0832faSShawn Lin 5116e0832faSShawn Lin return ret; 5126e0832faSShawn Lin } 5136e0832faSShawn Lin 51436d9018dSRobert Marko static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 51536d9018dSRobert Marko { 51636d9018dSRobert Marko /* change DBI base address */ 51739171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 51836d9018dSRobert Marko 51936d9018dSRobert Marko if (IS_ENABLED(CONFIG_PCI_MSI)) { 52039171b33SManivannan Sadhasivam u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 52136d9018dSRobert Marko 52217804668SManivannan Sadhasivam val |= EN; 52339171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 52436d9018dSRobert Marko } 52536d9018dSRobert Marko 526fa2dc252SManivannan Sadhasivam qcom_pcie_clear_hpc(pcie->pci); 527fa2dc252SManivannan Sadhasivam 52836d9018dSRobert Marko return 0; 52936d9018dSRobert Marko } 53036d9018dSRobert Marko 5316e0832faSShawn Lin static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) 5326e0832faSShawn Lin { 5336e0832faSShawn Lin u32 val; 5346e0832faSShawn Lin 5356e0832faSShawn Lin /* enable link training */ 53639171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_LTSSM); 53717804668SManivannan Sadhasivam val |= LTSSM_EN; 53839171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_LTSSM); 5396e0832faSShawn Lin } 5406e0832faSShawn Lin 5416e0832faSShawn Lin static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 5426e0832faSShawn Lin { 5436e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 5446e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 5456e0832faSShawn Lin struct device *dev = pci->dev; 5466e0832faSShawn Lin int ret; 5476e0832faSShawn Lin 5486e0832faSShawn Lin res->supplies[0].supply = "vdda"; 5496e0832faSShawn Lin res->supplies[1].supply = "vddpe-3v3"; 5506e0832faSShawn Lin ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 5516e0832faSShawn Lin res->supplies); 5526e0832faSShawn Lin if (ret) 5536e0832faSShawn Lin return ret; 5546e0832faSShawn Lin 5555329bcc4SManivannan Sadhasivam res->clks[0].id = "aux"; 5565329bcc4SManivannan Sadhasivam res->clks[1].id = "cfg"; 5575329bcc4SManivannan Sadhasivam res->clks[2].id = "bus_master"; 5585329bcc4SManivannan Sadhasivam res->clks[3].id = "bus_slave"; 5596e0832faSShawn Lin 5605329bcc4SManivannan Sadhasivam ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 5615329bcc4SManivannan Sadhasivam if (ret < 0) 5625329bcc4SManivannan Sadhasivam return ret; 5636e0832faSShawn Lin 564affac98aSDmitry Baryshkov return 0; 5656e0832faSShawn Lin } 5666e0832faSShawn Lin 5676e0832faSShawn Lin static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 5686e0832faSShawn Lin { 5696e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 5706e0832faSShawn Lin 5715329bcc4SManivannan Sadhasivam clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 5726e0832faSShawn Lin regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 5736e0832faSShawn Lin } 5746e0832faSShawn Lin 5756e0832faSShawn Lin static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 5766e0832faSShawn Lin { 5776e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 5786e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 5796e0832faSShawn Lin struct device *dev = pci->dev; 5806e0832faSShawn Lin int ret; 5816e0832faSShawn Lin 5826e0832faSShawn Lin ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 5836e0832faSShawn Lin if (ret < 0) { 5846e0832faSShawn Lin dev_err(dev, "cannot enable regulators\n"); 5856e0832faSShawn Lin return ret; 5866e0832faSShawn Lin } 5876e0832faSShawn Lin 5885329bcc4SManivannan Sadhasivam ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 5896e0832faSShawn Lin if (ret) { 5905329bcc4SManivannan Sadhasivam dev_err(dev, "cannot prepare/enable clocks\n"); 5915329bcc4SManivannan Sadhasivam regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 5925329bcc4SManivannan Sadhasivam return ret; 5936e0832faSShawn Lin } 5946e0832faSShawn Lin 5956e0832faSShawn Lin return 0; 5966e0832faSShawn Lin } 5976e0832faSShawn Lin 5986e0832faSShawn Lin static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 5996e0832faSShawn Lin { 60036d9018dSRobert Marko u32 val; 6016e0832faSShawn Lin 6026e0832faSShawn Lin /* enable PCIe clocks and resets */ 60339171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 60417804668SManivannan Sadhasivam val &= ~PHY_TEST_PWR_DOWN; 60539171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 6066e0832faSShawn Lin 6076e0832faSShawn Lin /* change DBI base address */ 60839171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 6096e0832faSShawn Lin 6106e0832faSShawn Lin /* MAC PHY_POWERDOWN MUX DISABLE */ 61139171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_SYS_CTRL); 61217804668SManivannan Sadhasivam val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 61339171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_SYS_CTRL); 6146e0832faSShawn Lin 61539171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 61617804668SManivannan Sadhasivam val |= BYPASS; 61739171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 6186e0832faSShawn Lin 61939171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 62017804668SManivannan Sadhasivam val |= EN; 62139171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 6226e0832faSShawn Lin 62325966e78SManivannan Sadhasivam qcom_pcie_clear_hpc(pcie->pci); 62425966e78SManivannan Sadhasivam 6256e0832faSShawn Lin return 0; 6266e0832faSShawn Lin } 6276e0832faSShawn Lin 6286e0832faSShawn Lin static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) 6296e0832faSShawn Lin { 6306e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 6316e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 6326e0832faSShawn Lin struct device *dev = pci->dev; 63367021ae0SBjorn Andersson bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); 6345aa18097SBjorn Andersson int ret; 6356e0832faSShawn Lin 6365aa18097SBjorn Andersson res->clks[0].id = "aux"; 6375aa18097SBjorn Andersson res->clks[1].id = "master_bus"; 6385aa18097SBjorn Andersson res->clks[2].id = "slave_bus"; 63967021ae0SBjorn Andersson res->clks[3].id = "iface"; 6406e0832faSShawn Lin 64167021ae0SBjorn Andersson /* qcom,pcie-ipq4019 is defined without "iface" */ 64267021ae0SBjorn Andersson res->num_clks = is_ipq ? 3 : 4; 6436e0832faSShawn Lin 6445aa18097SBjorn Andersson ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); 6455aa18097SBjorn Andersson if (ret < 0) 6465aa18097SBjorn Andersson return ret; 6476e0832faSShawn Lin 648fb0eacb2SManivannan Sadhasivam res->resets[0].id = "axi_m"; 649fb0eacb2SManivannan Sadhasivam res->resets[1].id = "axi_s"; 650fb0eacb2SManivannan Sadhasivam res->resets[2].id = "axi_m_sticky"; 651fb0eacb2SManivannan Sadhasivam res->resets[3].id = "pipe_sticky"; 652fb0eacb2SManivannan Sadhasivam res->resets[4].id = "pwr"; 653fb0eacb2SManivannan Sadhasivam res->resets[5].id = "ahb"; 654fb0eacb2SManivannan Sadhasivam res->resets[6].id = "pipe"; 655fb0eacb2SManivannan Sadhasivam res->resets[7].id = "axi_m_vmid"; 656fb0eacb2SManivannan Sadhasivam res->resets[8].id = "axi_s_xpu"; 657fb0eacb2SManivannan Sadhasivam res->resets[9].id = "parf"; 658fb0eacb2SManivannan Sadhasivam res->resets[10].id = "phy"; 659fb0eacb2SManivannan Sadhasivam res->resets[11].id = "phy_ahb"; 6606e0832faSShawn Lin 661fb0eacb2SManivannan Sadhasivam res->num_resets = is_ipq ? 12 : 6; 6626e0832faSShawn Lin 663fb0eacb2SManivannan Sadhasivam ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 664fb0eacb2SManivannan Sadhasivam if (ret < 0) 665fb0eacb2SManivannan Sadhasivam return ret; 6666e0832faSShawn Lin 6676e0832faSShawn Lin return 0; 6686e0832faSShawn Lin } 6696e0832faSShawn Lin 6706e0832faSShawn Lin static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) 6716e0832faSShawn Lin { 6726e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 6736e0832faSShawn Lin 674fb0eacb2SManivannan Sadhasivam reset_control_bulk_assert(res->num_resets, res->resets); 6755aa18097SBjorn Andersson clk_bulk_disable_unprepare(res->num_clks, res->clks); 6766e0832faSShawn Lin } 6776e0832faSShawn Lin 6786e0832faSShawn Lin static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 6796e0832faSShawn Lin { 6806e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 6816e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 6826e0832faSShawn Lin struct device *dev = pci->dev; 6836e0832faSShawn Lin int ret; 6846e0832faSShawn Lin 685fb0eacb2SManivannan Sadhasivam ret = reset_control_bulk_assert(res->num_resets, res->resets); 686fb0eacb2SManivannan Sadhasivam if (ret < 0) { 687fb0eacb2SManivannan Sadhasivam dev_err(dev, "cannot assert resets\n"); 6886e0832faSShawn Lin return ret; 6896e0832faSShawn Lin } 6906e0832faSShawn Lin 6916e0832faSShawn Lin usleep_range(10000, 12000); 6926e0832faSShawn Lin 693fb0eacb2SManivannan Sadhasivam ret = reset_control_bulk_deassert(res->num_resets, res->resets); 694fb0eacb2SManivannan Sadhasivam if (ret < 0) { 695fb0eacb2SManivannan Sadhasivam dev_err(dev, "cannot deassert resets\n"); 6966e0832faSShawn Lin return ret; 6976e0832faSShawn Lin } 6986e0832faSShawn Lin 6996e0832faSShawn Lin usleep_range(10000, 12000); 7006e0832faSShawn Lin 7015aa18097SBjorn Andersson ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 702fb0eacb2SManivannan Sadhasivam if (ret) { 703fb0eacb2SManivannan Sadhasivam reset_control_bulk_assert(res->num_resets, res->resets); 704fb0eacb2SManivannan Sadhasivam return ret; 705fb0eacb2SManivannan Sadhasivam } 7066e0832faSShawn Lin 70736d9018dSRobert Marko return 0; 70836d9018dSRobert Marko } 70936d9018dSRobert Marko 7106e0832faSShawn Lin static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) 7116e0832faSShawn Lin { 7126e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 7136e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 7146e0832faSShawn Lin struct device *dev = pci->dev; 715b699ed9bSManivannan Sadhasivam int ret; 7166e0832faSShawn Lin 717b699ed9bSManivannan Sadhasivam res->clks[0].id = "iface"; 718b699ed9bSManivannan Sadhasivam res->clks[1].id = "axi_m"; 719b699ed9bSManivannan Sadhasivam res->clks[2].id = "axi_s"; 720b699ed9bSManivannan Sadhasivam res->clks[3].id = "ahb"; 721b699ed9bSManivannan Sadhasivam res->clks[4].id = "aux"; 7226e0832faSShawn Lin 723b699ed9bSManivannan Sadhasivam ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 724b699ed9bSManivannan Sadhasivam if (ret < 0) 725b699ed9bSManivannan Sadhasivam return ret; 7266e0832faSShawn Lin 727157feccaSManivannan Sadhasivam res->rst[0].id = "axi_m"; 728157feccaSManivannan Sadhasivam res->rst[1].id = "axi_s"; 729157feccaSManivannan Sadhasivam res->rst[2].id = "pipe"; 730157feccaSManivannan Sadhasivam res->rst[3].id = "axi_m_sticky"; 731157feccaSManivannan Sadhasivam res->rst[4].id = "sticky"; 732157feccaSManivannan Sadhasivam res->rst[5].id = "ahb"; 733157feccaSManivannan Sadhasivam res->rst[6].id = "sleep"; 734157feccaSManivannan Sadhasivam 735157feccaSManivannan Sadhasivam ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); 736157feccaSManivannan Sadhasivam if (ret < 0) 737157feccaSManivannan Sadhasivam return ret; 7386e0832faSShawn Lin 7396e0832faSShawn Lin return 0; 7406e0832faSShawn Lin } 7416e0832faSShawn Lin 7426e0832faSShawn Lin static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) 7436e0832faSShawn Lin { 7446e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 7456e0832faSShawn Lin 746b699ed9bSManivannan Sadhasivam clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 7476e0832faSShawn Lin } 7486e0832faSShawn Lin 7496e0832faSShawn Lin static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) 7506e0832faSShawn Lin { 7516e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 7526e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 7536e0832faSShawn Lin struct device *dev = pci->dev; 754157feccaSManivannan Sadhasivam int ret; 7556e0832faSShawn Lin 756157feccaSManivannan Sadhasivam ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 757157feccaSManivannan Sadhasivam if (ret < 0) { 758157feccaSManivannan Sadhasivam dev_err(dev, "cannot assert resets\n"); 7596e0832faSShawn Lin return ret; 7606e0832faSShawn Lin } 7616e0832faSShawn Lin 7626e0832faSShawn Lin usleep_range(2000, 2500); 7636e0832faSShawn Lin 764157feccaSManivannan Sadhasivam ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); 765157feccaSManivannan Sadhasivam if (ret < 0) { 766157feccaSManivannan Sadhasivam dev_err(dev, "cannot deassert resets\n"); 7676e0832faSShawn Lin return ret; 7686e0832faSShawn Lin } 7696e0832faSShawn Lin 7706e0832faSShawn Lin /* 7716e0832faSShawn Lin * Don't have a way to see if the reset has completed. 7726e0832faSShawn Lin * Wait for some time. 7736e0832faSShawn Lin */ 7746e0832faSShawn Lin usleep_range(2000, 2500); 7756e0832faSShawn Lin 776b699ed9bSManivannan Sadhasivam ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 7776e0832faSShawn Lin if (ret) { 778b699ed9bSManivannan Sadhasivam dev_err(dev, "cannot prepare/enable clocks\n"); 779b699ed9bSManivannan Sadhasivam goto err_assert_resets; 7806e0832faSShawn Lin } 7816e0832faSShawn Lin 7826e0832faSShawn Lin return 0; 7836e0832faSShawn Lin 784b699ed9bSManivannan Sadhasivam err_assert_resets: 7856e0832faSShawn Lin /* 7866e0832faSShawn Lin * Not checking for failure, will anyway return 7876e0832faSShawn Lin * the original failure in 'ret'. 7886e0832faSShawn Lin */ 789157feccaSManivannan Sadhasivam reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 7906e0832faSShawn Lin 7916e0832faSShawn Lin return ret; 7926e0832faSShawn Lin } 7936e0832faSShawn Lin 794a0e43bb9SRobert Marko static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 795a0e43bb9SRobert Marko { 796a0e43bb9SRobert Marko struct dw_pcie *pci = pcie->pci; 797a0e43bb9SRobert Marko u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 798a0e43bb9SRobert Marko u32 val; 799a0e43bb9SRobert Marko 8006e0832faSShawn Lin writel(SLV_ADDR_SPACE_SZ, 80139171b33SManivannan Sadhasivam pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); 8026e0832faSShawn Lin 80339171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 80417804668SManivannan Sadhasivam val &= ~PHY_TEST_PWR_DOWN; 80539171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 8066e0832faSShawn Lin 80739171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 8086e0832faSShawn Lin 8096e0832faSShawn Lin writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 8106e0832faSShawn Lin | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 8116e0832faSShawn Lin AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 81239171b33SManivannan Sadhasivam pcie->parf + PARF_SYS_CTRL); 81339171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_Q2A_FLUSH); 8146e0832faSShawn Lin 8156e0832faSShawn Lin writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); 81660f0072dSManivannan Sadhasivam 81760f0072dSManivannan Sadhasivam dw_pcie_dbi_ro_wr_en(pci); 81860f0072dSManivannan Sadhasivam 8199a765805SBaruch Siach writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 8206e0832faSShawn Lin 8216e0832faSShawn Lin val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 8226e0832faSShawn Lin val &= ~PCI_EXP_LNKCAP_ASPMS; 8236e0832faSShawn Lin writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 8246e0832faSShawn Lin 8256e0832faSShawn Lin writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 8266e0832faSShawn Lin PCI_EXP_DEVCTL2); 8276e0832faSShawn Lin 828a33d700eSManivannan Sadhasivam dw_pcie_dbi_ro_wr_dis(pci); 829a33d700eSManivannan Sadhasivam 8306e0832faSShawn Lin return 0; 8316e0832faSShawn Lin } 8326e0832faSShawn Lin 833ed8cc3b1SBjorn Andersson static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 834ed8cc3b1SBjorn Andersson { 835ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 836ed8cc3b1SBjorn Andersson struct dw_pcie *pci = pcie->pci; 837ed8cc3b1SBjorn Andersson struct device *dev = pci->dev; 83870574511SJohan Hovold unsigned int num_clks, num_opt_clks; 8391c5aa037SDmitry Baryshkov unsigned int idx; 840ed8cc3b1SBjorn Andersson int ret; 841ed8cc3b1SBjorn Andersson 8426276a403SAbel Vesa res->rst = devm_reset_control_array_get_exclusive(dev); 8436276a403SAbel Vesa if (IS_ERR(res->rst)) 8446276a403SAbel Vesa return PTR_ERR(res->rst); 845ed8cc3b1SBjorn Andersson 846ed8cc3b1SBjorn Andersson res->supplies[0].supply = "vdda"; 847ed8cc3b1SBjorn Andersson res->supplies[1].supply = "vddpe-3v3"; 848ed8cc3b1SBjorn Andersson ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 849ed8cc3b1SBjorn Andersson res->supplies); 850ed8cc3b1SBjorn Andersson if (ret) 851ed8cc3b1SBjorn Andersson return ret; 852ed8cc3b1SBjorn Andersson 8531c5aa037SDmitry Baryshkov idx = 0; 8541c5aa037SDmitry Baryshkov res->clks[idx++].id = "aux"; 8551c5aa037SDmitry Baryshkov res->clks[idx++].id = "cfg"; 8561c5aa037SDmitry Baryshkov res->clks[idx++].id = "bus_master"; 8571c5aa037SDmitry Baryshkov res->clks[idx++].id = "bus_slave"; 8581c5aa037SDmitry Baryshkov res->clks[idx++].id = "slave_q2a"; 8591c5aa037SDmitry Baryshkov 86070574511SJohan Hovold num_clks = idx; 86170574511SJohan Hovold 86270574511SJohan Hovold ret = devm_clk_bulk_get(dev, num_clks, res->clks); 86370574511SJohan Hovold if (ret < 0) 86470574511SJohan Hovold return ret; 86570574511SJohan Hovold 866014aa351SJohan Hovold res->clks[idx++].id = "tbu"; 867014aa351SJohan Hovold res->clks[idx++].id = "ddrss_sf_tbu"; 868014aa351SJohan Hovold res->clks[idx++].id = "aggre0"; 869014aa351SJohan Hovold res->clks[idx++].id = "aggre1"; 8706276a403SAbel Vesa res->clks[idx++].id = "noc_aggr"; 87170574511SJohan Hovold res->clks[idx++].id = "noc_aggr_4"; 87270574511SJohan Hovold res->clks[idx++].id = "noc_aggr_south_sf"; 87370574511SJohan Hovold res->clks[idx++].id = "cnoc_qx"; 8747394d0a8SManivannan Sadhasivam res->clks[idx++].id = "sleep"; 8756276a403SAbel Vesa res->clks[idx++].id = "cnoc_sf_axi"; 87670574511SJohan Hovold 87770574511SJohan Hovold num_opt_clks = idx - num_clks; 8781c5aa037SDmitry Baryshkov res->num_clks = idx; 879ed8cc3b1SBjorn Andersson 88070574511SJohan Hovold ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); 881ed8cc3b1SBjorn Andersson if (ret < 0) 882ed8cc3b1SBjorn Andersson return ret; 883ed8cc3b1SBjorn Andersson 884affac98aSDmitry Baryshkov return 0; 885ed8cc3b1SBjorn Andersson } 886ed8cc3b1SBjorn Andersson 887ed8cc3b1SBjorn Andersson static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 888ed8cc3b1SBjorn Andersson { 889ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 890ed8cc3b1SBjorn Andersson struct dw_pcie *pci = pcie->pci; 891ed8cc3b1SBjorn Andersson struct device *dev = pci->dev; 892ed8cc3b1SBjorn Andersson u32 val; 893ed8cc3b1SBjorn Andersson int ret; 894ed8cc3b1SBjorn Andersson 895ed8cc3b1SBjorn Andersson ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 896ed8cc3b1SBjorn Andersson if (ret < 0) { 897ed8cc3b1SBjorn Andersson dev_err(dev, "cannot enable regulators\n"); 898ed8cc3b1SBjorn Andersson return ret; 899ed8cc3b1SBjorn Andersson } 900ed8cc3b1SBjorn Andersson 9017081556fSDmitry Baryshkov ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 902ed8cc3b1SBjorn Andersson if (ret < 0) 903ed8cc3b1SBjorn Andersson goto err_disable_regulators; 904ed8cc3b1SBjorn Andersson 9056276a403SAbel Vesa ret = reset_control_assert(res->rst); 9066276a403SAbel Vesa if (ret) { 9076276a403SAbel Vesa dev_err(dev, "reset assert failed (%d)\n", ret); 908ed8cc3b1SBjorn Andersson goto err_disable_clocks; 909ed8cc3b1SBjorn Andersson } 910ed8cc3b1SBjorn Andersson 911ed8cc3b1SBjorn Andersson usleep_range(1000, 1500); 912ed8cc3b1SBjorn Andersson 9136276a403SAbel Vesa ret = reset_control_deassert(res->rst); 9146276a403SAbel Vesa if (ret) { 9156276a403SAbel Vesa dev_err(dev, "reset deassert failed (%d)\n", ret); 916ed8cc3b1SBjorn Andersson goto err_disable_clocks; 917ed8cc3b1SBjorn Andersson } 918ed8cc3b1SBjorn Andersson 9191c5aa037SDmitry Baryshkov /* Wait for reset to complete, required on SM8450 */ 9201c5aa037SDmitry Baryshkov usleep_range(1000, 1500); 9211c5aa037SDmitry Baryshkov 922ed8cc3b1SBjorn Andersson /* configure PCIe to RC mode */ 92339171b33SManivannan Sadhasivam writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 924ed8cc3b1SBjorn Andersson 925ed8cc3b1SBjorn Andersson /* enable PCIe clocks and resets */ 92639171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 92717804668SManivannan Sadhasivam val &= ~PHY_TEST_PWR_DOWN; 92839171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 929ed8cc3b1SBjorn Andersson 930ed8cc3b1SBjorn Andersson /* change DBI base address */ 93139171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 932ed8cc3b1SBjorn Andersson 933ed8cc3b1SBjorn Andersson /* MAC PHY_POWERDOWN MUX DISABLE */ 93439171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_SYS_CTRL); 93517804668SManivannan Sadhasivam val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 93639171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_SYS_CTRL); 937ed8cc3b1SBjorn Andersson 93839171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 93917804668SManivannan Sadhasivam val |= BYPASS; 94039171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 941ed8cc3b1SBjorn Andersson 9425147ba8aSKrishna chaitanya chundru /* Enable L1 and L1SS */ 94339171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PM_CTRL); 9445147ba8aSKrishna chaitanya chundru val &= ~REQ_NOT_ENTR_L1; 94539171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PM_CTRL); 9465147ba8aSKrishna chaitanya chundru 94739171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 94817804668SManivannan Sadhasivam val |= EN; 94939171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 950ed8cc3b1SBjorn Andersson 951ed8cc3b1SBjorn Andersson return 0; 952ed8cc3b1SBjorn Andersson err_disable_clocks: 9537081556fSDmitry Baryshkov clk_bulk_disable_unprepare(res->num_clks, res->clks); 954ed8cc3b1SBjorn Andersson err_disable_regulators: 955ed8cc3b1SBjorn Andersson regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 956ed8cc3b1SBjorn Andersson 957ed8cc3b1SBjorn Andersson return ret; 958ed8cc3b1SBjorn Andersson } 959ed8cc3b1SBjorn Andersson 960a54db86dSManivannan Sadhasivam static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) 961a54db86dSManivannan Sadhasivam { 962a54db86dSManivannan Sadhasivam qcom_pcie_clear_hpc(pcie->pci); 963a54db86dSManivannan Sadhasivam 964a54db86dSManivannan Sadhasivam return 0; 965a54db86dSManivannan Sadhasivam } 966a54db86dSManivannan Sadhasivam 967ed8cc3b1SBjorn Andersson static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) 968ed8cc3b1SBjorn Andersson { 969ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 970ed8cc3b1SBjorn Andersson 9717081556fSDmitry Baryshkov clk_bulk_disable_unprepare(res->num_clks, res->clks); 9727eb5768cSDmitry Baryshkov 973ed8cc3b1SBjorn Andersson regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 974ed8cc3b1SBjorn Andersson } 975ed8cc3b1SBjorn Andersson 9761f709398SManivannan Sadhasivam static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) 9771f709398SManivannan Sadhasivam { 9781f709398SManivannan Sadhasivam /* iommu map structure */ 9791f709398SManivannan Sadhasivam struct { 9801f709398SManivannan Sadhasivam u32 bdf; 9811f709398SManivannan Sadhasivam u32 phandle; 9821f709398SManivannan Sadhasivam u32 smmu_sid; 9831f709398SManivannan Sadhasivam u32 smmu_sid_len; 9841f709398SManivannan Sadhasivam } *map; 9851f709398SManivannan Sadhasivam void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; 9861f709398SManivannan Sadhasivam struct device *dev = pcie->pci->dev; 9871f709398SManivannan Sadhasivam u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 9881f709398SManivannan Sadhasivam int i, nr_map, size = 0; 9891f709398SManivannan Sadhasivam u32 smmu_sid_base; 9901f709398SManivannan Sadhasivam 9911f709398SManivannan Sadhasivam of_get_property(dev->of_node, "iommu-map", &size); 9921f709398SManivannan Sadhasivam if (!size) 9931f709398SManivannan Sadhasivam return 0; 9941f709398SManivannan Sadhasivam 9951f709398SManivannan Sadhasivam map = kzalloc(size, GFP_KERNEL); 9961f709398SManivannan Sadhasivam if (!map) 9971f709398SManivannan Sadhasivam return -ENOMEM; 9981f709398SManivannan Sadhasivam 9991f709398SManivannan Sadhasivam of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, 10001f709398SManivannan Sadhasivam size / sizeof(u32)); 10011f709398SManivannan Sadhasivam 10021f709398SManivannan Sadhasivam nr_map = size / (sizeof(*map)); 10031f709398SManivannan Sadhasivam 10041f709398SManivannan Sadhasivam crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 10051f709398SManivannan Sadhasivam 10061f709398SManivannan Sadhasivam /* Registers need to be zero out first */ 10071f709398SManivannan Sadhasivam memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 10081f709398SManivannan Sadhasivam 10091f709398SManivannan Sadhasivam /* Extract the SMMU SID base from the first entry of iommu-map */ 10101f709398SManivannan Sadhasivam smmu_sid_base = map[0].smmu_sid; 10111f709398SManivannan Sadhasivam 10121f709398SManivannan Sadhasivam /* Look for an available entry to hold the mapping */ 10131f709398SManivannan Sadhasivam for (i = 0; i < nr_map; i++) { 10141f709398SManivannan Sadhasivam __be16 bdf_be = cpu_to_be16(map[i].bdf); 10151f709398SManivannan Sadhasivam u32 val; 10161f709398SManivannan Sadhasivam u8 hash; 10171f709398SManivannan Sadhasivam 10181f709398SManivannan Sadhasivam hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0); 10191f709398SManivannan Sadhasivam 10201f709398SManivannan Sadhasivam val = readl(bdf_to_sid_base + hash * sizeof(u32)); 10211f709398SManivannan Sadhasivam 10221f709398SManivannan Sadhasivam /* If the register is already populated, look for next available entry */ 10231f709398SManivannan Sadhasivam while (val) { 10241f709398SManivannan Sadhasivam u8 current_hash = hash++; 10251f709398SManivannan Sadhasivam u8 next_mask = 0xff; 10261f709398SManivannan Sadhasivam 10271f709398SManivannan Sadhasivam /* If NEXT field is NULL then update it with next hash */ 10281f709398SManivannan Sadhasivam if (!(val & next_mask)) { 10291f709398SManivannan Sadhasivam val |= (u32)hash; 10301f709398SManivannan Sadhasivam writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 10311f709398SManivannan Sadhasivam } 10321f709398SManivannan Sadhasivam 10331f709398SManivannan Sadhasivam val = readl(bdf_to_sid_base + hash * sizeof(u32)); 10341f709398SManivannan Sadhasivam } 10351f709398SManivannan Sadhasivam 10361f709398SManivannan Sadhasivam /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 10371f709398SManivannan Sadhasivam val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 10381f709398SManivannan Sadhasivam writel(val, bdf_to_sid_base + hash * sizeof(u32)); 10391f709398SManivannan Sadhasivam } 10401f709398SManivannan Sadhasivam 10411f709398SManivannan Sadhasivam kfree(map); 10421f709398SManivannan Sadhasivam 10431f709398SManivannan Sadhasivam return 0; 10441f709398SManivannan Sadhasivam } 10451f709398SManivannan Sadhasivam 10460cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) 1047ed8cc3b1SBjorn Andersson { 10480cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 10490cf7c2efSSelvam Sathappan Periakaruppan struct dw_pcie *pci = pcie->pci; 10500cf7c2efSSelvam Sathappan Periakaruppan struct device *dev = pci->dev; 10510cf7c2efSSelvam Sathappan Periakaruppan int ret; 1052ed8cc3b1SBjorn Andersson 10530cf7c2efSSelvam Sathappan Periakaruppan res->clks[0].id = "iface"; 10540cf7c2efSSelvam Sathappan Periakaruppan res->clks[1].id = "axi_m"; 10550cf7c2efSSelvam Sathappan Periakaruppan res->clks[2].id = "axi_s"; 10560cf7c2efSSelvam Sathappan Periakaruppan res->clks[3].id = "axi_bridge"; 10570cf7c2efSSelvam Sathappan Periakaruppan res->clks[4].id = "rchng"; 1058aa9c0df9SPrasad Malisetty 10590cf7c2efSSelvam Sathappan Periakaruppan ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 10600cf7c2efSSelvam Sathappan Periakaruppan if (ret < 0) 10610cf7c2efSSelvam Sathappan Periakaruppan return ret; 10620cf7c2efSSelvam Sathappan Periakaruppan 10630cf7c2efSSelvam Sathappan Periakaruppan res->rst = devm_reset_control_array_get_exclusive(dev); 10640cf7c2efSSelvam Sathappan Periakaruppan if (IS_ERR(res->rst)) 10650cf7c2efSSelvam Sathappan Periakaruppan return PTR_ERR(res->rst); 10660cf7c2efSSelvam Sathappan Periakaruppan 10670cf7c2efSSelvam Sathappan Periakaruppan return 0; 1068ed8cc3b1SBjorn Andersson } 1069ed8cc3b1SBjorn Andersson 10700cf7c2efSSelvam Sathappan Periakaruppan static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) 1071ed8cc3b1SBjorn Andersson { 10720cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1073ed8cc3b1SBjorn Andersson 10740cf7c2efSSelvam Sathappan Periakaruppan clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 10750cf7c2efSSelvam Sathappan Periakaruppan } 10760cf7c2efSSelvam Sathappan Periakaruppan 10770cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) 10780cf7c2efSSelvam Sathappan Periakaruppan { 10790cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 10800cf7c2efSSelvam Sathappan Periakaruppan struct device *dev = pcie->pci->dev; 10810cf7c2efSSelvam Sathappan Periakaruppan int ret; 10820cf7c2efSSelvam Sathappan Periakaruppan 10830cf7c2efSSelvam Sathappan Periakaruppan ret = reset_control_assert(res->rst); 10840cf7c2efSSelvam Sathappan Periakaruppan if (ret) { 10850cf7c2efSSelvam Sathappan Periakaruppan dev_err(dev, "reset assert failed (%d)\n", ret); 10860cf7c2efSSelvam Sathappan Periakaruppan return ret; 10870cf7c2efSSelvam Sathappan Periakaruppan } 10880cf7c2efSSelvam Sathappan Periakaruppan 10890cf7c2efSSelvam Sathappan Periakaruppan /* 10900cf7c2efSSelvam Sathappan Periakaruppan * Delay periods before and after reset deassert are working values 10910cf7c2efSSelvam Sathappan Periakaruppan * from downstream Codeaurora kernel 10920cf7c2efSSelvam Sathappan Periakaruppan */ 10930cf7c2efSSelvam Sathappan Periakaruppan usleep_range(2000, 2500); 10940cf7c2efSSelvam Sathappan Periakaruppan 10950cf7c2efSSelvam Sathappan Periakaruppan ret = reset_control_deassert(res->rst); 10960cf7c2efSSelvam Sathappan Periakaruppan if (ret) { 10970cf7c2efSSelvam Sathappan Periakaruppan dev_err(dev, "reset deassert failed (%d)\n", ret); 10980cf7c2efSSelvam Sathappan Periakaruppan return ret; 10990cf7c2efSSelvam Sathappan Periakaruppan } 11000cf7c2efSSelvam Sathappan Periakaruppan 11010cf7c2efSSelvam Sathappan Periakaruppan usleep_range(2000, 2500); 11020cf7c2efSSelvam Sathappan Periakaruppan 11030cf7c2efSSelvam Sathappan Periakaruppan return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 11040cf7c2efSSelvam Sathappan Periakaruppan } 11050cf7c2efSSelvam Sathappan Periakaruppan 11060cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) 11070cf7c2efSSelvam Sathappan Periakaruppan { 11080cf7c2efSSelvam Sathappan Periakaruppan struct dw_pcie *pci = pcie->pci; 11090cf7c2efSSelvam Sathappan Periakaruppan u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 11100cf7c2efSSelvam Sathappan Periakaruppan u32 val; 11110cf7c2efSSelvam Sathappan Periakaruppan int i; 11120cf7c2efSSelvam Sathappan Periakaruppan 11130cf7c2efSSelvam Sathappan Periakaruppan writel(SLV_ADDR_SPACE_SZ, 111439171b33SManivannan Sadhasivam pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); 11150cf7c2efSSelvam Sathappan Periakaruppan 111639171b33SManivannan Sadhasivam val = readl(pcie->parf + PARF_PHY_CTRL); 111717804668SManivannan Sadhasivam val &= ~PHY_TEST_PWR_DOWN; 111839171b33SManivannan Sadhasivam writel(val, pcie->parf + PARF_PHY_CTRL); 11190cf7c2efSSelvam Sathappan Periakaruppan 112039171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 11210cf7c2efSSelvam Sathappan Periakaruppan 112239171b33SManivannan Sadhasivam writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 11230cf7c2efSSelvam Sathappan Periakaruppan writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, 112439171b33SManivannan Sadhasivam pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 11250cf7c2efSSelvam Sathappan Periakaruppan writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | 11260cf7c2efSSelvam Sathappan Periakaruppan GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 11270cf7c2efSSelvam Sathappan Periakaruppan pci->dbi_base + GEN3_RELATED_OFF); 11280cf7c2efSSelvam Sathappan Periakaruppan 11290cf7c2efSSelvam Sathappan Periakaruppan writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | 11300cf7c2efSSelvam Sathappan Periakaruppan SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 11310cf7c2efSSelvam Sathappan Periakaruppan AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 113239171b33SManivannan Sadhasivam pcie->parf + PARF_SYS_CTRL); 11330cf7c2efSSelvam Sathappan Periakaruppan 113439171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_Q2A_FLUSH); 11350cf7c2efSSelvam Sathappan Periakaruppan 11360cf7c2efSSelvam Sathappan Periakaruppan dw_pcie_dbi_ro_wr_en(pci); 1137200b8f85SManivannan Sadhasivam 11380cf7c2efSSelvam Sathappan Periakaruppan writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 11390cf7c2efSSelvam Sathappan Periakaruppan 11400cf7c2efSSelvam Sathappan Periakaruppan val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 11410cf7c2efSSelvam Sathappan Periakaruppan val &= ~PCI_EXP_LNKCAP_ASPMS; 11420cf7c2efSSelvam Sathappan Periakaruppan writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 11430cf7c2efSSelvam Sathappan Periakaruppan 11440cf7c2efSSelvam Sathappan Periakaruppan writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 11450cf7c2efSSelvam Sathappan Periakaruppan PCI_EXP_DEVCTL2); 11460cf7c2efSSelvam Sathappan Periakaruppan 1147200b8f85SManivannan Sadhasivam dw_pcie_dbi_ro_wr_dis(pci); 1148200b8f85SManivannan Sadhasivam 11490cf7c2efSSelvam Sathappan Periakaruppan for (i = 0; i < 256; i++) 115039171b33SManivannan Sadhasivam writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); 11510cf7c2efSSelvam Sathappan Periakaruppan 11520cf7c2efSSelvam Sathappan Periakaruppan return 0; 1153ed8cc3b1SBjorn Andersson } 1154ed8cc3b1SBjorn Andersson 11556e0832faSShawn Lin static int qcom_pcie_link_up(struct dw_pcie *pci) 11566e0832faSShawn Lin { 11577b87ddc0SRob Herring u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 11587b87ddc0SRob Herring u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 11596e0832faSShawn Lin 11606e0832faSShawn Lin return !!(val & PCI_EXP_LNKSTA_DLLLA); 11616e0832faSShawn Lin } 11626e0832faSShawn Lin 116360b3c27fSSerge Semin static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 11646e0832faSShawn Lin { 11656e0832faSShawn Lin struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 11666e0832faSShawn Lin struct qcom_pcie *pcie = to_qcom_pcie(pci); 11676e0832faSShawn Lin int ret; 11686e0832faSShawn Lin 11696e0832faSShawn Lin qcom_ep_reset_assert(pcie); 11706e0832faSShawn Lin 1171f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->init(pcie); 11726e0832faSShawn Lin if (ret) 11736e0832faSShawn Lin return ret; 11746e0832faSShawn Lin 1175f90747d1SDmitry Baryshkov ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1176f90747d1SDmitry Baryshkov if (ret) 1177f90747d1SDmitry Baryshkov goto err_deinit; 1178f90747d1SDmitry Baryshkov 11796e0832faSShawn Lin ret = phy_power_on(pcie->phy); 11806e0832faSShawn Lin if (ret) 11816e0832faSShawn Lin goto err_deinit; 11826e0832faSShawn Lin 1183f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->post_init) { 1184f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->post_init(pcie); 11856e0832faSShawn Lin if (ret) 11866e0832faSShawn Lin goto err_disable_phy; 11876e0832faSShawn Lin } 11886e0832faSShawn Lin 11896e0832faSShawn Lin qcom_ep_reset_deassert(pcie); 11906e0832faSShawn Lin 1191f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->config_sid) { 1192f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->config_sid(pcie); 11934c939882SManivannan Sadhasivam if (ret) 11940e4d9a5cSJohan Hovold goto err_assert_reset; 11954c939882SManivannan Sadhasivam } 11964c939882SManivannan Sadhasivam 11976e0832faSShawn Lin return 0; 1198886a9c13SRob Herring 11990e4d9a5cSJohan Hovold err_assert_reset: 12004c939882SManivannan Sadhasivam qcom_ep_reset_assert(pcie); 12016e0832faSShawn Lin err_disable_phy: 12026e0832faSShawn Lin phy_power_off(pcie->phy); 12036e0832faSShawn Lin err_deinit: 1204f94c35e0SDmitry Baryshkov pcie->cfg->ops->deinit(pcie); 12056e0832faSShawn Lin 12066e0832faSShawn Lin return ret; 12076e0832faSShawn Lin } 12086e0832faSShawn Lin 1209997e010dSJohan Hovold static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) 1210997e010dSJohan Hovold { 1211997e010dSJohan Hovold struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1212997e010dSJohan Hovold struct qcom_pcie *pcie = to_qcom_pcie(pci); 1213997e010dSJohan Hovold 1214997e010dSJohan Hovold qcom_ep_reset_assert(pcie); 1215997e010dSJohan Hovold phy_power_off(pcie->phy); 1216997e010dSJohan Hovold pcie->cfg->ops->deinit(pcie); 1217997e010dSJohan Hovold } 1218997e010dSJohan Hovold 12196e0832faSShawn Lin static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 12206e0832faSShawn Lin .host_init = qcom_pcie_host_init, 1221997e010dSJohan Hovold .host_deinit = qcom_pcie_host_deinit, 12226e0832faSShawn Lin }; 12236e0832faSShawn Lin 12246e0832faSShawn Lin /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ 12256e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_1_0 = { 12266e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_1_0, 12276e0832faSShawn Lin .init = qcom_pcie_init_2_1_0, 122836d9018dSRobert Marko .post_init = qcom_pcie_post_init_2_1_0, 12296e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_1_0, 12306e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 12316e0832faSShawn Lin }; 12326e0832faSShawn Lin 12336e0832faSShawn Lin /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ 12346e0832faSShawn Lin static const struct qcom_pcie_ops ops_1_0_0 = { 12356e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_1_0_0, 12366e0832faSShawn Lin .init = qcom_pcie_init_1_0_0, 123736d9018dSRobert Marko .post_init = qcom_pcie_post_init_1_0_0, 12386e0832faSShawn Lin .deinit = qcom_pcie_deinit_1_0_0, 12396e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 12406e0832faSShawn Lin }; 12416e0832faSShawn Lin 12426e0832faSShawn Lin /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ 12436e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_3_2 = { 12446e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_3_2, 12456e0832faSShawn Lin .init = qcom_pcie_init_2_3_2, 12466e0832faSShawn Lin .post_init = qcom_pcie_post_init_2_3_2, 12476e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_3_2, 12486e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 12496e0832faSShawn Lin }; 12506e0832faSShawn Lin 12516e0832faSShawn Lin /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */ 12526e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_4_0 = { 12536e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_4_0, 12546e0832faSShawn Lin .init = qcom_pcie_init_2_4_0, 1255e35d13a5SManivannan Sadhasivam .post_init = qcom_pcie_post_init_2_3_2, 12566e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_4_0, 12576e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 12586e0832faSShawn Lin }; 12596e0832faSShawn Lin 12606e0832faSShawn Lin /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */ 12616e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_3_3 = { 12626e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_3_3, 12636e0832faSShawn Lin .init = qcom_pcie_init_2_3_3, 1264a0e43bb9SRobert Marko .post_init = qcom_pcie_post_init_2_3_3, 12656e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_3_3, 12666e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 12676e0832faSShawn Lin }; 12686e0832faSShawn Lin 1269ed8cc3b1SBjorn Andersson /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ 1270ed8cc3b1SBjorn Andersson static const struct qcom_pcie_ops ops_2_7_0 = { 1271ed8cc3b1SBjorn Andersson .get_resources = qcom_pcie_get_resources_2_7_0, 1272ed8cc3b1SBjorn Andersson .init = qcom_pcie_init_2_7_0, 1273a54db86dSManivannan Sadhasivam .post_init = qcom_pcie_post_init_2_7_0, 1274ed8cc3b1SBjorn Andersson .deinit = qcom_pcie_deinit_2_7_0, 1275ed8cc3b1SBjorn Andersson .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1276ed8cc3b1SBjorn Andersson }; 1277ed8cc3b1SBjorn Andersson 1278e1dd639eSManivannan Sadhasivam /* Qcom IP rev.: 1.9.0 */ 1279e1dd639eSManivannan Sadhasivam static const struct qcom_pcie_ops ops_1_9_0 = { 1280e1dd639eSManivannan Sadhasivam .get_resources = qcom_pcie_get_resources_2_7_0, 1281e1dd639eSManivannan Sadhasivam .init = qcom_pcie_init_2_7_0, 1282a54db86dSManivannan Sadhasivam .post_init = qcom_pcie_post_init_2_7_0, 1283e1dd639eSManivannan Sadhasivam .deinit = qcom_pcie_deinit_2_7_0, 1284e1dd639eSManivannan Sadhasivam .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 12851f709398SManivannan Sadhasivam .config_sid = qcom_pcie_config_sid_1_9_0, 1286e1dd639eSManivannan Sadhasivam }; 1287e1dd639eSManivannan Sadhasivam 12880cf7c2efSSelvam Sathappan Periakaruppan /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ 12890cf7c2efSSelvam Sathappan Periakaruppan static const struct qcom_pcie_ops ops_2_9_0 = { 12900cf7c2efSSelvam Sathappan Periakaruppan .get_resources = qcom_pcie_get_resources_2_9_0, 12910cf7c2efSSelvam Sathappan Periakaruppan .init = qcom_pcie_init_2_9_0, 12920cf7c2efSSelvam Sathappan Periakaruppan .post_init = qcom_pcie_post_init_2_9_0, 12930cf7c2efSSelvam Sathappan Periakaruppan .deinit = qcom_pcie_deinit_2_9_0, 12940cf7c2efSSelvam Sathappan Periakaruppan .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 12950cf7c2efSSelvam Sathappan Periakaruppan }; 12960cf7c2efSSelvam Sathappan Periakaruppan 129722311735SJohan Hovold static const struct qcom_pcie_cfg cfg_1_0_0 = { 1298b89ff410SPrasad Malisetty .ops = &ops_1_0_0, 1299b89ff410SPrasad Malisetty }; 1300b89ff410SPrasad Malisetty 130122311735SJohan Hovold static const struct qcom_pcie_cfg cfg_1_9_0 = { 130222311735SJohan Hovold .ops = &ops_1_9_0, 130322311735SJohan Hovold }; 130422311735SJohan Hovold 130522311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_1_0 = { 1306b89ff410SPrasad Malisetty .ops = &ops_2_1_0, 1307b89ff410SPrasad Malisetty }; 1308b89ff410SPrasad Malisetty 130922311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_3_2 = { 1310b89ff410SPrasad Malisetty .ops = &ops_2_3_2, 1311b89ff410SPrasad Malisetty }; 1312b89ff410SPrasad Malisetty 131322311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_3_3 = { 1314b89ff410SPrasad Malisetty .ops = &ops_2_3_3, 1315b89ff410SPrasad Malisetty }; 1316b89ff410SPrasad Malisetty 131722311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_4_0 = { 1318b89ff410SPrasad Malisetty .ops = &ops_2_4_0, 1319b89ff410SPrasad Malisetty }; 1320b89ff410SPrasad Malisetty 132122311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_7_0 = { 1322b89ff410SPrasad Malisetty .ops = &ops_2_7_0, 1323b89ff410SPrasad Malisetty }; 1324b89ff410SPrasad Malisetty 132522311735SJohan Hovold static const struct qcom_pcie_cfg cfg_2_9_0 = { 13260cf7c2efSSelvam Sathappan Periakaruppan .ops = &ops_2_9_0, 13270cf7c2efSSelvam Sathappan Periakaruppan }; 13280cf7c2efSSelvam Sathappan Periakaruppan 13296e0832faSShawn Lin static const struct dw_pcie_ops dw_pcie_ops = { 13306e0832faSShawn Lin .link_up = qcom_pcie_link_up, 1331886a9c13SRob Herring .start_link = qcom_pcie_start_link, 13326e0832faSShawn Lin }; 13336e0832faSShawn Lin 1334c4860af8SJohan Hovold static int qcom_pcie_icc_init(struct qcom_pcie *pcie) 1335c4860af8SJohan Hovold { 1336c4860af8SJohan Hovold struct dw_pcie *pci = pcie->pci; 1337c4860af8SJohan Hovold int ret; 1338c4860af8SJohan Hovold 1339c4860af8SJohan Hovold pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); 1340c4860af8SJohan Hovold if (IS_ERR(pcie->icc_mem)) 1341c4860af8SJohan Hovold return PTR_ERR(pcie->icc_mem); 1342c4860af8SJohan Hovold 1343c4860af8SJohan Hovold /* 1344c4860af8SJohan Hovold * Some Qualcomm platforms require interconnect bandwidth constraints 1345c4860af8SJohan Hovold * to be set before enabling interconnect clocks. 1346c4860af8SJohan Hovold * 1347c4860af8SJohan Hovold * Set an initial peak bandwidth corresponding to single-lane Gen 1 1348c4860af8SJohan Hovold * for the pcie-mem path. 1349c4860af8SJohan Hovold */ 1350c4860af8SJohan Hovold ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); 1351c4860af8SJohan Hovold if (ret) { 1352c4860af8SJohan Hovold dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 1353c4860af8SJohan Hovold ret); 1354c4860af8SJohan Hovold return ret; 1355c4860af8SJohan Hovold } 1356c4860af8SJohan Hovold 1357c4860af8SJohan Hovold return 0; 1358c4860af8SJohan Hovold } 1359c4860af8SJohan Hovold 1360c4860af8SJohan Hovold static void qcom_pcie_icc_update(struct qcom_pcie *pcie) 1361c4860af8SJohan Hovold { 1362c4860af8SJohan Hovold struct dw_pcie *pci = pcie->pci; 1363c4860af8SJohan Hovold u32 offset, status, bw; 1364c4860af8SJohan Hovold int speed, width; 1365c4860af8SJohan Hovold int ret; 1366c4860af8SJohan Hovold 1367c4860af8SJohan Hovold if (!pcie->icc_mem) 1368c4860af8SJohan Hovold return; 1369c4860af8SJohan Hovold 1370c4860af8SJohan Hovold offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1371c4860af8SJohan Hovold status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1372c4860af8SJohan Hovold 1373c4860af8SJohan Hovold /* Only update constraints if link is up. */ 1374c4860af8SJohan Hovold if (!(status & PCI_EXP_LNKSTA_DLLLA)) 1375c4860af8SJohan Hovold return; 1376c4860af8SJohan Hovold 1377c4860af8SJohan Hovold speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 1378c4860af8SJohan Hovold width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 1379c4860af8SJohan Hovold 1380c4860af8SJohan Hovold switch (speed) { 1381c4860af8SJohan Hovold case 1: 1382c4860af8SJohan Hovold bw = MBps_to_icc(250); 1383c4860af8SJohan Hovold break; 1384c4860af8SJohan Hovold case 2: 1385c4860af8SJohan Hovold bw = MBps_to_icc(500); 1386c4860af8SJohan Hovold break; 1387c4860af8SJohan Hovold default: 1388c4860af8SJohan Hovold WARN_ON_ONCE(1); 1389c4860af8SJohan Hovold fallthrough; 1390c4860af8SJohan Hovold case 3: 1391c4860af8SJohan Hovold bw = MBps_to_icc(985); 1392c4860af8SJohan Hovold break; 1393c4860af8SJohan Hovold } 1394c4860af8SJohan Hovold 1395c4860af8SJohan Hovold ret = icc_set_bw(pcie->icc_mem, 0, width * bw); 1396c4860af8SJohan Hovold if (ret) { 1397c4860af8SJohan Hovold dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 1398c4860af8SJohan Hovold ret); 1399c4860af8SJohan Hovold } 1400c4860af8SJohan Hovold } 1401c4860af8SJohan Hovold 140205f46464SManivannan Sadhasivam static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) 140305f46464SManivannan Sadhasivam { 140405f46464SManivannan Sadhasivam struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); 140505f46464SManivannan Sadhasivam 140605f46464SManivannan Sadhasivam seq_printf(s, "L0s transition count: %u\n", 140705f46464SManivannan Sadhasivam readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 140805f46464SManivannan Sadhasivam 140905f46464SManivannan Sadhasivam seq_printf(s, "L1 transition count: %u\n", 141005f46464SManivannan Sadhasivam readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 141105f46464SManivannan Sadhasivam 141205f46464SManivannan Sadhasivam seq_printf(s, "L1.1 transition count: %u\n", 141305f46464SManivannan Sadhasivam readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 141405f46464SManivannan Sadhasivam 141505f46464SManivannan Sadhasivam seq_printf(s, "L1.2 transition count: %u\n", 141605f46464SManivannan Sadhasivam readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 141705f46464SManivannan Sadhasivam 141805f46464SManivannan Sadhasivam seq_printf(s, "L2 transition count: %u\n", 141905f46464SManivannan Sadhasivam readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 142005f46464SManivannan Sadhasivam 142105f46464SManivannan Sadhasivam return 0; 142205f46464SManivannan Sadhasivam } 142305f46464SManivannan Sadhasivam 142405f46464SManivannan Sadhasivam static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) 142505f46464SManivannan Sadhasivam { 142605f46464SManivannan Sadhasivam struct dw_pcie *pci = pcie->pci; 142705f46464SManivannan Sadhasivam struct device *dev = pci->dev; 142805f46464SManivannan Sadhasivam char *name; 142905f46464SManivannan Sadhasivam 143005f46464SManivannan Sadhasivam name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 143105f46464SManivannan Sadhasivam if (!name) 143205f46464SManivannan Sadhasivam return; 143305f46464SManivannan Sadhasivam 143405f46464SManivannan Sadhasivam pcie->debugfs = debugfs_create_dir(name, NULL); 143505f46464SManivannan Sadhasivam debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, 143605f46464SManivannan Sadhasivam qcom_pcie_link_transition_count); 143705f46464SManivannan Sadhasivam } 143805f46464SManivannan Sadhasivam 14396e0832faSShawn Lin static int qcom_pcie_probe(struct platform_device *pdev) 14406e0832faSShawn Lin { 1441b89ff410SPrasad Malisetty const struct qcom_pcie_cfg *pcie_cfg; 144205f46464SManivannan Sadhasivam struct device *dev = &pdev->dev; 144305f46464SManivannan Sadhasivam struct qcom_pcie *pcie; 144405f46464SManivannan Sadhasivam struct dw_pcie_rp *pp; 144505f46464SManivannan Sadhasivam struct resource *res; 144605f46464SManivannan Sadhasivam struct dw_pcie *pci; 14476e0832faSShawn Lin int ret; 14486e0832faSShawn Lin 14494e0e9053SChristophe JAILLET pcie_cfg = of_device_get_match_data(dev); 14504e0e9053SChristophe JAILLET if (!pcie_cfg || !pcie_cfg->ops) { 14514e0e9053SChristophe JAILLET dev_err(dev, "Invalid platform data\n"); 14524e0e9053SChristophe JAILLET return -EINVAL; 14534e0e9053SChristophe JAILLET } 14544e0e9053SChristophe JAILLET 14556e0832faSShawn Lin pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 14566e0832faSShawn Lin if (!pcie) 14576e0832faSShawn Lin return -ENOMEM; 14586e0832faSShawn Lin 14596e0832faSShawn Lin pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 14606e0832faSShawn Lin if (!pci) 14616e0832faSShawn Lin return -ENOMEM; 14626e0832faSShawn Lin 14636e0832faSShawn Lin pm_runtime_enable(dev); 14646e5da6f7SBjorn Andersson ret = pm_runtime_get_sync(dev); 1465cb52a402SDinghao Liu if (ret < 0) 1466cb52a402SDinghao Liu goto err_pm_runtime_put; 14676e5da6f7SBjorn Andersson 14686e0832faSShawn Lin pci->dev = dev; 14696e0832faSShawn Lin pci->ops = &dw_pcie_ops; 14706e0832faSShawn Lin pp = &pci->pp; 14716e0832faSShawn Lin 14726e0832faSShawn Lin pcie->pci = pci; 14736e0832faSShawn Lin 1474f94c35e0SDmitry Baryshkov pcie->cfg = pcie_cfg; 14756e0832faSShawn Lin 147602b485e3SBjorn Andersson pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 14776e5da6f7SBjorn Andersson if (IS_ERR(pcie->reset)) { 14786e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->reset); 14796e5da6f7SBjorn Andersson goto err_pm_runtime_put; 14806e5da6f7SBjorn Andersson } 14816e0832faSShawn Lin 1482936fa5cdSDejin Zheng pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 14836e5da6f7SBjorn Andersson if (IS_ERR(pcie->parf)) { 14846e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->parf); 14856e5da6f7SBjorn Andersson goto err_pm_runtime_put; 14866e5da6f7SBjorn Andersson } 14876e0832faSShawn Lin 1488936fa5cdSDejin Zheng pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 14896e5da6f7SBjorn Andersson if (IS_ERR(pcie->elbi)) { 14906e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->elbi); 14916e5da6f7SBjorn Andersson goto err_pm_runtime_put; 14926e5da6f7SBjorn Andersson } 14936e0832faSShawn Lin 149405f46464SManivannan Sadhasivam /* MHI region is optional */ 149505f46464SManivannan Sadhasivam res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi"); 149605f46464SManivannan Sadhasivam if (res) { 149705f46464SManivannan Sadhasivam pcie->mhi = devm_ioremap_resource(dev, res); 149805f46464SManivannan Sadhasivam if (IS_ERR(pcie->mhi)) { 149905f46464SManivannan Sadhasivam ret = PTR_ERR(pcie->mhi); 150005f46464SManivannan Sadhasivam goto err_pm_runtime_put; 150105f46464SManivannan Sadhasivam } 150205f46464SManivannan Sadhasivam } 150305f46464SManivannan Sadhasivam 15046e0832faSShawn Lin pcie->phy = devm_phy_optional_get(dev, "pciephy"); 15056e5da6f7SBjorn Andersson if (IS_ERR(pcie->phy)) { 15066e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->phy); 15076e5da6f7SBjorn Andersson goto err_pm_runtime_put; 15086e5da6f7SBjorn Andersson } 15096e0832faSShawn Lin 1510c4860af8SJohan Hovold ret = qcom_pcie_icc_init(pcie); 1511c4860af8SJohan Hovold if (ret) 1512c4860af8SJohan Hovold goto err_pm_runtime_put; 1513c4860af8SJohan Hovold 1514f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->get_resources(pcie); 15156e0832faSShawn Lin if (ret) 15166e5da6f7SBjorn Andersson goto err_pm_runtime_put; 15176e0832faSShawn Lin 15186e0832faSShawn Lin pp->ops = &qcom_pcie_dw_ops; 15196e0832faSShawn Lin 15206e0832faSShawn Lin ret = phy_init(pcie->phy); 152187d83b96SJohan Hovold if (ret) 15226e5da6f7SBjorn Andersson goto err_pm_runtime_put; 15236e0832faSShawn Lin 15246e0832faSShawn Lin platform_set_drvdata(pdev, pcie); 15256e0832faSShawn Lin 15266e0832faSShawn Lin ret = dw_pcie_host_init(pp); 15276e0832faSShawn Lin if (ret) { 15286e0832faSShawn Lin dev_err(dev, "cannot initialize host\n"); 152983013631SJohan Hovold goto err_phy_exit; 15306e0832faSShawn Lin } 15316e0832faSShawn Lin 1532c4860af8SJohan Hovold qcom_pcie_icc_update(pcie); 1533c4860af8SJohan Hovold 153405f46464SManivannan Sadhasivam if (pcie->mhi) 153505f46464SManivannan Sadhasivam qcom_pcie_init_debugfs(pcie); 153605f46464SManivannan Sadhasivam 15376e0832faSShawn Lin return 0; 15386e5da6f7SBjorn Andersson 153983013631SJohan Hovold err_phy_exit: 154083013631SJohan Hovold phy_exit(pcie->phy); 15416e5da6f7SBjorn Andersson err_pm_runtime_put: 15426e5da6f7SBjorn Andersson pm_runtime_put(dev); 15436e5da6f7SBjorn Andersson pm_runtime_disable(dev); 15446e5da6f7SBjorn Andersson 15456e5da6f7SBjorn Andersson return ret; 15466e0832faSShawn Lin } 15476e0832faSShawn Lin 1548ad9b9b6eSManivannan Sadhasivam static int qcom_pcie_suspend_noirq(struct device *dev) 1549ad9b9b6eSManivannan Sadhasivam { 1550ad9b9b6eSManivannan Sadhasivam struct qcom_pcie *pcie = dev_get_drvdata(dev); 1551ad9b9b6eSManivannan Sadhasivam int ret; 1552ad9b9b6eSManivannan Sadhasivam 1553ad9b9b6eSManivannan Sadhasivam /* 1554ad9b9b6eSManivannan Sadhasivam * Set minimum bandwidth required to keep data path functional during 1555ad9b9b6eSManivannan Sadhasivam * suspend. 1556ad9b9b6eSManivannan Sadhasivam */ 1557ad9b9b6eSManivannan Sadhasivam ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); 1558ad9b9b6eSManivannan Sadhasivam if (ret) { 1559ad9b9b6eSManivannan Sadhasivam dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); 1560ad9b9b6eSManivannan Sadhasivam return ret; 1561ad9b9b6eSManivannan Sadhasivam } 1562ad9b9b6eSManivannan Sadhasivam 1563ad9b9b6eSManivannan Sadhasivam /* 1564ad9b9b6eSManivannan Sadhasivam * Turn OFF the resources only for controllers without active PCIe 1565ad9b9b6eSManivannan Sadhasivam * devices. For controllers with active devices, the resources are kept 1566ad9b9b6eSManivannan Sadhasivam * ON and the link is expected to be in L0/L1 (sub)states. 1567ad9b9b6eSManivannan Sadhasivam * 1568ad9b9b6eSManivannan Sadhasivam * Turning OFF the resources for controllers with active PCIe devices 1569ad9b9b6eSManivannan Sadhasivam * will trigger access violation during the end of the suspend cycle, 1570ad9b9b6eSManivannan Sadhasivam * as kernel tries to access the PCIe devices config space for masking 1571ad9b9b6eSManivannan Sadhasivam * MSIs. 1572ad9b9b6eSManivannan Sadhasivam * 1573ad9b9b6eSManivannan Sadhasivam * Also, it is not desirable to put the link into L2/L3 state as that 1574ad9b9b6eSManivannan Sadhasivam * implies VDD supply will be removed and the devices may go into 1575ad9b9b6eSManivannan Sadhasivam * powerdown state. This will affect the lifetime of the storage devices 1576ad9b9b6eSManivannan Sadhasivam * like NVMe. 1577ad9b9b6eSManivannan Sadhasivam */ 1578ad9b9b6eSManivannan Sadhasivam if (!dw_pcie_link_up(pcie->pci)) { 1579ad9b9b6eSManivannan Sadhasivam qcom_pcie_host_deinit(&pcie->pci->pp); 1580ad9b9b6eSManivannan Sadhasivam pcie->suspended = true; 1581ad9b9b6eSManivannan Sadhasivam } 1582ad9b9b6eSManivannan Sadhasivam 1583ad9b9b6eSManivannan Sadhasivam return 0; 1584ad9b9b6eSManivannan Sadhasivam } 1585ad9b9b6eSManivannan Sadhasivam 1586ad9b9b6eSManivannan Sadhasivam static int qcom_pcie_resume_noirq(struct device *dev) 1587ad9b9b6eSManivannan Sadhasivam { 1588ad9b9b6eSManivannan Sadhasivam struct qcom_pcie *pcie = dev_get_drvdata(dev); 1589ad9b9b6eSManivannan Sadhasivam int ret; 1590ad9b9b6eSManivannan Sadhasivam 1591ad9b9b6eSManivannan Sadhasivam if (pcie->suspended) { 1592ad9b9b6eSManivannan Sadhasivam ret = qcom_pcie_host_init(&pcie->pci->pp); 1593ad9b9b6eSManivannan Sadhasivam if (ret) 1594ad9b9b6eSManivannan Sadhasivam return ret; 1595ad9b9b6eSManivannan Sadhasivam 1596ad9b9b6eSManivannan Sadhasivam pcie->suspended = false; 1597ad9b9b6eSManivannan Sadhasivam } 1598ad9b9b6eSManivannan Sadhasivam 1599ad9b9b6eSManivannan Sadhasivam qcom_pcie_icc_update(pcie); 1600ad9b9b6eSManivannan Sadhasivam 1601ad9b9b6eSManivannan Sadhasivam return 0; 1602ad9b9b6eSManivannan Sadhasivam } 1603ad9b9b6eSManivannan Sadhasivam 16046e0832faSShawn Lin static const struct of_device_id qcom_pcie_match[] = { 1605d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, 160622311735SJohan Hovold { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, 1607d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, 1608d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, 160922311735SJohan Hovold { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, 161022311735SJohan Hovold { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, 161122311735SJohan Hovold { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, 1612f3561322SRobert Marko { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, 1613d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, 161422311735SJohan Hovold { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, 161522311735SJohan Hovold { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, 1616d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, 1617d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, 1618d6cbfcd2SJohan Hovold { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, 161922311735SJohan Hovold { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, 16207394d0a8SManivannan Sadhasivam { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, 162122311735SJohan Hovold { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, 162222311735SJohan Hovold { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, 1623720e0d91SDmitry Baryshkov { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, 162422311735SJohan Hovold { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, 162522311735SJohan Hovold { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, 16266276a403SAbel Vesa { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, 16276e0832faSShawn Lin { } 16286e0832faSShawn Lin }; 16296e0832faSShawn Lin 1630322f0343SMarc Gonzalez static void qcom_fixup_class(struct pci_dev *dev) 1631322f0343SMarc Gonzalez { 1632904b10fbSPali Rohár dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 1633322f0343SMarc Gonzalez } 1634604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); 1635604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); 1636604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); 1637604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); 1638604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); 1639604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); 1640604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); 1641322f0343SMarc Gonzalez 1642ad9b9b6eSManivannan Sadhasivam static const struct dev_pm_ops qcom_pcie_pm_ops = { 1643ad9b9b6eSManivannan Sadhasivam NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq) 1644ad9b9b6eSManivannan Sadhasivam }; 1645ad9b9b6eSManivannan Sadhasivam 16466e0832faSShawn Lin static struct platform_driver qcom_pcie_driver = { 16476e0832faSShawn Lin .probe = qcom_pcie_probe, 16486e0832faSShawn Lin .driver = { 16496e0832faSShawn Lin .name = "qcom-pcie", 16506e0832faSShawn Lin .suppress_bind_attrs = true, 16516e0832faSShawn Lin .of_match_table = qcom_pcie_match, 1652ad9b9b6eSManivannan Sadhasivam .pm = &qcom_pcie_pm_ops, 1653c0e1eb44SManivannan Sadhasivam .probe_type = PROBE_PREFER_ASYNCHRONOUS, 16546e0832faSShawn Lin }, 16556e0832faSShawn Lin }; 16566e0832faSShawn Lin builtin_platform_driver(qcom_pcie_driver); 1657