16e0832faSShawn Lin // SPDX-License-Identifier: GPL-2.0 26e0832faSShawn Lin /* 36e0832faSShawn Lin * Qualcomm PCIe root complex driver 46e0832faSShawn Lin * 56e0832faSShawn Lin * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 66e0832faSShawn Lin * Copyright 2015 Linaro Limited. 76e0832faSShawn Lin * 86e0832faSShawn Lin * Author: Stanimir Varbanov <svarbanov@mm-sol.com> 96e0832faSShawn Lin */ 106e0832faSShawn Lin 116e0832faSShawn Lin #include <linux/clk.h> 124c939882SManivannan Sadhasivam #include <linux/crc8.h> 136e0832faSShawn Lin #include <linux/delay.h> 146e0832faSShawn Lin #include <linux/gpio/consumer.h> 156e0832faSShawn Lin #include <linux/interrupt.h> 166e0832faSShawn Lin #include <linux/io.h> 176e0832faSShawn Lin #include <linux/iopoll.h> 186e0832faSShawn Lin #include <linux/kernel.h> 196e0832faSShawn Lin #include <linux/init.h> 206e0832faSShawn Lin #include <linux/of_device.h> 216e0832faSShawn Lin #include <linux/of_gpio.h> 226e0832faSShawn Lin #include <linux/pci.h> 236e0832faSShawn Lin #include <linux/pm_runtime.h> 246e0832faSShawn Lin #include <linux/platform_device.h> 256e0832faSShawn Lin #include <linux/phy/phy.h> 266e0832faSShawn Lin #include <linux/regulator/consumer.h> 276e0832faSShawn Lin #include <linux/reset.h> 286e0832faSShawn Lin #include <linux/slab.h> 296e0832faSShawn Lin #include <linux/types.h> 306e0832faSShawn Lin 3151ed2c2bSSham Muthayyan #include "../../pci.h" 326e0832faSShawn Lin #include "pcie-designware.h" 336e0832faSShawn Lin 346e0832faSShawn Lin #define PCIE20_PARF_SYS_CTRL 0x00 356e0832faSShawn Lin #define MST_WAKEUP_EN BIT(13) 366e0832faSShawn Lin #define SLV_WAKEUP_EN BIT(12) 376e0832faSShawn Lin #define MSTR_ACLK_CGC_DIS BIT(10) 386e0832faSShawn Lin #define SLV_ACLK_CGC_DIS BIT(9) 396e0832faSShawn Lin #define CORE_CLK_CGC_DIS BIT(6) 406e0832faSShawn Lin #define AUX_PWR_DET BIT(4) 416e0832faSShawn Lin #define L23_CLK_RMV_DIS BIT(2) 426e0832faSShawn Lin #define L1_CLK_RMV_DIS BIT(1) 436e0832faSShawn Lin 445147ba8aSKrishna chaitanya chundru #define PCIE20_PARF_PM_CTRL 0x20 455147ba8aSKrishna chaitanya chundru #define REQ_NOT_ENTR_L1 BIT(5) 465147ba8aSKrishna chaitanya chundru 476e0832faSShawn Lin #define PCIE20_PARF_PHY_CTRL 0x40 48de3c4bf6SAnsuel Smith #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) 49de3c4bf6SAnsuel Smith #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) 50de3c4bf6SAnsuel Smith 516e0832faSShawn Lin #define PCIE20_PARF_PHY_REFCLK 0x4C 52de3c4bf6SAnsuel Smith #define PHY_REFCLK_SSP_EN BIT(16) 53de3c4bf6SAnsuel Smith #define PHY_REFCLK_USE_PAD BIT(12) 54de3c4bf6SAnsuel Smith 556e0832faSShawn Lin #define PCIE20_PARF_DBI_BASE_ADDR 0x168 566e0832faSShawn Lin #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C 576e0832faSShawn Lin #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 580cf7c2efSSelvam Sathappan Periakaruppan #define AHB_CLK_EN BIT(0) 590cf7c2efSSelvam Sathappan Periakaruppan #define MSTR_AXI_CLK_EN BIT(1) 600cf7c2efSSelvam Sathappan Periakaruppan #define BYPASS BIT(4) 610cf7c2efSSelvam Sathappan Periakaruppan 626e0832faSShawn Lin #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 636e0832faSShawn Lin #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 646e0832faSShawn Lin #define PCIE20_PARF_LTSSM 0x1B0 656e0832faSShawn Lin #define PCIE20_PARF_SID_OFFSET 0x234 666e0832faSShawn Lin #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C 67ed8cc3b1SBjorn Andersson #define PCIE20_PARF_DEVICE_TYPE 0x1000 684c939882SManivannan Sadhasivam #define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 696e0832faSShawn Lin 706e0832faSShawn Lin #define PCIE20_ELBI_SYS_CTRL 0x04 716e0832faSShawn Lin #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) 726e0832faSShawn Lin 736e0832faSShawn Lin #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 746e0832faSShawn Lin #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 756e0832faSShawn Lin #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 766e0832faSShawn Lin #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c 776e0832faSShawn Lin #define CFG_BRIDGE_SB_INIT BIT(0) 786e0832faSShawn Lin 799a765805SBaruch Siach #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ 809a765805SBaruch Siach 250) 819a765805SBaruch Siach #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \ 829a765805SBaruch Siach 1) 839a765805SBaruch Siach #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ 849a765805SBaruch Siach PCI_EXP_SLTCAP_PCP | \ 859a765805SBaruch Siach PCI_EXP_SLTCAP_MRLSP | \ 869a765805SBaruch Siach PCI_EXP_SLTCAP_AIP | \ 879a765805SBaruch Siach PCI_EXP_SLTCAP_PIP | \ 889a765805SBaruch Siach PCI_EXP_SLTCAP_HPS | \ 899a765805SBaruch Siach PCI_EXP_SLTCAP_HPC | \ 909a765805SBaruch Siach PCI_EXP_SLTCAP_EIP | \ 919a765805SBaruch Siach PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ 929a765805SBaruch Siach PCIE_CAP_SLOT_POWER_LIMIT_SCALE) 936e0832faSShawn Lin 946e0832faSShawn Lin #define PCIE20_PARF_Q2A_FLUSH 0x1AC 956e0832faSShawn Lin 966e0832faSShawn Lin #define PCIE20_MISC_CONTROL_1_REG 0x8BC 976e0832faSShawn Lin #define DBI_RO_WR_EN 1 986e0832faSShawn Lin 996e0832faSShawn Lin #define PERST_DELAY_US 1000 1005149901eSAnsuel Smith /* PARF registers */ 1015149901eSAnsuel Smith #define PCIE20_PARF_PCS_DEEMPH 0x34 1025149901eSAnsuel Smith #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) 1035149901eSAnsuel Smith #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) 1045149901eSAnsuel Smith #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) 1055149901eSAnsuel Smith 1065149901eSAnsuel Smith #define PCIE20_PARF_PCS_SWING 0x38 1075149901eSAnsuel Smith #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) 1085149901eSAnsuel Smith #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) 1095149901eSAnsuel Smith 1105149901eSAnsuel Smith #define PCIE20_PARF_CONFIG_BITS 0x50 1115149901eSAnsuel Smith #define PHY_RX0_EQ(x) ((x) << 24) 1126e0832faSShawn Lin 1136e0832faSShawn Lin #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 1146e0832faSShawn Lin #define SLV_ADDR_SPACE_SZ 0x10000000 1156e0832faSShawn Lin 11651ed2c2bSSham Muthayyan #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 11751ed2c2bSSham Muthayyan 118ed8cc3b1SBjorn Andersson #define DEVICE_TYPE_RC 0x4 119ed8cc3b1SBjorn Andersson 1206e0832faSShawn Lin #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 1216a114526SAnsuel Smith #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 1224c939882SManivannan Sadhasivam 1234c939882SManivannan Sadhasivam #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 1244c939882SManivannan Sadhasivam 1256e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 { 1266a114526SAnsuel Smith struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; 1276e0832faSShawn Lin struct reset_control *pci_reset; 1286e0832faSShawn Lin struct reset_control *axi_reset; 1296e0832faSShawn Lin struct reset_control *ahb_reset; 1306e0832faSShawn Lin struct reset_control *por_reset; 1316e0832faSShawn Lin struct reset_control *phy_reset; 132ee367e2cSAnsuel Smith struct reset_control *ext_reset; 1336e0832faSShawn Lin struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; 1346e0832faSShawn Lin }; 1356e0832faSShawn Lin 1366e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 { 1376e0832faSShawn Lin struct clk *iface; 1386e0832faSShawn Lin struct clk *aux; 1396e0832faSShawn Lin struct clk *master_bus; 1406e0832faSShawn Lin struct clk *slave_bus; 1416e0832faSShawn Lin struct reset_control *core; 1426e0832faSShawn Lin struct regulator *vdda; 1436e0832faSShawn Lin }; 1446e0832faSShawn Lin 1456e0832faSShawn Lin #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 1466e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 { 1476e0832faSShawn Lin struct clk *aux_clk; 1486e0832faSShawn Lin struct clk *master_clk; 1496e0832faSShawn Lin struct clk *slave_clk; 1506e0832faSShawn Lin struct clk *cfg_clk; 1516e0832faSShawn Lin struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; 1526e0832faSShawn Lin }; 1536e0832faSShawn Lin 15467021ae0SBjorn Andersson #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 1556e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 { 1565aa18097SBjorn Andersson struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; 1575aa18097SBjorn Andersson int num_clks; 1586e0832faSShawn Lin struct reset_control *axi_m_reset; 1596e0832faSShawn Lin struct reset_control *axi_s_reset; 1606e0832faSShawn Lin struct reset_control *pipe_reset; 1616e0832faSShawn Lin struct reset_control *axi_m_vmid_reset; 1626e0832faSShawn Lin struct reset_control *axi_s_xpu_reset; 1636e0832faSShawn Lin struct reset_control *parf_reset; 1646e0832faSShawn Lin struct reset_control *phy_reset; 1656e0832faSShawn Lin struct reset_control *axi_m_sticky_reset; 1666e0832faSShawn Lin struct reset_control *pipe_sticky_reset; 1676e0832faSShawn Lin struct reset_control *pwr_reset; 1686e0832faSShawn Lin struct reset_control *ahb_reset; 1696e0832faSShawn Lin struct reset_control *phy_ahb_reset; 1706e0832faSShawn Lin }; 1716e0832faSShawn Lin 1726e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 { 1736e0832faSShawn Lin struct clk *iface; 1746e0832faSShawn Lin struct clk *axi_m_clk; 1756e0832faSShawn Lin struct clk *axi_s_clk; 1766e0832faSShawn Lin struct clk *ahb_clk; 1776e0832faSShawn Lin struct clk *aux_clk; 1786e0832faSShawn Lin struct reset_control *rst[7]; 1796e0832faSShawn Lin }; 1806e0832faSShawn Lin 1817081556fSDmitry Baryshkov /* 6 clocks typically, 7 for sm8250 */ 182ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 { 183*70574511SJohan Hovold struct clk_bulk_data clks[12]; 1847081556fSDmitry Baryshkov int num_clks; 185ed8cc3b1SBjorn Andersson struct regulator_bulk_data supplies[2]; 186ed8cc3b1SBjorn Andersson struct reset_control *pci_reset; 187ed8cc3b1SBjorn Andersson }; 188ed8cc3b1SBjorn Andersson 1890cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 { 1900cf7c2efSSelvam Sathappan Periakaruppan struct clk_bulk_data clks[5]; 1910cf7c2efSSelvam Sathappan Periakaruppan struct reset_control *rst; 1926e0832faSShawn Lin }; 1936e0832faSShawn Lin 1946e0832faSShawn Lin union qcom_pcie_resources { 1956e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 v1_0_0; 1966e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 v2_1_0; 1976e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 v2_3_2; 1986e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 v2_3_3; 1996e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 v2_4_0; 200ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 v2_7_0; 2010cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 v2_9_0; 2026e0832faSShawn Lin }; 2036e0832faSShawn Lin 2046e0832faSShawn Lin struct qcom_pcie; 2056e0832faSShawn Lin 2066e0832faSShawn Lin struct qcom_pcie_ops { 2076e0832faSShawn Lin int (*get_resources)(struct qcom_pcie *pcie); 2086e0832faSShawn Lin int (*init)(struct qcom_pcie *pcie); 2096e0832faSShawn Lin int (*post_init)(struct qcom_pcie *pcie); 2106e0832faSShawn Lin void (*deinit)(struct qcom_pcie *pcie); 2116e0832faSShawn Lin void (*post_deinit)(struct qcom_pcie *pcie); 2126e0832faSShawn Lin void (*ltssm_enable)(struct qcom_pcie *pcie); 2134c939882SManivannan Sadhasivam int (*config_sid)(struct qcom_pcie *pcie); 2146e0832faSShawn Lin }; 2156e0832faSShawn Lin 216b89ff410SPrasad Malisetty struct qcom_pcie_cfg { 217b89ff410SPrasad Malisetty const struct qcom_pcie_ops *ops; 2181c5aa037SDmitry Baryshkov unsigned int has_tbu_clk:1; 2190614f98bSDmitry Baryshkov unsigned int has_ddrss_sf_tbu_clk:1; 2201c5aa037SDmitry Baryshkov unsigned int has_aggre0_clk:1; 2211c5aa037SDmitry Baryshkov unsigned int has_aggre1_clk:1; 222b89ff410SPrasad Malisetty }; 223b89ff410SPrasad Malisetty 2246e0832faSShawn Lin struct qcom_pcie { 2256e0832faSShawn Lin struct dw_pcie *pci; 2266e0832faSShawn Lin void __iomem *parf; /* DT parf */ 2276e0832faSShawn Lin void __iomem *elbi; /* DT elbi */ 2286e0832faSShawn Lin union qcom_pcie_resources res; 2296e0832faSShawn Lin struct phy *phy; 2306e0832faSShawn Lin struct gpio_desc *reset; 231f94c35e0SDmitry Baryshkov const struct qcom_pcie_cfg *cfg; 2326e0832faSShawn Lin }; 2336e0832faSShawn Lin 2346e0832faSShawn Lin #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) 2356e0832faSShawn Lin 2366e0832faSShawn Lin static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 2376e0832faSShawn Lin { 2386e0832faSShawn Lin gpiod_set_value_cansleep(pcie->reset, 1); 2396e0832faSShawn Lin usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 2406e0832faSShawn Lin } 2416e0832faSShawn Lin 2426e0832faSShawn Lin static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) 2436e0832faSShawn Lin { 24464adde31SNiklas Cassel /* Ensure that PERST has been asserted for at least 100 ms */ 24564adde31SNiklas Cassel msleep(100); 2466e0832faSShawn Lin gpiod_set_value_cansleep(pcie->reset, 0); 2476e0832faSShawn Lin usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 2486e0832faSShawn Lin } 2496e0832faSShawn Lin 250886a9c13SRob Herring static int qcom_pcie_start_link(struct dw_pcie *pci) 2516e0832faSShawn Lin { 252886a9c13SRob Herring struct qcom_pcie *pcie = to_qcom_pcie(pci); 2536e0832faSShawn Lin 2546e0832faSShawn Lin /* Enable Link Training state machine */ 255f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->ltssm_enable) 256f94c35e0SDmitry Baryshkov pcie->cfg->ops->ltssm_enable(pcie); 2576e0832faSShawn Lin 258886a9c13SRob Herring return 0; 2596e0832faSShawn Lin } 2606e0832faSShawn Lin 2616e0832faSShawn Lin static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 2626e0832faSShawn Lin { 2636e0832faSShawn Lin u32 val; 2646e0832faSShawn Lin 2656e0832faSShawn Lin /* enable link training */ 2666e0832faSShawn Lin val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); 2676e0832faSShawn Lin val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE; 2686e0832faSShawn Lin writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); 2696e0832faSShawn Lin } 2706e0832faSShawn Lin 2716e0832faSShawn Lin static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 2726e0832faSShawn Lin { 2736e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 2746e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 2756e0832faSShawn Lin struct device *dev = pci->dev; 2766e0832faSShawn Lin int ret; 2776e0832faSShawn Lin 2786e0832faSShawn Lin res->supplies[0].supply = "vdda"; 2796e0832faSShawn Lin res->supplies[1].supply = "vdda_phy"; 2806e0832faSShawn Lin res->supplies[2].supply = "vdda_refclk"; 2816e0832faSShawn Lin ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 2826e0832faSShawn Lin res->supplies); 2836e0832faSShawn Lin if (ret) 2846e0832faSShawn Lin return ret; 2856e0832faSShawn Lin 2866a114526SAnsuel Smith res->clks[0].id = "iface"; 2876a114526SAnsuel Smith res->clks[1].id = "core"; 2886a114526SAnsuel Smith res->clks[2].id = "phy"; 2896a114526SAnsuel Smith res->clks[3].id = "aux"; 2906a114526SAnsuel Smith res->clks[4].id = "ref"; 2916e0832faSShawn Lin 2926a114526SAnsuel Smith /* iface, core, phy are required */ 2936a114526SAnsuel Smith ret = devm_clk_bulk_get(dev, 3, res->clks); 2946a114526SAnsuel Smith if (ret < 0) 2956a114526SAnsuel Smith return ret; 2966e0832faSShawn Lin 2976a114526SAnsuel Smith /* aux, ref are optional */ 2986a114526SAnsuel Smith ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); 2996a114526SAnsuel Smith if (ret < 0) 3006a114526SAnsuel Smith return ret; 3018b6f0330SAnsuel Smith 3026e0832faSShawn Lin res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); 3036e0832faSShawn Lin if (IS_ERR(res->pci_reset)) 3046e0832faSShawn Lin return PTR_ERR(res->pci_reset); 3056e0832faSShawn Lin 3066e0832faSShawn Lin res->axi_reset = devm_reset_control_get_exclusive(dev, "axi"); 3076e0832faSShawn Lin if (IS_ERR(res->axi_reset)) 3086e0832faSShawn Lin return PTR_ERR(res->axi_reset); 3096e0832faSShawn Lin 3106e0832faSShawn Lin res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb"); 3116e0832faSShawn Lin if (IS_ERR(res->ahb_reset)) 3126e0832faSShawn Lin return PTR_ERR(res->ahb_reset); 3136e0832faSShawn Lin 3146e0832faSShawn Lin res->por_reset = devm_reset_control_get_exclusive(dev, "por"); 3156e0832faSShawn Lin if (IS_ERR(res->por_reset)) 3166e0832faSShawn Lin return PTR_ERR(res->por_reset); 3176e0832faSShawn Lin 318ee367e2cSAnsuel Smith res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); 319ee367e2cSAnsuel Smith if (IS_ERR(res->ext_reset)) 320ee367e2cSAnsuel Smith return PTR_ERR(res->ext_reset); 321ee367e2cSAnsuel Smith 3226e0832faSShawn Lin res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); 3236e0832faSShawn Lin return PTR_ERR_OR_ZERO(res->phy_reset); 3246e0832faSShawn Lin } 3256e0832faSShawn Lin 3266e0832faSShawn Lin static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 3276e0832faSShawn Lin { 3286e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 3296e0832faSShawn Lin 3306a114526SAnsuel Smith clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 3316e0832faSShawn Lin reset_control_assert(res->pci_reset); 3326e0832faSShawn Lin reset_control_assert(res->axi_reset); 3336e0832faSShawn Lin reset_control_assert(res->ahb_reset); 3346e0832faSShawn Lin reset_control_assert(res->por_reset); 335ee367e2cSAnsuel Smith reset_control_assert(res->ext_reset); 336dd58318cSAbhishek Sahu reset_control_assert(res->phy_reset); 337d3d4d028SAnsuel Smith 338d3d4d028SAnsuel Smith writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); 339d3d4d028SAnsuel Smith 3406e0832faSShawn Lin regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 3416e0832faSShawn Lin } 3426e0832faSShawn Lin 3436e0832faSShawn Lin static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 3446e0832faSShawn Lin { 3456e0832faSShawn Lin struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 3466e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 3476e0832faSShawn Lin struct device *dev = pci->dev; 3486e0832faSShawn Lin int ret; 3496e0832faSShawn Lin 350d3d4d028SAnsuel Smith /* reset the PCIe interface as uboot can leave it undefined state */ 351d3d4d028SAnsuel Smith reset_control_assert(res->pci_reset); 352d3d4d028SAnsuel Smith reset_control_assert(res->axi_reset); 353d3d4d028SAnsuel Smith reset_control_assert(res->ahb_reset); 354d3d4d028SAnsuel Smith reset_control_assert(res->por_reset); 355d3d4d028SAnsuel Smith reset_control_assert(res->ext_reset); 356d3d4d028SAnsuel Smith reset_control_assert(res->phy_reset); 357d3d4d028SAnsuel Smith 3586e0832faSShawn Lin ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 3596e0832faSShawn Lin if (ret < 0) { 3606e0832faSShawn Lin dev_err(dev, "cannot enable regulators\n"); 3616e0832faSShawn Lin return ret; 3626e0832faSShawn Lin } 3636e0832faSShawn Lin 3646e0832faSShawn Lin ret = reset_control_deassert(res->ahb_reset); 3656e0832faSShawn Lin if (ret) { 3666e0832faSShawn Lin dev_err(dev, "cannot deassert ahb reset\n"); 3676e0832faSShawn Lin goto err_deassert_ahb; 3686e0832faSShawn Lin } 3696e0832faSShawn Lin 370ee367e2cSAnsuel Smith ret = reset_control_deassert(res->ext_reset); 371ee367e2cSAnsuel Smith if (ret) { 372ee367e2cSAnsuel Smith dev_err(dev, "cannot deassert ext reset\n"); 3736a114526SAnsuel Smith goto err_deassert_ext; 374ee367e2cSAnsuel Smith } 375ee367e2cSAnsuel Smith 3766a114526SAnsuel Smith ret = reset_control_deassert(res->phy_reset); 3776a114526SAnsuel Smith if (ret) { 3786a114526SAnsuel Smith dev_err(dev, "cannot deassert phy reset\n"); 3796a114526SAnsuel Smith goto err_deassert_phy; 3806a114526SAnsuel Smith } 3816a114526SAnsuel Smith 3826a114526SAnsuel Smith ret = reset_control_deassert(res->pci_reset); 3836a114526SAnsuel Smith if (ret) { 3846a114526SAnsuel Smith dev_err(dev, "cannot deassert pci reset\n"); 3856a114526SAnsuel Smith goto err_deassert_pci; 3866a114526SAnsuel Smith } 3876a114526SAnsuel Smith 3886a114526SAnsuel Smith ret = reset_control_deassert(res->por_reset); 3896a114526SAnsuel Smith if (ret) { 3906a114526SAnsuel Smith dev_err(dev, "cannot deassert por reset\n"); 3916a114526SAnsuel Smith goto err_deassert_por; 3926a114526SAnsuel Smith } 3936a114526SAnsuel Smith 3946a114526SAnsuel Smith ret = reset_control_deassert(res->axi_reset); 3956a114526SAnsuel Smith if (ret) { 3966a114526SAnsuel Smith dev_err(dev, "cannot deassert axi reset\n"); 3976a114526SAnsuel Smith goto err_deassert_axi; 3986a114526SAnsuel Smith } 3996a114526SAnsuel Smith 40036d9018dSRobert Marko return 0; 40136d9018dSRobert Marko 40236d9018dSRobert Marko err_deassert_axi: 40336d9018dSRobert Marko reset_control_assert(res->por_reset); 40436d9018dSRobert Marko err_deassert_por: 40536d9018dSRobert Marko reset_control_assert(res->pci_reset); 40636d9018dSRobert Marko err_deassert_pci: 40736d9018dSRobert Marko reset_control_assert(res->phy_reset); 40836d9018dSRobert Marko err_deassert_phy: 40936d9018dSRobert Marko reset_control_assert(res->ext_reset); 41036d9018dSRobert Marko err_deassert_ext: 41136d9018dSRobert Marko reset_control_assert(res->ahb_reset); 41236d9018dSRobert Marko err_deassert_ahb: 41336d9018dSRobert Marko regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 41436d9018dSRobert Marko 41536d9018dSRobert Marko return ret; 41636d9018dSRobert Marko } 41736d9018dSRobert Marko 41836d9018dSRobert Marko static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) 41936d9018dSRobert Marko { 42036d9018dSRobert Marko struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 42136d9018dSRobert Marko struct dw_pcie *pci = pcie->pci; 42236d9018dSRobert Marko struct device *dev = pci->dev; 42336d9018dSRobert Marko struct device_node *node = dev->of_node; 42436d9018dSRobert Marko u32 val; 42536d9018dSRobert Marko int ret; 4266a114526SAnsuel Smith 4276e0832faSShawn Lin /* enable PCIe clocks and resets */ 4286e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 4296e0832faSShawn Lin val &= ~BIT(0); 4306e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 4316e0832faSShawn Lin 43238f897aeSChristian Marangi ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 43338f897aeSChristian Marangi if (ret) 43436d9018dSRobert Marko return ret; 43538f897aeSChristian Marangi 4368df093feSAnsuel Smith if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || 4378df093feSAnsuel Smith of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { 4385149901eSAnsuel Smith writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | 4395149901eSAnsuel Smith PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | 4405149901eSAnsuel Smith PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), 4415149901eSAnsuel Smith pcie->parf + PCIE20_PARF_PCS_DEEMPH); 4425149901eSAnsuel Smith writel(PCS_SWING_TX_SWING_FULL(120) | 4435149901eSAnsuel Smith PCS_SWING_TX_SWING_LOW(120), 4445149901eSAnsuel Smith pcie->parf + PCIE20_PARF_PCS_SWING); 4455149901eSAnsuel Smith writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); 4465149901eSAnsuel Smith } 4475149901eSAnsuel Smith 448de3c4bf6SAnsuel Smith if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { 449de3c4bf6SAnsuel Smith /* set TX termination offset */ 450de3c4bf6SAnsuel Smith val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 451de3c4bf6SAnsuel Smith val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; 452de3c4bf6SAnsuel Smith val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); 453de3c4bf6SAnsuel Smith writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 454de3c4bf6SAnsuel Smith } 455de3c4bf6SAnsuel Smith 4566e0832faSShawn Lin /* enable external reference clock */ 4576e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); 4582cfef197SAnsuel Smith /* USE_PAD is required only for ipq806x */ 4592cfef197SAnsuel Smith if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) 460de3c4bf6SAnsuel Smith val &= ~PHY_REFCLK_USE_PAD; 461de3c4bf6SAnsuel Smith val |= PHY_REFCLK_SSP_EN; 4626e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); 4636e0832faSShawn Lin 4646e0832faSShawn Lin /* wait for clock acquisition */ 4656e0832faSShawn Lin usleep_range(1000, 1500); 4666e0832faSShawn Lin 4676e0832faSShawn Lin /* Set the Max TLP size to 2K, instead of using default of 4K */ 4686e0832faSShawn Lin writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, 4696e0832faSShawn Lin pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); 4706e0832faSShawn Lin writel(CFG_BRIDGE_SB_INIT, 4716e0832faSShawn Lin pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); 4726e0832faSShawn Lin 4736e0832faSShawn Lin return 0; 4746e0832faSShawn Lin } 4756e0832faSShawn Lin 4766e0832faSShawn Lin static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) 4776e0832faSShawn Lin { 4786e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 4796e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 4806e0832faSShawn Lin struct device *dev = pci->dev; 4816e0832faSShawn Lin 4826e0832faSShawn Lin res->vdda = devm_regulator_get(dev, "vdda"); 4836e0832faSShawn Lin if (IS_ERR(res->vdda)) 4846e0832faSShawn Lin return PTR_ERR(res->vdda); 4856e0832faSShawn Lin 4866e0832faSShawn Lin res->iface = devm_clk_get(dev, "iface"); 4876e0832faSShawn Lin if (IS_ERR(res->iface)) 4886e0832faSShawn Lin return PTR_ERR(res->iface); 4896e0832faSShawn Lin 4906e0832faSShawn Lin res->aux = devm_clk_get(dev, "aux"); 4916e0832faSShawn Lin if (IS_ERR(res->aux)) 4926e0832faSShawn Lin return PTR_ERR(res->aux); 4936e0832faSShawn Lin 4946e0832faSShawn Lin res->master_bus = devm_clk_get(dev, "master_bus"); 4956e0832faSShawn Lin if (IS_ERR(res->master_bus)) 4966e0832faSShawn Lin return PTR_ERR(res->master_bus); 4976e0832faSShawn Lin 4986e0832faSShawn Lin res->slave_bus = devm_clk_get(dev, "slave_bus"); 4996e0832faSShawn Lin if (IS_ERR(res->slave_bus)) 5006e0832faSShawn Lin return PTR_ERR(res->slave_bus); 5016e0832faSShawn Lin 5026e0832faSShawn Lin res->core = devm_reset_control_get_exclusive(dev, "core"); 5036e0832faSShawn Lin return PTR_ERR_OR_ZERO(res->core); 5046e0832faSShawn Lin } 5056e0832faSShawn Lin 5066e0832faSShawn Lin static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) 5076e0832faSShawn Lin { 5086e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 5096e0832faSShawn Lin 5106e0832faSShawn Lin reset_control_assert(res->core); 5116e0832faSShawn Lin clk_disable_unprepare(res->slave_bus); 5126e0832faSShawn Lin clk_disable_unprepare(res->master_bus); 5136e0832faSShawn Lin clk_disable_unprepare(res->iface); 5146e0832faSShawn Lin clk_disable_unprepare(res->aux); 5156e0832faSShawn Lin regulator_disable(res->vdda); 5166e0832faSShawn Lin } 5176e0832faSShawn Lin 5186e0832faSShawn Lin static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) 5196e0832faSShawn Lin { 5206e0832faSShawn Lin struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 5216e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 5226e0832faSShawn Lin struct device *dev = pci->dev; 5236e0832faSShawn Lin int ret; 5246e0832faSShawn Lin 5256e0832faSShawn Lin ret = reset_control_deassert(res->core); 5266e0832faSShawn Lin if (ret) { 5276e0832faSShawn Lin dev_err(dev, "cannot deassert core reset\n"); 5286e0832faSShawn Lin return ret; 5296e0832faSShawn Lin } 5306e0832faSShawn Lin 5316e0832faSShawn Lin ret = clk_prepare_enable(res->aux); 5326e0832faSShawn Lin if (ret) { 5336e0832faSShawn Lin dev_err(dev, "cannot prepare/enable aux clock\n"); 5346e0832faSShawn Lin goto err_res; 5356e0832faSShawn Lin } 5366e0832faSShawn Lin 5376e0832faSShawn Lin ret = clk_prepare_enable(res->iface); 5386e0832faSShawn Lin if (ret) { 5396e0832faSShawn Lin dev_err(dev, "cannot prepare/enable iface clock\n"); 5406e0832faSShawn Lin goto err_aux; 5416e0832faSShawn Lin } 5426e0832faSShawn Lin 5436e0832faSShawn Lin ret = clk_prepare_enable(res->master_bus); 5446e0832faSShawn Lin if (ret) { 5456e0832faSShawn Lin dev_err(dev, "cannot prepare/enable master_bus clock\n"); 5466e0832faSShawn Lin goto err_iface; 5476e0832faSShawn Lin } 5486e0832faSShawn Lin 5496e0832faSShawn Lin ret = clk_prepare_enable(res->slave_bus); 5506e0832faSShawn Lin if (ret) { 5516e0832faSShawn Lin dev_err(dev, "cannot prepare/enable slave_bus clock\n"); 5526e0832faSShawn Lin goto err_master; 5536e0832faSShawn Lin } 5546e0832faSShawn Lin 5556e0832faSShawn Lin ret = regulator_enable(res->vdda); 5566e0832faSShawn Lin if (ret) { 5576e0832faSShawn Lin dev_err(dev, "cannot enable vdda regulator\n"); 5586e0832faSShawn Lin goto err_slave; 5596e0832faSShawn Lin } 5606e0832faSShawn Lin 5616e0832faSShawn Lin return 0; 5626e0832faSShawn Lin err_slave: 5636e0832faSShawn Lin clk_disable_unprepare(res->slave_bus); 5646e0832faSShawn Lin err_master: 5656e0832faSShawn Lin clk_disable_unprepare(res->master_bus); 5666e0832faSShawn Lin err_iface: 5676e0832faSShawn Lin clk_disable_unprepare(res->iface); 5686e0832faSShawn Lin err_aux: 5696e0832faSShawn Lin clk_disable_unprepare(res->aux); 5706e0832faSShawn Lin err_res: 5716e0832faSShawn Lin reset_control_assert(res->core); 5726e0832faSShawn Lin 5736e0832faSShawn Lin return ret; 5746e0832faSShawn Lin } 5756e0832faSShawn Lin 57636d9018dSRobert Marko static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 57736d9018dSRobert Marko { 57836d9018dSRobert Marko /* change DBI base address */ 57936d9018dSRobert Marko writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 58036d9018dSRobert Marko 58136d9018dSRobert Marko if (IS_ENABLED(CONFIG_PCI_MSI)) { 58236d9018dSRobert Marko u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); 58336d9018dSRobert Marko 58436d9018dSRobert Marko val |= BIT(31); 58536d9018dSRobert Marko writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); 58636d9018dSRobert Marko } 58736d9018dSRobert Marko 58836d9018dSRobert Marko return 0; 58936d9018dSRobert Marko } 59036d9018dSRobert Marko 5916e0832faSShawn Lin static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) 5926e0832faSShawn Lin { 5936e0832faSShawn Lin u32 val; 5946e0832faSShawn Lin 5956e0832faSShawn Lin /* enable link training */ 5966e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_LTSSM); 5976e0832faSShawn Lin val |= BIT(8); 5986e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_LTSSM); 5996e0832faSShawn Lin } 6006e0832faSShawn Lin 6016e0832faSShawn Lin static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 6026e0832faSShawn Lin { 6036e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 6046e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 6056e0832faSShawn Lin struct device *dev = pci->dev; 6066e0832faSShawn Lin int ret; 6076e0832faSShawn Lin 6086e0832faSShawn Lin res->supplies[0].supply = "vdda"; 6096e0832faSShawn Lin res->supplies[1].supply = "vddpe-3v3"; 6106e0832faSShawn Lin ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 6116e0832faSShawn Lin res->supplies); 6126e0832faSShawn Lin if (ret) 6136e0832faSShawn Lin return ret; 6146e0832faSShawn Lin 6156e0832faSShawn Lin res->aux_clk = devm_clk_get(dev, "aux"); 6166e0832faSShawn Lin if (IS_ERR(res->aux_clk)) 6176e0832faSShawn Lin return PTR_ERR(res->aux_clk); 6186e0832faSShawn Lin 6196e0832faSShawn Lin res->cfg_clk = devm_clk_get(dev, "cfg"); 6206e0832faSShawn Lin if (IS_ERR(res->cfg_clk)) 6216e0832faSShawn Lin return PTR_ERR(res->cfg_clk); 6226e0832faSShawn Lin 6236e0832faSShawn Lin res->master_clk = devm_clk_get(dev, "bus_master"); 6246e0832faSShawn Lin if (IS_ERR(res->master_clk)) 6256e0832faSShawn Lin return PTR_ERR(res->master_clk); 6266e0832faSShawn Lin 6276e0832faSShawn Lin res->slave_clk = devm_clk_get(dev, "bus_slave"); 6286e0832faSShawn Lin if (IS_ERR(res->slave_clk)) 6296e0832faSShawn Lin return PTR_ERR(res->slave_clk); 6306e0832faSShawn Lin 631affac98aSDmitry Baryshkov return 0; 6326e0832faSShawn Lin } 6336e0832faSShawn Lin 6346e0832faSShawn Lin static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 6356e0832faSShawn Lin { 6366e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 6376e0832faSShawn Lin 6386e0832faSShawn Lin clk_disable_unprepare(res->slave_clk); 6396e0832faSShawn Lin clk_disable_unprepare(res->master_clk); 6406e0832faSShawn Lin clk_disable_unprepare(res->cfg_clk); 6416e0832faSShawn Lin clk_disable_unprepare(res->aux_clk); 6426e0832faSShawn Lin 6436e0832faSShawn Lin regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 6446e0832faSShawn Lin } 6456e0832faSShawn Lin 6466e0832faSShawn Lin static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 6476e0832faSShawn Lin { 6486e0832faSShawn Lin struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 6496e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 6506e0832faSShawn Lin struct device *dev = pci->dev; 6516e0832faSShawn Lin int ret; 6526e0832faSShawn Lin 6536e0832faSShawn Lin ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 6546e0832faSShawn Lin if (ret < 0) { 6556e0832faSShawn Lin dev_err(dev, "cannot enable regulators\n"); 6566e0832faSShawn Lin return ret; 6576e0832faSShawn Lin } 6586e0832faSShawn Lin 6596e0832faSShawn Lin ret = clk_prepare_enable(res->aux_clk); 6606e0832faSShawn Lin if (ret) { 6616e0832faSShawn Lin dev_err(dev, "cannot prepare/enable aux clock\n"); 6626e0832faSShawn Lin goto err_aux_clk; 6636e0832faSShawn Lin } 6646e0832faSShawn Lin 6656e0832faSShawn Lin ret = clk_prepare_enable(res->cfg_clk); 6666e0832faSShawn Lin if (ret) { 6676e0832faSShawn Lin dev_err(dev, "cannot prepare/enable cfg clock\n"); 6686e0832faSShawn Lin goto err_cfg_clk; 6696e0832faSShawn Lin } 6706e0832faSShawn Lin 6716e0832faSShawn Lin ret = clk_prepare_enable(res->master_clk); 6726e0832faSShawn Lin if (ret) { 6736e0832faSShawn Lin dev_err(dev, "cannot prepare/enable master clock\n"); 6746e0832faSShawn Lin goto err_master_clk; 6756e0832faSShawn Lin } 6766e0832faSShawn Lin 6776e0832faSShawn Lin ret = clk_prepare_enable(res->slave_clk); 6786e0832faSShawn Lin if (ret) { 6796e0832faSShawn Lin dev_err(dev, "cannot prepare/enable slave clock\n"); 6806e0832faSShawn Lin goto err_slave_clk; 6816e0832faSShawn Lin } 6826e0832faSShawn Lin 6836e0832faSShawn Lin return 0; 6846e0832faSShawn Lin 6856e0832faSShawn Lin err_slave_clk: 6866e0832faSShawn Lin clk_disable_unprepare(res->master_clk); 6876e0832faSShawn Lin err_master_clk: 6886e0832faSShawn Lin clk_disable_unprepare(res->cfg_clk); 6896e0832faSShawn Lin err_cfg_clk: 6906e0832faSShawn Lin clk_disable_unprepare(res->aux_clk); 6916e0832faSShawn Lin 6926e0832faSShawn Lin err_aux_clk: 6936e0832faSShawn Lin regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 6946e0832faSShawn Lin 6956e0832faSShawn Lin return ret; 6966e0832faSShawn Lin } 6976e0832faSShawn Lin 6986e0832faSShawn Lin static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 6996e0832faSShawn Lin { 70036d9018dSRobert Marko u32 val; 7016e0832faSShawn Lin 7026e0832faSShawn Lin /* enable PCIe clocks and resets */ 7036e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 7046e0832faSShawn Lin val &= ~BIT(0); 7056e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 7066e0832faSShawn Lin 7076e0832faSShawn Lin /* change DBI base address */ 7086e0832faSShawn Lin writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 7096e0832faSShawn Lin 7106e0832faSShawn Lin /* MAC PHY_POWERDOWN MUX DISABLE */ 7116e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); 7126e0832faSShawn Lin val &= ~BIT(29); 7136e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); 7146e0832faSShawn Lin 7156e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 7166e0832faSShawn Lin val |= BIT(4); 7176e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 7186e0832faSShawn Lin 7196e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 7206e0832faSShawn Lin val |= BIT(31); 7216e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 7226e0832faSShawn Lin 7236e0832faSShawn Lin return 0; 7246e0832faSShawn Lin } 7256e0832faSShawn Lin 7266e0832faSShawn Lin static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) 7276e0832faSShawn Lin { 7286e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 7296e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 7306e0832faSShawn Lin struct device *dev = pci->dev; 73167021ae0SBjorn Andersson bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); 7325aa18097SBjorn Andersson int ret; 7336e0832faSShawn Lin 7345aa18097SBjorn Andersson res->clks[0].id = "aux"; 7355aa18097SBjorn Andersson res->clks[1].id = "master_bus"; 7365aa18097SBjorn Andersson res->clks[2].id = "slave_bus"; 73767021ae0SBjorn Andersson res->clks[3].id = "iface"; 7386e0832faSShawn Lin 73967021ae0SBjorn Andersson /* qcom,pcie-ipq4019 is defined without "iface" */ 74067021ae0SBjorn Andersson res->num_clks = is_ipq ? 3 : 4; 7416e0832faSShawn Lin 7425aa18097SBjorn Andersson ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); 7435aa18097SBjorn Andersson if (ret < 0) 7445aa18097SBjorn Andersson return ret; 7456e0832faSShawn Lin 7466e0832faSShawn Lin res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m"); 7476e0832faSShawn Lin if (IS_ERR(res->axi_m_reset)) 7486e0832faSShawn Lin return PTR_ERR(res->axi_m_reset); 7496e0832faSShawn Lin 7506e0832faSShawn Lin res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s"); 7516e0832faSShawn Lin if (IS_ERR(res->axi_s_reset)) 7526e0832faSShawn Lin return PTR_ERR(res->axi_s_reset); 7536e0832faSShawn Lin 75467021ae0SBjorn Andersson if (is_ipq) { 75567021ae0SBjorn Andersson /* 75667021ae0SBjorn Andersson * These resources relates to the PHY or are secure clocks, but 75767021ae0SBjorn Andersson * are controlled here for IPQ4019 75867021ae0SBjorn Andersson */ 7596e0832faSShawn Lin res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); 7606e0832faSShawn Lin if (IS_ERR(res->pipe_reset)) 7616e0832faSShawn Lin return PTR_ERR(res->pipe_reset); 7626e0832faSShawn Lin 7636e0832faSShawn Lin res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, 7646e0832faSShawn Lin "axi_m_vmid"); 7656e0832faSShawn Lin if (IS_ERR(res->axi_m_vmid_reset)) 7666e0832faSShawn Lin return PTR_ERR(res->axi_m_vmid_reset); 7676e0832faSShawn Lin 7686e0832faSShawn Lin res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, 7696e0832faSShawn Lin "axi_s_xpu"); 7706e0832faSShawn Lin if (IS_ERR(res->axi_s_xpu_reset)) 7716e0832faSShawn Lin return PTR_ERR(res->axi_s_xpu_reset); 7726e0832faSShawn Lin 7736e0832faSShawn Lin res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); 7746e0832faSShawn Lin if (IS_ERR(res->parf_reset)) 7756e0832faSShawn Lin return PTR_ERR(res->parf_reset); 7766e0832faSShawn Lin 7776e0832faSShawn Lin res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); 7786e0832faSShawn Lin if (IS_ERR(res->phy_reset)) 7796e0832faSShawn Lin return PTR_ERR(res->phy_reset); 78067021ae0SBjorn Andersson } 7816e0832faSShawn Lin 7826e0832faSShawn Lin res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev, 7836e0832faSShawn Lin "axi_m_sticky"); 7846e0832faSShawn Lin if (IS_ERR(res->axi_m_sticky_reset)) 7856e0832faSShawn Lin return PTR_ERR(res->axi_m_sticky_reset); 7866e0832faSShawn Lin 7876e0832faSShawn Lin res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev, 7886e0832faSShawn Lin "pipe_sticky"); 7896e0832faSShawn Lin if (IS_ERR(res->pipe_sticky_reset)) 7906e0832faSShawn Lin return PTR_ERR(res->pipe_sticky_reset); 7916e0832faSShawn Lin 7926e0832faSShawn Lin res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr"); 7936e0832faSShawn Lin if (IS_ERR(res->pwr_reset)) 7946e0832faSShawn Lin return PTR_ERR(res->pwr_reset); 7956e0832faSShawn Lin 7966e0832faSShawn Lin res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb"); 7976e0832faSShawn Lin if (IS_ERR(res->ahb_reset)) 7986e0832faSShawn Lin return PTR_ERR(res->ahb_reset); 7996e0832faSShawn Lin 80067021ae0SBjorn Andersson if (is_ipq) { 8016e0832faSShawn Lin res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); 8026e0832faSShawn Lin if (IS_ERR(res->phy_ahb_reset)) 8036e0832faSShawn Lin return PTR_ERR(res->phy_ahb_reset); 80467021ae0SBjorn Andersson } 8056e0832faSShawn Lin 8066e0832faSShawn Lin return 0; 8076e0832faSShawn Lin } 8086e0832faSShawn Lin 8096e0832faSShawn Lin static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) 8106e0832faSShawn Lin { 8116e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 8126e0832faSShawn Lin 8136e0832faSShawn Lin reset_control_assert(res->axi_m_reset); 8146e0832faSShawn Lin reset_control_assert(res->axi_s_reset); 8156e0832faSShawn Lin reset_control_assert(res->pipe_reset); 8166e0832faSShawn Lin reset_control_assert(res->pipe_sticky_reset); 8176e0832faSShawn Lin reset_control_assert(res->phy_reset); 8186e0832faSShawn Lin reset_control_assert(res->phy_ahb_reset); 8196e0832faSShawn Lin reset_control_assert(res->axi_m_sticky_reset); 8206e0832faSShawn Lin reset_control_assert(res->pwr_reset); 8216e0832faSShawn Lin reset_control_assert(res->ahb_reset); 8225aa18097SBjorn Andersson clk_bulk_disable_unprepare(res->num_clks, res->clks); 8236e0832faSShawn Lin } 8246e0832faSShawn Lin 8256e0832faSShawn Lin static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 8266e0832faSShawn Lin { 8276e0832faSShawn Lin struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 8286e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 8296e0832faSShawn Lin struct device *dev = pci->dev; 8306e0832faSShawn Lin int ret; 8316e0832faSShawn Lin 8326e0832faSShawn Lin ret = reset_control_assert(res->axi_m_reset); 8336e0832faSShawn Lin if (ret) { 8346e0832faSShawn Lin dev_err(dev, "cannot assert axi master reset\n"); 8356e0832faSShawn Lin return ret; 8366e0832faSShawn Lin } 8376e0832faSShawn Lin 8386e0832faSShawn Lin ret = reset_control_assert(res->axi_s_reset); 8396e0832faSShawn Lin if (ret) { 8406e0832faSShawn Lin dev_err(dev, "cannot assert axi slave reset\n"); 8416e0832faSShawn Lin return ret; 8426e0832faSShawn Lin } 8436e0832faSShawn Lin 8446e0832faSShawn Lin usleep_range(10000, 12000); 8456e0832faSShawn Lin 8466e0832faSShawn Lin ret = reset_control_assert(res->pipe_reset); 8476e0832faSShawn Lin if (ret) { 8486e0832faSShawn Lin dev_err(dev, "cannot assert pipe reset\n"); 8496e0832faSShawn Lin return ret; 8506e0832faSShawn Lin } 8516e0832faSShawn Lin 8526e0832faSShawn Lin ret = reset_control_assert(res->pipe_sticky_reset); 8536e0832faSShawn Lin if (ret) { 8546e0832faSShawn Lin dev_err(dev, "cannot assert pipe sticky reset\n"); 8556e0832faSShawn Lin return ret; 8566e0832faSShawn Lin } 8576e0832faSShawn Lin 8586e0832faSShawn Lin ret = reset_control_assert(res->phy_reset); 8596e0832faSShawn Lin if (ret) { 8606e0832faSShawn Lin dev_err(dev, "cannot assert phy reset\n"); 8616e0832faSShawn Lin return ret; 8626e0832faSShawn Lin } 8636e0832faSShawn Lin 8646e0832faSShawn Lin ret = reset_control_assert(res->phy_ahb_reset); 8656e0832faSShawn Lin if (ret) { 8666e0832faSShawn Lin dev_err(dev, "cannot assert phy ahb reset\n"); 8676e0832faSShawn Lin return ret; 8686e0832faSShawn Lin } 8696e0832faSShawn Lin 8706e0832faSShawn Lin usleep_range(10000, 12000); 8716e0832faSShawn Lin 8726e0832faSShawn Lin ret = reset_control_assert(res->axi_m_sticky_reset); 8736e0832faSShawn Lin if (ret) { 8746e0832faSShawn Lin dev_err(dev, "cannot assert axi master sticky reset\n"); 8756e0832faSShawn Lin return ret; 8766e0832faSShawn Lin } 8776e0832faSShawn Lin 8786e0832faSShawn Lin ret = reset_control_assert(res->pwr_reset); 8796e0832faSShawn Lin if (ret) { 8806e0832faSShawn Lin dev_err(dev, "cannot assert power reset\n"); 8816e0832faSShawn Lin return ret; 8826e0832faSShawn Lin } 8836e0832faSShawn Lin 8846e0832faSShawn Lin ret = reset_control_assert(res->ahb_reset); 8856e0832faSShawn Lin if (ret) { 8866e0832faSShawn Lin dev_err(dev, "cannot assert ahb reset\n"); 8876e0832faSShawn Lin return ret; 8886e0832faSShawn Lin } 8896e0832faSShawn Lin 8906e0832faSShawn Lin usleep_range(10000, 12000); 8916e0832faSShawn Lin 8926e0832faSShawn Lin ret = reset_control_deassert(res->phy_ahb_reset); 8936e0832faSShawn Lin if (ret) { 8946e0832faSShawn Lin dev_err(dev, "cannot deassert phy ahb reset\n"); 8956e0832faSShawn Lin return ret; 8966e0832faSShawn Lin } 8976e0832faSShawn Lin 8986e0832faSShawn Lin ret = reset_control_deassert(res->phy_reset); 8996e0832faSShawn Lin if (ret) { 9006e0832faSShawn Lin dev_err(dev, "cannot deassert phy reset\n"); 9016e0832faSShawn Lin goto err_rst_phy; 9026e0832faSShawn Lin } 9036e0832faSShawn Lin 9046e0832faSShawn Lin ret = reset_control_deassert(res->pipe_reset); 9056e0832faSShawn Lin if (ret) { 9066e0832faSShawn Lin dev_err(dev, "cannot deassert pipe reset\n"); 9076e0832faSShawn Lin goto err_rst_pipe; 9086e0832faSShawn Lin } 9096e0832faSShawn Lin 9106e0832faSShawn Lin ret = reset_control_deassert(res->pipe_sticky_reset); 9116e0832faSShawn Lin if (ret) { 9126e0832faSShawn Lin dev_err(dev, "cannot deassert pipe sticky reset\n"); 9136e0832faSShawn Lin goto err_rst_pipe_sticky; 9146e0832faSShawn Lin } 9156e0832faSShawn Lin 9166e0832faSShawn Lin usleep_range(10000, 12000); 9176e0832faSShawn Lin 9186e0832faSShawn Lin ret = reset_control_deassert(res->axi_m_reset); 9196e0832faSShawn Lin if (ret) { 9206e0832faSShawn Lin dev_err(dev, "cannot deassert axi master reset\n"); 9216e0832faSShawn Lin goto err_rst_axi_m; 9226e0832faSShawn Lin } 9236e0832faSShawn Lin 9246e0832faSShawn Lin ret = reset_control_deassert(res->axi_m_sticky_reset); 9256e0832faSShawn Lin if (ret) { 9266e0832faSShawn Lin dev_err(dev, "cannot deassert axi master sticky reset\n"); 9276e0832faSShawn Lin goto err_rst_axi_m_sticky; 9286e0832faSShawn Lin } 9296e0832faSShawn Lin 9306e0832faSShawn Lin ret = reset_control_deassert(res->axi_s_reset); 9316e0832faSShawn Lin if (ret) { 9326e0832faSShawn Lin dev_err(dev, "cannot deassert axi slave reset\n"); 9336e0832faSShawn Lin goto err_rst_axi_s; 9346e0832faSShawn Lin } 9356e0832faSShawn Lin 9366e0832faSShawn Lin ret = reset_control_deassert(res->pwr_reset); 9376e0832faSShawn Lin if (ret) { 9386e0832faSShawn Lin dev_err(dev, "cannot deassert power reset\n"); 9396e0832faSShawn Lin goto err_rst_pwr; 9406e0832faSShawn Lin } 9416e0832faSShawn Lin 9426e0832faSShawn Lin ret = reset_control_deassert(res->ahb_reset); 9436e0832faSShawn Lin if (ret) { 9446e0832faSShawn Lin dev_err(dev, "cannot deassert ahb reset\n"); 9456e0832faSShawn Lin goto err_rst_ahb; 9466e0832faSShawn Lin } 9476e0832faSShawn Lin 9486e0832faSShawn Lin usleep_range(10000, 12000); 9496e0832faSShawn Lin 9505aa18097SBjorn Andersson ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 9515aa18097SBjorn Andersson if (ret) 9525aa18097SBjorn Andersson goto err_clks; 9536e0832faSShawn Lin 95436d9018dSRobert Marko return 0; 95536d9018dSRobert Marko 95636d9018dSRobert Marko err_clks: 95736d9018dSRobert Marko reset_control_assert(res->ahb_reset); 95836d9018dSRobert Marko err_rst_ahb: 95936d9018dSRobert Marko reset_control_assert(res->pwr_reset); 96036d9018dSRobert Marko err_rst_pwr: 96136d9018dSRobert Marko reset_control_assert(res->axi_s_reset); 96236d9018dSRobert Marko err_rst_axi_s: 96336d9018dSRobert Marko reset_control_assert(res->axi_m_sticky_reset); 96436d9018dSRobert Marko err_rst_axi_m_sticky: 96536d9018dSRobert Marko reset_control_assert(res->axi_m_reset); 96636d9018dSRobert Marko err_rst_axi_m: 96736d9018dSRobert Marko reset_control_assert(res->pipe_sticky_reset); 96836d9018dSRobert Marko err_rst_pipe_sticky: 96936d9018dSRobert Marko reset_control_assert(res->pipe_reset); 97036d9018dSRobert Marko err_rst_pipe: 97136d9018dSRobert Marko reset_control_assert(res->phy_reset); 97236d9018dSRobert Marko err_rst_phy: 97336d9018dSRobert Marko reset_control_assert(res->phy_ahb_reset); 97436d9018dSRobert Marko return ret; 97536d9018dSRobert Marko } 97636d9018dSRobert Marko 97736d9018dSRobert Marko static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) 97836d9018dSRobert Marko { 97936d9018dSRobert Marko u32 val; 98036d9018dSRobert Marko 9816e0832faSShawn Lin /* enable PCIe clocks and resets */ 9826e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 9836e0832faSShawn Lin val &= ~BIT(0); 9846e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 9856e0832faSShawn Lin 9866e0832faSShawn Lin /* change DBI base address */ 9876e0832faSShawn Lin writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 9886e0832faSShawn Lin 9896e0832faSShawn Lin /* MAC PHY_POWERDOWN MUX DISABLE */ 9906e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); 9916e0832faSShawn Lin val &= ~BIT(29); 9926e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); 9936e0832faSShawn Lin 9946e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 9956e0832faSShawn Lin val |= BIT(4); 9966e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 9976e0832faSShawn Lin 9986e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 9996e0832faSShawn Lin val |= BIT(31); 10006e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 10016e0832faSShawn Lin 10026e0832faSShawn Lin return 0; 10036e0832faSShawn Lin } 10046e0832faSShawn Lin 10056e0832faSShawn Lin static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) 10066e0832faSShawn Lin { 10076e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 10086e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 10096e0832faSShawn Lin struct device *dev = pci->dev; 10106e0832faSShawn Lin int i; 10116e0832faSShawn Lin const char *rst_names[] = { "axi_m", "axi_s", "pipe", 10126e0832faSShawn Lin "axi_m_sticky", "sticky", 10136e0832faSShawn Lin "ahb", "sleep", }; 10146e0832faSShawn Lin 10156e0832faSShawn Lin res->iface = devm_clk_get(dev, "iface"); 10166e0832faSShawn Lin if (IS_ERR(res->iface)) 10176e0832faSShawn Lin return PTR_ERR(res->iface); 10186e0832faSShawn Lin 10196e0832faSShawn Lin res->axi_m_clk = devm_clk_get(dev, "axi_m"); 10206e0832faSShawn Lin if (IS_ERR(res->axi_m_clk)) 10216e0832faSShawn Lin return PTR_ERR(res->axi_m_clk); 10226e0832faSShawn Lin 10236e0832faSShawn Lin res->axi_s_clk = devm_clk_get(dev, "axi_s"); 10246e0832faSShawn Lin if (IS_ERR(res->axi_s_clk)) 10256e0832faSShawn Lin return PTR_ERR(res->axi_s_clk); 10266e0832faSShawn Lin 10276e0832faSShawn Lin res->ahb_clk = devm_clk_get(dev, "ahb"); 10286e0832faSShawn Lin if (IS_ERR(res->ahb_clk)) 10296e0832faSShawn Lin return PTR_ERR(res->ahb_clk); 10306e0832faSShawn Lin 10316e0832faSShawn Lin res->aux_clk = devm_clk_get(dev, "aux"); 10326e0832faSShawn Lin if (IS_ERR(res->aux_clk)) 10336e0832faSShawn Lin return PTR_ERR(res->aux_clk); 10346e0832faSShawn Lin 10356e0832faSShawn Lin for (i = 0; i < ARRAY_SIZE(rst_names); i++) { 10366e0832faSShawn Lin res->rst[i] = devm_reset_control_get(dev, rst_names[i]); 10376e0832faSShawn Lin if (IS_ERR(res->rst[i])) 10386e0832faSShawn Lin return PTR_ERR(res->rst[i]); 10396e0832faSShawn Lin } 10406e0832faSShawn Lin 10416e0832faSShawn Lin return 0; 10426e0832faSShawn Lin } 10436e0832faSShawn Lin 10446e0832faSShawn Lin static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) 10456e0832faSShawn Lin { 10466e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 10476e0832faSShawn Lin 10486e0832faSShawn Lin clk_disable_unprepare(res->iface); 10496e0832faSShawn Lin clk_disable_unprepare(res->axi_m_clk); 10506e0832faSShawn Lin clk_disable_unprepare(res->axi_s_clk); 10516e0832faSShawn Lin clk_disable_unprepare(res->ahb_clk); 10526e0832faSShawn Lin clk_disable_unprepare(res->aux_clk); 10536e0832faSShawn Lin } 10546e0832faSShawn Lin 10556e0832faSShawn Lin static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) 10566e0832faSShawn Lin { 10576e0832faSShawn Lin struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 10586e0832faSShawn Lin struct dw_pcie *pci = pcie->pci; 10596e0832faSShawn Lin struct device *dev = pci->dev; 10606e0832faSShawn Lin int i, ret; 10616e0832faSShawn Lin 10626e0832faSShawn Lin for (i = 0; i < ARRAY_SIZE(res->rst); i++) { 10636e0832faSShawn Lin ret = reset_control_assert(res->rst[i]); 10646e0832faSShawn Lin if (ret) { 10656e0832faSShawn Lin dev_err(dev, "reset #%d assert failed (%d)\n", i, ret); 10666e0832faSShawn Lin return ret; 10676e0832faSShawn Lin } 10686e0832faSShawn Lin } 10696e0832faSShawn Lin 10706e0832faSShawn Lin usleep_range(2000, 2500); 10716e0832faSShawn Lin 10726e0832faSShawn Lin for (i = 0; i < ARRAY_SIZE(res->rst); i++) { 10736e0832faSShawn Lin ret = reset_control_deassert(res->rst[i]); 10746e0832faSShawn Lin if (ret) { 10756e0832faSShawn Lin dev_err(dev, "reset #%d deassert failed (%d)\n", i, 10766e0832faSShawn Lin ret); 10776e0832faSShawn Lin return ret; 10786e0832faSShawn Lin } 10796e0832faSShawn Lin } 10806e0832faSShawn Lin 10816e0832faSShawn Lin /* 10826e0832faSShawn Lin * Don't have a way to see if the reset has completed. 10836e0832faSShawn Lin * Wait for some time. 10846e0832faSShawn Lin */ 10856e0832faSShawn Lin usleep_range(2000, 2500); 10866e0832faSShawn Lin 10876e0832faSShawn Lin ret = clk_prepare_enable(res->iface); 10886e0832faSShawn Lin if (ret) { 10896e0832faSShawn Lin dev_err(dev, "cannot prepare/enable core clock\n"); 10906e0832faSShawn Lin goto err_clk_iface; 10916e0832faSShawn Lin } 10926e0832faSShawn Lin 10936e0832faSShawn Lin ret = clk_prepare_enable(res->axi_m_clk); 10946e0832faSShawn Lin if (ret) { 10956e0832faSShawn Lin dev_err(dev, "cannot prepare/enable core clock\n"); 10966e0832faSShawn Lin goto err_clk_axi_m; 10976e0832faSShawn Lin } 10986e0832faSShawn Lin 10996e0832faSShawn Lin ret = clk_prepare_enable(res->axi_s_clk); 11006e0832faSShawn Lin if (ret) { 11016e0832faSShawn Lin dev_err(dev, "cannot prepare/enable axi slave clock\n"); 11026e0832faSShawn Lin goto err_clk_axi_s; 11036e0832faSShawn Lin } 11046e0832faSShawn Lin 11056e0832faSShawn Lin ret = clk_prepare_enable(res->ahb_clk); 11066e0832faSShawn Lin if (ret) { 11076e0832faSShawn Lin dev_err(dev, "cannot prepare/enable ahb clock\n"); 11086e0832faSShawn Lin goto err_clk_ahb; 11096e0832faSShawn Lin } 11106e0832faSShawn Lin 11116e0832faSShawn Lin ret = clk_prepare_enable(res->aux_clk); 11126e0832faSShawn Lin if (ret) { 11136e0832faSShawn Lin dev_err(dev, "cannot prepare/enable aux clock\n"); 11146e0832faSShawn Lin goto err_clk_aux; 11156e0832faSShawn Lin } 11166e0832faSShawn Lin 11176e0832faSShawn Lin return 0; 11186e0832faSShawn Lin 11196e0832faSShawn Lin err_clk_aux: 11206e0832faSShawn Lin clk_disable_unprepare(res->ahb_clk); 11216e0832faSShawn Lin err_clk_ahb: 11226e0832faSShawn Lin clk_disable_unprepare(res->axi_s_clk); 11236e0832faSShawn Lin err_clk_axi_s: 11246e0832faSShawn Lin clk_disable_unprepare(res->axi_m_clk); 11256e0832faSShawn Lin err_clk_axi_m: 11266e0832faSShawn Lin clk_disable_unprepare(res->iface); 11276e0832faSShawn Lin err_clk_iface: 11286e0832faSShawn Lin /* 11296e0832faSShawn Lin * Not checking for failure, will anyway return 11306e0832faSShawn Lin * the original failure in 'ret'. 11316e0832faSShawn Lin */ 11326e0832faSShawn Lin for (i = 0; i < ARRAY_SIZE(res->rst); i++) 11336e0832faSShawn Lin reset_control_assert(res->rst[i]); 11346e0832faSShawn Lin 11356e0832faSShawn Lin return ret; 11366e0832faSShawn Lin } 11376e0832faSShawn Lin 1138a0e43bb9SRobert Marko static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 1139a0e43bb9SRobert Marko { 1140a0e43bb9SRobert Marko struct dw_pcie *pci = pcie->pci; 1141a0e43bb9SRobert Marko u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1142a0e43bb9SRobert Marko u32 val; 1143a0e43bb9SRobert Marko 11446e0832faSShawn Lin writel(SLV_ADDR_SPACE_SZ, 11456e0832faSShawn Lin pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); 11466e0832faSShawn Lin 11476e0832faSShawn Lin val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 11486e0832faSShawn Lin val &= ~BIT(0); 11496e0832faSShawn Lin writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 11506e0832faSShawn Lin 11516e0832faSShawn Lin writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 11526e0832faSShawn Lin 11536e0832faSShawn Lin writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 11546e0832faSShawn Lin | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 11556e0832faSShawn Lin AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 11566e0832faSShawn Lin pcie->parf + PCIE20_PARF_SYS_CTRL); 11576e0832faSShawn Lin writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); 11586e0832faSShawn Lin 11596e0832faSShawn Lin writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); 11606e0832faSShawn Lin writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); 11619a765805SBaruch Siach writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 11626e0832faSShawn Lin 11636e0832faSShawn Lin val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 11646e0832faSShawn Lin val &= ~PCI_EXP_LNKCAP_ASPMS; 11656e0832faSShawn Lin writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 11666e0832faSShawn Lin 11676e0832faSShawn Lin writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 11686e0832faSShawn Lin PCI_EXP_DEVCTL2); 11696e0832faSShawn Lin 11706e0832faSShawn Lin return 0; 11716e0832faSShawn Lin } 11726e0832faSShawn Lin 1173ed8cc3b1SBjorn Andersson static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 1174ed8cc3b1SBjorn Andersson { 1175ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 1176ed8cc3b1SBjorn Andersson struct dw_pcie *pci = pcie->pci; 1177ed8cc3b1SBjorn Andersson struct device *dev = pci->dev; 1178*70574511SJohan Hovold unsigned int num_clks, num_opt_clks; 11791c5aa037SDmitry Baryshkov unsigned int idx; 1180ed8cc3b1SBjorn Andersson int ret; 1181ed8cc3b1SBjorn Andersson 1182ed8cc3b1SBjorn Andersson res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); 1183ed8cc3b1SBjorn Andersson if (IS_ERR(res->pci_reset)) 1184ed8cc3b1SBjorn Andersson return PTR_ERR(res->pci_reset); 1185ed8cc3b1SBjorn Andersson 1186ed8cc3b1SBjorn Andersson res->supplies[0].supply = "vdda"; 1187ed8cc3b1SBjorn Andersson res->supplies[1].supply = "vddpe-3v3"; 1188ed8cc3b1SBjorn Andersson ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 1189ed8cc3b1SBjorn Andersson res->supplies); 1190ed8cc3b1SBjorn Andersson if (ret) 1191ed8cc3b1SBjorn Andersson return ret; 1192ed8cc3b1SBjorn Andersson 11931c5aa037SDmitry Baryshkov idx = 0; 11941c5aa037SDmitry Baryshkov res->clks[idx++].id = "aux"; 11951c5aa037SDmitry Baryshkov res->clks[idx++].id = "cfg"; 11961c5aa037SDmitry Baryshkov res->clks[idx++].id = "bus_master"; 11971c5aa037SDmitry Baryshkov res->clks[idx++].id = "bus_slave"; 11981c5aa037SDmitry Baryshkov res->clks[idx++].id = "slave_q2a"; 11991c5aa037SDmitry Baryshkov if (pcie->cfg->has_tbu_clk) 12001c5aa037SDmitry Baryshkov res->clks[idx++].id = "tbu"; 12011c5aa037SDmitry Baryshkov if (pcie->cfg->has_ddrss_sf_tbu_clk) 12021c5aa037SDmitry Baryshkov res->clks[idx++].id = "ddrss_sf_tbu"; 12031c5aa037SDmitry Baryshkov if (pcie->cfg->has_aggre0_clk) 12041c5aa037SDmitry Baryshkov res->clks[idx++].id = "aggre0"; 12051c5aa037SDmitry Baryshkov if (pcie->cfg->has_aggre1_clk) 12061c5aa037SDmitry Baryshkov res->clks[idx++].id = "aggre1"; 12071c5aa037SDmitry Baryshkov 1208*70574511SJohan Hovold num_clks = idx; 1209*70574511SJohan Hovold 1210*70574511SJohan Hovold ret = devm_clk_bulk_get(dev, num_clks, res->clks); 1211*70574511SJohan Hovold if (ret < 0) 1212*70574511SJohan Hovold return ret; 1213*70574511SJohan Hovold 1214*70574511SJohan Hovold res->clks[idx++].id = "noc_aggr_4"; 1215*70574511SJohan Hovold res->clks[idx++].id = "noc_aggr_south_sf"; 1216*70574511SJohan Hovold res->clks[idx++].id = "cnoc_qx"; 1217*70574511SJohan Hovold 1218*70574511SJohan Hovold num_opt_clks = idx - num_clks; 12191c5aa037SDmitry Baryshkov res->num_clks = idx; 1220ed8cc3b1SBjorn Andersson 1221*70574511SJohan Hovold ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); 1222ed8cc3b1SBjorn Andersson if (ret < 0) 1223ed8cc3b1SBjorn Andersson return ret; 1224ed8cc3b1SBjorn Andersson 1225affac98aSDmitry Baryshkov return 0; 1226ed8cc3b1SBjorn Andersson } 1227ed8cc3b1SBjorn Andersson 1228ed8cc3b1SBjorn Andersson static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 1229ed8cc3b1SBjorn Andersson { 1230ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 1231ed8cc3b1SBjorn Andersson struct dw_pcie *pci = pcie->pci; 1232ed8cc3b1SBjorn Andersson struct device *dev = pci->dev; 1233ed8cc3b1SBjorn Andersson u32 val; 1234ed8cc3b1SBjorn Andersson int ret; 1235ed8cc3b1SBjorn Andersson 1236ed8cc3b1SBjorn Andersson ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 1237ed8cc3b1SBjorn Andersson if (ret < 0) { 1238ed8cc3b1SBjorn Andersson dev_err(dev, "cannot enable regulators\n"); 1239ed8cc3b1SBjorn Andersson return ret; 1240ed8cc3b1SBjorn Andersson } 1241ed8cc3b1SBjorn Andersson 12427081556fSDmitry Baryshkov ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 1243ed8cc3b1SBjorn Andersson if (ret < 0) 1244ed8cc3b1SBjorn Andersson goto err_disable_regulators; 1245ed8cc3b1SBjorn Andersson 1246ed8cc3b1SBjorn Andersson ret = reset_control_assert(res->pci_reset); 1247ed8cc3b1SBjorn Andersson if (ret < 0) { 1248ed8cc3b1SBjorn Andersson dev_err(dev, "cannot deassert pci reset\n"); 1249ed8cc3b1SBjorn Andersson goto err_disable_clocks; 1250ed8cc3b1SBjorn Andersson } 1251ed8cc3b1SBjorn Andersson 1252ed8cc3b1SBjorn Andersson usleep_range(1000, 1500); 1253ed8cc3b1SBjorn Andersson 1254ed8cc3b1SBjorn Andersson ret = reset_control_deassert(res->pci_reset); 1255ed8cc3b1SBjorn Andersson if (ret < 0) { 1256ed8cc3b1SBjorn Andersson dev_err(dev, "cannot deassert pci reset\n"); 1257ed8cc3b1SBjorn Andersson goto err_disable_clocks; 1258ed8cc3b1SBjorn Andersson } 1259ed8cc3b1SBjorn Andersson 12601c5aa037SDmitry Baryshkov /* Wait for reset to complete, required on SM8450 */ 12611c5aa037SDmitry Baryshkov usleep_range(1000, 1500); 12621c5aa037SDmitry Baryshkov 1263ed8cc3b1SBjorn Andersson /* configure PCIe to RC mode */ 1264ed8cc3b1SBjorn Andersson writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); 1265ed8cc3b1SBjorn Andersson 1266ed8cc3b1SBjorn Andersson /* enable PCIe clocks and resets */ 1267ed8cc3b1SBjorn Andersson val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 1268ed8cc3b1SBjorn Andersson val &= ~BIT(0); 1269ed8cc3b1SBjorn Andersson writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 1270ed8cc3b1SBjorn Andersson 1271ed8cc3b1SBjorn Andersson /* change DBI base address */ 1272ed8cc3b1SBjorn Andersson writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 1273ed8cc3b1SBjorn Andersson 1274ed8cc3b1SBjorn Andersson /* MAC PHY_POWERDOWN MUX DISABLE */ 1275ed8cc3b1SBjorn Andersson val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); 1276ed8cc3b1SBjorn Andersson val &= ~BIT(29); 1277ed8cc3b1SBjorn Andersson writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); 1278ed8cc3b1SBjorn Andersson 1279ed8cc3b1SBjorn Andersson val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 1280ed8cc3b1SBjorn Andersson val |= BIT(4); 1281ed8cc3b1SBjorn Andersson writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 1282ed8cc3b1SBjorn Andersson 12835147ba8aSKrishna chaitanya chundru /* Enable L1 and L1SS */ 12845147ba8aSKrishna chaitanya chundru val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); 12855147ba8aSKrishna chaitanya chundru val &= ~REQ_NOT_ENTR_L1; 12865147ba8aSKrishna chaitanya chundru writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); 12875147ba8aSKrishna chaitanya chundru 1288ed8cc3b1SBjorn Andersson if (IS_ENABLED(CONFIG_PCI_MSI)) { 1289ed8cc3b1SBjorn Andersson val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); 1290ed8cc3b1SBjorn Andersson val |= BIT(31); 1291ed8cc3b1SBjorn Andersson writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); 1292ed8cc3b1SBjorn Andersson } 1293ed8cc3b1SBjorn Andersson 1294ed8cc3b1SBjorn Andersson return 0; 1295ed8cc3b1SBjorn Andersson err_disable_clocks: 12967081556fSDmitry Baryshkov clk_bulk_disable_unprepare(res->num_clks, res->clks); 1297ed8cc3b1SBjorn Andersson err_disable_regulators: 1298ed8cc3b1SBjorn Andersson regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1299ed8cc3b1SBjorn Andersson 1300ed8cc3b1SBjorn Andersson return ret; 1301ed8cc3b1SBjorn Andersson } 1302ed8cc3b1SBjorn Andersson 1303ed8cc3b1SBjorn Andersson static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) 1304ed8cc3b1SBjorn Andersson { 1305ed8cc3b1SBjorn Andersson struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 1306ed8cc3b1SBjorn Andersson 13077081556fSDmitry Baryshkov clk_bulk_disable_unprepare(res->num_clks, res->clks); 13087eb5768cSDmitry Baryshkov 1309ed8cc3b1SBjorn Andersson regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1310ed8cc3b1SBjorn Andersson } 1311ed8cc3b1SBjorn Andersson 13120cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) 1313ed8cc3b1SBjorn Andersson { 13140cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 13150cf7c2efSSelvam Sathappan Periakaruppan struct dw_pcie *pci = pcie->pci; 13160cf7c2efSSelvam Sathappan Periakaruppan struct device *dev = pci->dev; 13170cf7c2efSSelvam Sathappan Periakaruppan int ret; 1318ed8cc3b1SBjorn Andersson 13190cf7c2efSSelvam Sathappan Periakaruppan res->clks[0].id = "iface"; 13200cf7c2efSSelvam Sathappan Periakaruppan res->clks[1].id = "axi_m"; 13210cf7c2efSSelvam Sathappan Periakaruppan res->clks[2].id = "axi_s"; 13220cf7c2efSSelvam Sathappan Periakaruppan res->clks[3].id = "axi_bridge"; 13230cf7c2efSSelvam Sathappan Periakaruppan res->clks[4].id = "rchng"; 1324aa9c0df9SPrasad Malisetty 13250cf7c2efSSelvam Sathappan Periakaruppan ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 13260cf7c2efSSelvam Sathappan Periakaruppan if (ret < 0) 13270cf7c2efSSelvam Sathappan Periakaruppan return ret; 13280cf7c2efSSelvam Sathappan Periakaruppan 13290cf7c2efSSelvam Sathappan Periakaruppan res->rst = devm_reset_control_array_get_exclusive(dev); 13300cf7c2efSSelvam Sathappan Periakaruppan if (IS_ERR(res->rst)) 13310cf7c2efSSelvam Sathappan Periakaruppan return PTR_ERR(res->rst); 13320cf7c2efSSelvam Sathappan Periakaruppan 13330cf7c2efSSelvam Sathappan Periakaruppan return 0; 1334ed8cc3b1SBjorn Andersson } 1335ed8cc3b1SBjorn Andersson 13360cf7c2efSSelvam Sathappan Periakaruppan static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) 1337ed8cc3b1SBjorn Andersson { 13380cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1339ed8cc3b1SBjorn Andersson 13400cf7c2efSSelvam Sathappan Periakaruppan clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 13410cf7c2efSSelvam Sathappan Periakaruppan } 13420cf7c2efSSelvam Sathappan Periakaruppan 13430cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) 13440cf7c2efSSelvam Sathappan Periakaruppan { 13450cf7c2efSSelvam Sathappan Periakaruppan struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 13460cf7c2efSSelvam Sathappan Periakaruppan struct device *dev = pcie->pci->dev; 13470cf7c2efSSelvam Sathappan Periakaruppan int ret; 13480cf7c2efSSelvam Sathappan Periakaruppan 13490cf7c2efSSelvam Sathappan Periakaruppan ret = reset_control_assert(res->rst); 13500cf7c2efSSelvam Sathappan Periakaruppan if (ret) { 13510cf7c2efSSelvam Sathappan Periakaruppan dev_err(dev, "reset assert failed (%d)\n", ret); 13520cf7c2efSSelvam Sathappan Periakaruppan return ret; 13530cf7c2efSSelvam Sathappan Periakaruppan } 13540cf7c2efSSelvam Sathappan Periakaruppan 13550cf7c2efSSelvam Sathappan Periakaruppan /* 13560cf7c2efSSelvam Sathappan Periakaruppan * Delay periods before and after reset deassert are working values 13570cf7c2efSSelvam Sathappan Periakaruppan * from downstream Codeaurora kernel 13580cf7c2efSSelvam Sathappan Periakaruppan */ 13590cf7c2efSSelvam Sathappan Periakaruppan usleep_range(2000, 2500); 13600cf7c2efSSelvam Sathappan Periakaruppan 13610cf7c2efSSelvam Sathappan Periakaruppan ret = reset_control_deassert(res->rst); 13620cf7c2efSSelvam Sathappan Periakaruppan if (ret) { 13630cf7c2efSSelvam Sathappan Periakaruppan dev_err(dev, "reset deassert failed (%d)\n", ret); 13640cf7c2efSSelvam Sathappan Periakaruppan return ret; 13650cf7c2efSSelvam Sathappan Periakaruppan } 13660cf7c2efSSelvam Sathappan Periakaruppan 13670cf7c2efSSelvam Sathappan Periakaruppan usleep_range(2000, 2500); 13680cf7c2efSSelvam Sathappan Periakaruppan 13690cf7c2efSSelvam Sathappan Periakaruppan return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 13700cf7c2efSSelvam Sathappan Periakaruppan } 13710cf7c2efSSelvam Sathappan Periakaruppan 13720cf7c2efSSelvam Sathappan Periakaruppan static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) 13730cf7c2efSSelvam Sathappan Periakaruppan { 13740cf7c2efSSelvam Sathappan Periakaruppan struct dw_pcie *pci = pcie->pci; 13750cf7c2efSSelvam Sathappan Periakaruppan u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 13760cf7c2efSSelvam Sathappan Periakaruppan u32 val; 13770cf7c2efSSelvam Sathappan Periakaruppan int i; 13780cf7c2efSSelvam Sathappan Periakaruppan 13790cf7c2efSSelvam Sathappan Periakaruppan writel(SLV_ADDR_SPACE_SZ, 13800cf7c2efSSelvam Sathappan Periakaruppan pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); 13810cf7c2efSSelvam Sathappan Periakaruppan 13820cf7c2efSSelvam Sathappan Periakaruppan val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 13830cf7c2efSSelvam Sathappan Periakaruppan val &= ~BIT(0); 13840cf7c2efSSelvam Sathappan Periakaruppan writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 13850cf7c2efSSelvam Sathappan Periakaruppan 13860cf7c2efSSelvam Sathappan Periakaruppan writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 13870cf7c2efSSelvam Sathappan Periakaruppan 13880cf7c2efSSelvam Sathappan Periakaruppan writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); 13890cf7c2efSSelvam Sathappan Periakaruppan writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, 13900cf7c2efSSelvam Sathappan Periakaruppan pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 13910cf7c2efSSelvam Sathappan Periakaruppan writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | 13920cf7c2efSSelvam Sathappan Periakaruppan GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 13930cf7c2efSSelvam Sathappan Periakaruppan pci->dbi_base + GEN3_RELATED_OFF); 13940cf7c2efSSelvam Sathappan Periakaruppan 13950cf7c2efSSelvam Sathappan Periakaruppan writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | 13960cf7c2efSSelvam Sathappan Periakaruppan SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 13970cf7c2efSSelvam Sathappan Periakaruppan AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 13980cf7c2efSSelvam Sathappan Periakaruppan pcie->parf + PCIE20_PARF_SYS_CTRL); 13990cf7c2efSSelvam Sathappan Periakaruppan 14000cf7c2efSSelvam Sathappan Periakaruppan writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); 14010cf7c2efSSelvam Sathappan Periakaruppan 14020cf7c2efSSelvam Sathappan Periakaruppan dw_pcie_dbi_ro_wr_en(pci); 14030cf7c2efSSelvam Sathappan Periakaruppan writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 14040cf7c2efSSelvam Sathappan Periakaruppan 14050cf7c2efSSelvam Sathappan Periakaruppan val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 14060cf7c2efSSelvam Sathappan Periakaruppan val &= ~PCI_EXP_LNKCAP_ASPMS; 14070cf7c2efSSelvam Sathappan Periakaruppan writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 14080cf7c2efSSelvam Sathappan Periakaruppan 14090cf7c2efSSelvam Sathappan Periakaruppan writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 14100cf7c2efSSelvam Sathappan Periakaruppan PCI_EXP_DEVCTL2); 14110cf7c2efSSelvam Sathappan Periakaruppan 14120cf7c2efSSelvam Sathappan Periakaruppan for (i = 0; i < 256; i++) 14130cf7c2efSSelvam Sathappan Periakaruppan writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i)); 14140cf7c2efSSelvam Sathappan Periakaruppan 14150cf7c2efSSelvam Sathappan Periakaruppan return 0; 1416ed8cc3b1SBjorn Andersson } 1417ed8cc3b1SBjorn Andersson 14186e0832faSShawn Lin static int qcom_pcie_link_up(struct dw_pcie *pci) 14196e0832faSShawn Lin { 14207b87ddc0SRob Herring u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 14217b87ddc0SRob Herring u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 14226e0832faSShawn Lin 14236e0832faSShawn Lin return !!(val & PCI_EXP_LNKSTA_DLLLA); 14246e0832faSShawn Lin } 14256e0832faSShawn Lin 14264c939882SManivannan Sadhasivam static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) 14274c939882SManivannan Sadhasivam { 14284c939882SManivannan Sadhasivam /* iommu map structure */ 14294c939882SManivannan Sadhasivam struct { 14304c939882SManivannan Sadhasivam u32 bdf; 14314c939882SManivannan Sadhasivam u32 phandle; 14324c939882SManivannan Sadhasivam u32 smmu_sid; 14334c939882SManivannan Sadhasivam u32 smmu_sid_len; 14344c939882SManivannan Sadhasivam } *map; 14354c939882SManivannan Sadhasivam void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N; 14364c939882SManivannan Sadhasivam struct device *dev = pcie->pci->dev; 14374c939882SManivannan Sadhasivam u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 14384c939882SManivannan Sadhasivam int i, nr_map, size = 0; 14394c939882SManivannan Sadhasivam u32 smmu_sid_base; 14404c939882SManivannan Sadhasivam 14414c939882SManivannan Sadhasivam of_get_property(dev->of_node, "iommu-map", &size); 14424c939882SManivannan Sadhasivam if (!size) 14434c939882SManivannan Sadhasivam return 0; 14444c939882SManivannan Sadhasivam 14454c939882SManivannan Sadhasivam map = kzalloc(size, GFP_KERNEL); 14464c939882SManivannan Sadhasivam if (!map) 14474c939882SManivannan Sadhasivam return -ENOMEM; 14484c939882SManivannan Sadhasivam 14494c939882SManivannan Sadhasivam of_property_read_u32_array(dev->of_node, 14504c939882SManivannan Sadhasivam "iommu-map", (u32 *)map, size / sizeof(u32)); 14514c939882SManivannan Sadhasivam 14524c939882SManivannan Sadhasivam nr_map = size / (sizeof(*map)); 14534c939882SManivannan Sadhasivam 14544c939882SManivannan Sadhasivam crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 14554c939882SManivannan Sadhasivam 14564c939882SManivannan Sadhasivam /* Registers need to be zero out first */ 14574c939882SManivannan Sadhasivam memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 14584c939882SManivannan Sadhasivam 14594c939882SManivannan Sadhasivam /* Extract the SMMU SID base from the first entry of iommu-map */ 14604c939882SManivannan Sadhasivam smmu_sid_base = map[0].smmu_sid; 14614c939882SManivannan Sadhasivam 14624c939882SManivannan Sadhasivam /* Look for an available entry to hold the mapping */ 14634c939882SManivannan Sadhasivam for (i = 0; i < nr_map; i++) { 14643f13d611SManivannan Sadhasivam __be16 bdf_be = cpu_to_be16(map[i].bdf); 14654c939882SManivannan Sadhasivam u32 val; 14664c939882SManivannan Sadhasivam u8 hash; 14674c939882SManivannan Sadhasivam 14684c939882SManivannan Sadhasivam hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 14694c939882SManivannan Sadhasivam 0); 14704c939882SManivannan Sadhasivam 14714c939882SManivannan Sadhasivam val = readl(bdf_to_sid_base + hash * sizeof(u32)); 14724c939882SManivannan Sadhasivam 14734c939882SManivannan Sadhasivam /* If the register is already populated, look for next available entry */ 14744c939882SManivannan Sadhasivam while (val) { 14754c939882SManivannan Sadhasivam u8 current_hash = hash++; 14764c939882SManivannan Sadhasivam u8 next_mask = 0xff; 14774c939882SManivannan Sadhasivam 14784c939882SManivannan Sadhasivam /* If NEXT field is NULL then update it with next hash */ 14794c939882SManivannan Sadhasivam if (!(val & next_mask)) { 14804c939882SManivannan Sadhasivam val |= (u32)hash; 14814c939882SManivannan Sadhasivam writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 14824c939882SManivannan Sadhasivam } 14834c939882SManivannan Sadhasivam 14844c939882SManivannan Sadhasivam val = readl(bdf_to_sid_base + hash * sizeof(u32)); 14854c939882SManivannan Sadhasivam } 14864c939882SManivannan Sadhasivam 14874c939882SManivannan Sadhasivam /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 14884c939882SManivannan Sadhasivam val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 14894c939882SManivannan Sadhasivam writel(val, bdf_to_sid_base + hash * sizeof(u32)); 14904c939882SManivannan Sadhasivam } 14914c939882SManivannan Sadhasivam 14924c939882SManivannan Sadhasivam kfree(map); 14934c939882SManivannan Sadhasivam 14944c939882SManivannan Sadhasivam return 0; 14954c939882SManivannan Sadhasivam } 14964c939882SManivannan Sadhasivam 149760b3c27fSSerge Semin static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 14986e0832faSShawn Lin { 14996e0832faSShawn Lin struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 15006e0832faSShawn Lin struct qcom_pcie *pcie = to_qcom_pcie(pci); 15016e0832faSShawn Lin int ret; 15026e0832faSShawn Lin 15036e0832faSShawn Lin qcom_ep_reset_assert(pcie); 15046e0832faSShawn Lin 1505f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->init(pcie); 15066e0832faSShawn Lin if (ret) 15076e0832faSShawn Lin return ret; 15086e0832faSShawn Lin 15096e0832faSShawn Lin ret = phy_power_on(pcie->phy); 15106e0832faSShawn Lin if (ret) 15116e0832faSShawn Lin goto err_deinit; 15126e0832faSShawn Lin 1513f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->post_init) { 1514f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->post_init(pcie); 15156e0832faSShawn Lin if (ret) 15166e0832faSShawn Lin goto err_disable_phy; 15176e0832faSShawn Lin } 15186e0832faSShawn Lin 15196e0832faSShawn Lin qcom_ep_reset_deassert(pcie); 15206e0832faSShawn Lin 1521f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->config_sid) { 1522f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->config_sid(pcie); 15234c939882SManivannan Sadhasivam if (ret) 15244c939882SManivannan Sadhasivam goto err; 15254c939882SManivannan Sadhasivam } 15264c939882SManivannan Sadhasivam 15276e0832faSShawn Lin return 0; 1528886a9c13SRob Herring 15294c939882SManivannan Sadhasivam err: 15304c939882SManivannan Sadhasivam qcom_ep_reset_assert(pcie); 1531f94c35e0SDmitry Baryshkov if (pcie->cfg->ops->post_deinit) 1532f94c35e0SDmitry Baryshkov pcie->cfg->ops->post_deinit(pcie); 15336e0832faSShawn Lin err_disable_phy: 15346e0832faSShawn Lin phy_power_off(pcie->phy); 15356e0832faSShawn Lin err_deinit: 1536f94c35e0SDmitry Baryshkov pcie->cfg->ops->deinit(pcie); 15376e0832faSShawn Lin 15386e0832faSShawn Lin return ret; 15396e0832faSShawn Lin } 15406e0832faSShawn Lin 15416e0832faSShawn Lin static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 15426e0832faSShawn Lin .host_init = qcom_pcie_host_init, 15436e0832faSShawn Lin }; 15446e0832faSShawn Lin 15456e0832faSShawn Lin /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ 15466e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_1_0 = { 15476e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_1_0, 15486e0832faSShawn Lin .init = qcom_pcie_init_2_1_0, 154936d9018dSRobert Marko .post_init = qcom_pcie_post_init_2_1_0, 15506e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_1_0, 15516e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 15526e0832faSShawn Lin }; 15536e0832faSShawn Lin 15546e0832faSShawn Lin /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ 15556e0832faSShawn Lin static const struct qcom_pcie_ops ops_1_0_0 = { 15566e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_1_0_0, 15576e0832faSShawn Lin .init = qcom_pcie_init_1_0_0, 155836d9018dSRobert Marko .post_init = qcom_pcie_post_init_1_0_0, 15596e0832faSShawn Lin .deinit = qcom_pcie_deinit_1_0_0, 15606e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 15616e0832faSShawn Lin }; 15626e0832faSShawn Lin 15636e0832faSShawn Lin /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ 15646e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_3_2 = { 15656e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_3_2, 15666e0832faSShawn Lin .init = qcom_pcie_init_2_3_2, 15676e0832faSShawn Lin .post_init = qcom_pcie_post_init_2_3_2, 15686e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_3_2, 15696e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 15706e0832faSShawn Lin }; 15716e0832faSShawn Lin 15726e0832faSShawn Lin /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */ 15736e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_4_0 = { 15746e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_4_0, 15756e0832faSShawn Lin .init = qcom_pcie_init_2_4_0, 157636d9018dSRobert Marko .post_init = qcom_pcie_post_init_2_4_0, 15776e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_4_0, 15786e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 15796e0832faSShawn Lin }; 15806e0832faSShawn Lin 15816e0832faSShawn Lin /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */ 15826e0832faSShawn Lin static const struct qcom_pcie_ops ops_2_3_3 = { 15836e0832faSShawn Lin .get_resources = qcom_pcie_get_resources_2_3_3, 15846e0832faSShawn Lin .init = qcom_pcie_init_2_3_3, 1585a0e43bb9SRobert Marko .post_init = qcom_pcie_post_init_2_3_3, 15866e0832faSShawn Lin .deinit = qcom_pcie_deinit_2_3_3, 15876e0832faSShawn Lin .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 15886e0832faSShawn Lin }; 15896e0832faSShawn Lin 1590ed8cc3b1SBjorn Andersson /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ 1591ed8cc3b1SBjorn Andersson static const struct qcom_pcie_ops ops_2_7_0 = { 1592ed8cc3b1SBjorn Andersson .get_resources = qcom_pcie_get_resources_2_7_0, 1593ed8cc3b1SBjorn Andersson .init = qcom_pcie_init_2_7_0, 1594ed8cc3b1SBjorn Andersson .deinit = qcom_pcie_deinit_2_7_0, 1595ed8cc3b1SBjorn Andersson .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1596ed8cc3b1SBjorn Andersson }; 1597ed8cc3b1SBjorn Andersson 1598e1dd639eSManivannan Sadhasivam /* Qcom IP rev.: 1.9.0 */ 1599e1dd639eSManivannan Sadhasivam static const struct qcom_pcie_ops ops_1_9_0 = { 1600e1dd639eSManivannan Sadhasivam .get_resources = qcom_pcie_get_resources_2_7_0, 1601e1dd639eSManivannan Sadhasivam .init = qcom_pcie_init_2_7_0, 1602e1dd639eSManivannan Sadhasivam .deinit = qcom_pcie_deinit_2_7_0, 1603e1dd639eSManivannan Sadhasivam .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 16044c939882SManivannan Sadhasivam .config_sid = qcom_pcie_config_sid_sm8250, 1605e1dd639eSManivannan Sadhasivam }; 1606e1dd639eSManivannan Sadhasivam 16070cf7c2efSSelvam Sathappan Periakaruppan /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ 16080cf7c2efSSelvam Sathappan Periakaruppan static const struct qcom_pcie_ops ops_2_9_0 = { 16090cf7c2efSSelvam Sathappan Periakaruppan .get_resources = qcom_pcie_get_resources_2_9_0, 16100cf7c2efSSelvam Sathappan Periakaruppan .init = qcom_pcie_init_2_9_0, 16110cf7c2efSSelvam Sathappan Periakaruppan .post_init = qcom_pcie_post_init_2_9_0, 16120cf7c2efSSelvam Sathappan Periakaruppan .deinit = qcom_pcie_deinit_2_9_0, 16130cf7c2efSSelvam Sathappan Periakaruppan .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 16140cf7c2efSSelvam Sathappan Periakaruppan }; 16150cf7c2efSSelvam Sathappan Periakaruppan 1616b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg apq8084_cfg = { 1617b89ff410SPrasad Malisetty .ops = &ops_1_0_0, 1618b89ff410SPrasad Malisetty }; 1619b89ff410SPrasad Malisetty 1620b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg ipq8064_cfg = { 1621b89ff410SPrasad Malisetty .ops = &ops_2_1_0, 1622b89ff410SPrasad Malisetty }; 1623b89ff410SPrasad Malisetty 1624b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg msm8996_cfg = { 1625b89ff410SPrasad Malisetty .ops = &ops_2_3_2, 1626b89ff410SPrasad Malisetty }; 1627b89ff410SPrasad Malisetty 1628b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg ipq8074_cfg = { 1629b89ff410SPrasad Malisetty .ops = &ops_2_3_3, 1630b89ff410SPrasad Malisetty }; 1631b89ff410SPrasad Malisetty 1632b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg ipq4019_cfg = { 1633b89ff410SPrasad Malisetty .ops = &ops_2_4_0, 1634b89ff410SPrasad Malisetty }; 1635b89ff410SPrasad Malisetty 1636*70574511SJohan Hovold static const struct qcom_pcie_cfg sc8280xp_cfg = { 1637*70574511SJohan Hovold .ops = &ops_1_9_0, 1638*70574511SJohan Hovold .has_ddrss_sf_tbu_clk = true, 1639*70574511SJohan Hovold }; 1640*70574511SJohan Hovold 1641b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg sdm845_cfg = { 1642b89ff410SPrasad Malisetty .ops = &ops_2_7_0, 16431c5aa037SDmitry Baryshkov .has_tbu_clk = true, 1644b89ff410SPrasad Malisetty }; 1645b89ff410SPrasad Malisetty 1646a935601eSBhupesh Sharma static const struct qcom_pcie_cfg sm8150_cfg = { 1647a935601eSBhupesh Sharma /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as 1648a935601eSBhupesh Sharma * 1.9.0, so reuse the same. 1649a935601eSBhupesh Sharma */ 1650a935601eSBhupesh Sharma .ops = &ops_1_9_0, 1651a935601eSBhupesh Sharma }; 1652a935601eSBhupesh Sharma 1653b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg sm8250_cfg = { 1654b89ff410SPrasad Malisetty .ops = &ops_1_9_0, 16551c5aa037SDmitry Baryshkov .has_tbu_clk = true, 16560614f98bSDmitry Baryshkov .has_ddrss_sf_tbu_clk = true, 1657b89ff410SPrasad Malisetty }; 1658b89ff410SPrasad Malisetty 16591c5aa037SDmitry Baryshkov static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { 16601c5aa037SDmitry Baryshkov .ops = &ops_1_9_0, 16611c5aa037SDmitry Baryshkov .has_ddrss_sf_tbu_clk = true, 16621c5aa037SDmitry Baryshkov .has_aggre0_clk = true, 16631c5aa037SDmitry Baryshkov .has_aggre1_clk = true, 16641c5aa037SDmitry Baryshkov }; 16651c5aa037SDmitry Baryshkov 16661c5aa037SDmitry Baryshkov static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { 16671c5aa037SDmitry Baryshkov .ops = &ops_1_9_0, 16681c5aa037SDmitry Baryshkov .has_ddrss_sf_tbu_clk = true, 16691c5aa037SDmitry Baryshkov .has_aggre1_clk = true, 1670b89ff410SPrasad Malisetty }; 1671b89ff410SPrasad Malisetty 1672b89ff410SPrasad Malisetty static const struct qcom_pcie_cfg sc7280_cfg = { 1673b89ff410SPrasad Malisetty .ops = &ops_1_9_0, 16741c5aa037SDmitry Baryshkov .has_tbu_clk = true, 1675b89ff410SPrasad Malisetty }; 1676b89ff410SPrasad Malisetty 1677134b5ce3SBjorn Andersson static const struct qcom_pcie_cfg sc8180x_cfg = { 1678134b5ce3SBjorn Andersson .ops = &ops_1_9_0, 1679134b5ce3SBjorn Andersson .has_tbu_clk = true, 1680134b5ce3SBjorn Andersson }; 1681134b5ce3SBjorn Andersson 16820cf7c2efSSelvam Sathappan Periakaruppan static const struct qcom_pcie_cfg ipq6018_cfg = { 16830cf7c2efSSelvam Sathappan Periakaruppan .ops = &ops_2_9_0, 16840cf7c2efSSelvam Sathappan Periakaruppan }; 16850cf7c2efSSelvam Sathappan Periakaruppan 16866e0832faSShawn Lin static const struct dw_pcie_ops dw_pcie_ops = { 16876e0832faSShawn Lin .link_up = qcom_pcie_link_up, 1688886a9c13SRob Herring .start_link = qcom_pcie_start_link, 16896e0832faSShawn Lin }; 16906e0832faSShawn Lin 16916e0832faSShawn Lin static int qcom_pcie_probe(struct platform_device *pdev) 16926e0832faSShawn Lin { 16936e0832faSShawn Lin struct device *dev = &pdev->dev; 169460b3c27fSSerge Semin struct dw_pcie_rp *pp; 16956e0832faSShawn Lin struct dw_pcie *pci; 16966e0832faSShawn Lin struct qcom_pcie *pcie; 1697b89ff410SPrasad Malisetty const struct qcom_pcie_cfg *pcie_cfg; 16986e0832faSShawn Lin int ret; 16996e0832faSShawn Lin 17004e0e9053SChristophe JAILLET pcie_cfg = of_device_get_match_data(dev); 17014e0e9053SChristophe JAILLET if (!pcie_cfg || !pcie_cfg->ops) { 17024e0e9053SChristophe JAILLET dev_err(dev, "Invalid platform data\n"); 17034e0e9053SChristophe JAILLET return -EINVAL; 17044e0e9053SChristophe JAILLET } 17054e0e9053SChristophe JAILLET 17066e0832faSShawn Lin pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 17076e0832faSShawn Lin if (!pcie) 17086e0832faSShawn Lin return -ENOMEM; 17096e0832faSShawn Lin 17106e0832faSShawn Lin pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 17116e0832faSShawn Lin if (!pci) 17126e0832faSShawn Lin return -ENOMEM; 17136e0832faSShawn Lin 17146e0832faSShawn Lin pm_runtime_enable(dev); 17156e5da6f7SBjorn Andersson ret = pm_runtime_get_sync(dev); 1716cb52a402SDinghao Liu if (ret < 0) 1717cb52a402SDinghao Liu goto err_pm_runtime_put; 17186e5da6f7SBjorn Andersson 17196e0832faSShawn Lin pci->dev = dev; 17206e0832faSShawn Lin pci->ops = &dw_pcie_ops; 17216e0832faSShawn Lin pp = &pci->pp; 17226e0832faSShawn Lin 17236e0832faSShawn Lin pcie->pci = pci; 17246e0832faSShawn Lin 1725f94c35e0SDmitry Baryshkov pcie->cfg = pcie_cfg; 17266e0832faSShawn Lin 172702b485e3SBjorn Andersson pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 17286e5da6f7SBjorn Andersson if (IS_ERR(pcie->reset)) { 17296e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->reset); 17306e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17316e5da6f7SBjorn Andersson } 17326e0832faSShawn Lin 1733936fa5cdSDejin Zheng pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 17346e5da6f7SBjorn Andersson if (IS_ERR(pcie->parf)) { 17356e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->parf); 17366e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17376e5da6f7SBjorn Andersson } 17386e0832faSShawn Lin 1739936fa5cdSDejin Zheng pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 17406e5da6f7SBjorn Andersson if (IS_ERR(pcie->elbi)) { 17416e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->elbi); 17426e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17436e5da6f7SBjorn Andersson } 17446e0832faSShawn Lin 17456e0832faSShawn Lin pcie->phy = devm_phy_optional_get(dev, "pciephy"); 17466e5da6f7SBjorn Andersson if (IS_ERR(pcie->phy)) { 17476e5da6f7SBjorn Andersson ret = PTR_ERR(pcie->phy); 17486e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17496e5da6f7SBjorn Andersson } 17506e0832faSShawn Lin 1751f94c35e0SDmitry Baryshkov ret = pcie->cfg->ops->get_resources(pcie); 17526e0832faSShawn Lin if (ret) 17536e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17546e0832faSShawn Lin 17556e0832faSShawn Lin pp->ops = &qcom_pcie_dw_ops; 17566e0832faSShawn Lin 17576e0832faSShawn Lin ret = phy_init(pcie->phy); 175887d83b96SJohan Hovold if (ret) 17596e5da6f7SBjorn Andersson goto err_pm_runtime_put; 17606e0832faSShawn Lin 17616e0832faSShawn Lin platform_set_drvdata(pdev, pcie); 17626e0832faSShawn Lin 17636e0832faSShawn Lin ret = dw_pcie_host_init(pp); 17646e0832faSShawn Lin if (ret) { 17656e0832faSShawn Lin dev_err(dev, "cannot initialize host\n"); 176683013631SJohan Hovold goto err_phy_exit; 17676e0832faSShawn Lin } 17686e0832faSShawn Lin 17696e0832faSShawn Lin return 0; 17706e5da6f7SBjorn Andersson 177183013631SJohan Hovold err_phy_exit: 177283013631SJohan Hovold phy_exit(pcie->phy); 17736e5da6f7SBjorn Andersson err_pm_runtime_put: 17746e5da6f7SBjorn Andersson pm_runtime_put(dev); 17756e5da6f7SBjorn Andersson pm_runtime_disable(dev); 17766e5da6f7SBjorn Andersson 17776e5da6f7SBjorn Andersson return ret; 17786e0832faSShawn Lin } 17796e0832faSShawn Lin 17806e0832faSShawn Lin static const struct of_device_id qcom_pcie_match[] = { 1781b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg }, 1782b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg }, 1783b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg }, 1784b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg }, 1785b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg }, 1786b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, 1787b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, 1788b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, 1789b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, 1790a935601eSBhupesh Sharma { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, 1791b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, 1792134b5ce3SBjorn Andersson { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, 1793*70574511SJohan Hovold { .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg }, 17941c5aa037SDmitry Baryshkov { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, 17951c5aa037SDmitry Baryshkov { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, 1796b89ff410SPrasad Malisetty { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, 17970cf7c2efSSelvam Sathappan Periakaruppan { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg }, 17986e0832faSShawn Lin { } 17996e0832faSShawn Lin }; 18006e0832faSShawn Lin 1801322f0343SMarc Gonzalez static void qcom_fixup_class(struct pci_dev *dev) 1802322f0343SMarc Gonzalez { 1803904b10fbSPali Rohár dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 1804322f0343SMarc Gonzalez } 1805604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); 1806604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); 1807604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); 1808604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); 1809604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); 1810604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); 1811604f3956SBjorn Andersson DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); 1812322f0343SMarc Gonzalez 18136e0832faSShawn Lin static struct platform_driver qcom_pcie_driver = { 18146e0832faSShawn Lin .probe = qcom_pcie_probe, 18156e0832faSShawn Lin .driver = { 18166e0832faSShawn Lin .name = "qcom-pcie", 18176e0832faSShawn Lin .suppress_bind_attrs = true, 18186e0832faSShawn Lin .of_match_table = qcom_pcie_match, 18196e0832faSShawn Lin }, 18206e0832faSShawn Lin }; 18216e0832faSShawn Lin builtin_platform_driver(qcom_pcie_driver); 1822