1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/module.h> 22 23 #include "pcie-designware.h" 24 25 /* PARF registers */ 26 #define PARF_SYS_CTRL 0x00 27 #define PARF_DB_CTRL 0x10 28 #define PARF_PM_CTRL 0x20 29 #define PARF_MHI_BASE_ADDR_LOWER 0x178 30 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 31 #define PARF_DEBUG_INT_EN 0x190 32 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 33 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 34 #define PARF_Q2A_FLUSH 0x1ac 35 #define PARF_LTSSM 0x1b0 36 #define PARF_CFG_BITS 0x210 37 #define PARF_INT_ALL_STATUS 0x224 38 #define PARF_INT_ALL_CLEAR 0x228 39 #define PARF_INT_ALL_MASK 0x22c 40 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 41 #define PARF_DBI_BASE_ADDR 0x350 42 #define PARF_DBI_BASE_ADDR_HI 0x354 43 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 44 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 45 #define PARF_ATU_BASE_ADDR 0x634 46 #define PARF_ATU_BASE_ADDR_HI 0x638 47 #define PARF_SRIS_MODE 0x644 48 #define PARF_DEVICE_TYPE 0x1000 49 #define PARF_BDF_TO_SID_CFG 0x2c00 50 51 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 52 #define PARF_INT_ALL_LINK_DOWN BIT(1) 53 #define PARF_INT_ALL_BME BIT(2) 54 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 55 #define PARF_INT_ALL_DEBUG BIT(4) 56 #define PARF_INT_ALL_LTR BIT(5) 57 #define PARF_INT_ALL_MHI_Q6 BIT(6) 58 #define PARF_INT_ALL_MHI_A7 BIT(7) 59 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 60 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 61 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 62 #define PARF_INT_ALL_CFG_WRITE BIT(11) 63 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 64 #define PARF_INT_ALL_LINK_UP BIT(13) 65 #define PARF_INT_ALL_AER_LEGACY BIT(14) 66 #define PARF_INT_ALL_PLS_ERR BIT(15) 67 #define PARF_INT_ALL_PME_LEGACY BIT(16) 68 #define PARF_INT_ALL_PLS_PME BIT(17) 69 70 /* PARF_BDF_TO_SID_CFG register fields */ 71 #define PARF_BDF_TO_SID_BYPASS BIT(0) 72 73 /* PARF_DEBUG_INT_EN register fields */ 74 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 75 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 76 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 77 78 /* PARF_DEVICE_TYPE register fields */ 79 #define PARF_DEVICE_TYPE_EP 0x0 80 81 /* PARF_PM_CTRL register fields */ 82 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 83 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 84 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 85 86 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 87 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 88 89 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 90 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 91 92 /* PARF_Q2A_FLUSH register fields */ 93 #define PARF_Q2A_FLUSH_EN BIT(16) 94 95 /* PARF_SYS_CTRL register fields */ 96 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 97 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 98 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 99 100 /* PARF_DB_CTRL register fields */ 101 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 102 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 103 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 104 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 105 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 106 107 /* PARF_CFG_BITS register fields */ 108 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 109 110 /* ELBI registers */ 111 #define ELBI_SYS_STTS 0x08 112 113 /* DBI registers */ 114 #define DBI_CON_STATUS 0x44 115 116 /* DBI register fields */ 117 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 118 119 #define XMLH_LINK_UP 0x400 120 #define CORE_RESET_TIME_US_MIN 1000 121 #define CORE_RESET_TIME_US_MAX 1005 122 #define WAKE_DELAY_US 2000 /* 2 ms */ 123 124 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 125 126 enum qcom_pcie_ep_link_status { 127 QCOM_PCIE_EP_LINK_DISABLED, 128 QCOM_PCIE_EP_LINK_ENABLED, 129 QCOM_PCIE_EP_LINK_UP, 130 QCOM_PCIE_EP_LINK_DOWN, 131 }; 132 133 static struct clk_bulk_data qcom_pcie_ep_clks[] = { 134 { .id = "cfg" }, 135 { .id = "aux" }, 136 { .id = "bus_master" }, 137 { .id = "bus_slave" }, 138 { .id = "ref" }, 139 { .id = "sleep" }, 140 { .id = "slave_q2a" }, 141 }; 142 143 struct qcom_pcie_ep { 144 struct dw_pcie pci; 145 146 void __iomem *parf; 147 void __iomem *elbi; 148 struct regmap *perst_map; 149 struct resource *mmio_res; 150 151 struct reset_control *core_reset; 152 struct gpio_desc *reset; 153 struct gpio_desc *wake; 154 struct phy *phy; 155 156 u32 perst_en; 157 u32 perst_sep_en; 158 159 enum qcom_pcie_ep_link_status link_status; 160 int global_irq; 161 int perst_irq; 162 }; 163 164 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 165 { 166 struct dw_pcie *pci = &pcie_ep->pci; 167 struct device *dev = pci->dev; 168 int ret; 169 170 ret = reset_control_assert(pcie_ep->core_reset); 171 if (ret) { 172 dev_err(dev, "Cannot assert core reset\n"); 173 return ret; 174 } 175 176 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 177 178 ret = reset_control_deassert(pcie_ep->core_reset); 179 if (ret) { 180 dev_err(dev, "Cannot de-assert core reset\n"); 181 return ret; 182 } 183 184 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 185 186 return 0; 187 } 188 189 /* 190 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 191 * device reset during host reboot and hibernation. The driver is 192 * expected to handle this situation. 193 */ 194 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 195 { 196 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 197 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 198 } 199 200 static int qcom_pcie_dw_link_up(struct dw_pcie *pci) 201 { 202 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 203 u32 reg; 204 205 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 206 207 return reg & XMLH_LINK_UP; 208 } 209 210 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 211 { 212 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 213 214 enable_irq(pcie_ep->perst_irq); 215 216 return 0; 217 } 218 219 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 220 { 221 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 222 223 disable_irq(pcie_ep->perst_irq); 224 } 225 226 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 227 { 228 int ret; 229 230 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), 231 qcom_pcie_ep_clks); 232 if (ret) 233 return ret; 234 235 ret = qcom_pcie_ep_core_reset(pcie_ep); 236 if (ret) 237 goto err_disable_clk; 238 239 ret = phy_init(pcie_ep->phy); 240 if (ret) 241 goto err_disable_clk; 242 243 ret = phy_power_on(pcie_ep->phy); 244 if (ret) 245 goto err_phy_exit; 246 247 return 0; 248 249 err_phy_exit: 250 phy_exit(pcie_ep->phy); 251 err_disable_clk: 252 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 253 qcom_pcie_ep_clks); 254 255 return ret; 256 } 257 258 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 259 { 260 phy_power_off(pcie_ep->phy); 261 phy_exit(pcie_ep->phy); 262 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 263 qcom_pcie_ep_clks); 264 } 265 266 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 267 { 268 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 269 struct device *dev = pci->dev; 270 u32 val, offset; 271 int ret; 272 273 ret = qcom_pcie_enable_resources(pcie_ep); 274 if (ret) { 275 dev_err(dev, "Failed to enable resources: %d\n", ret); 276 return ret; 277 } 278 279 /* Assert WAKE# to RC to indicate device is ready */ 280 gpiod_set_value_cansleep(pcie_ep->wake, 1); 281 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 282 gpiod_set_value_cansleep(pcie_ep->wake, 0); 283 284 qcom_pcie_ep_configure_tcsr(pcie_ep); 285 286 /* Disable BDF to SID mapping */ 287 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 288 val |= PARF_BDF_TO_SID_BYPASS; 289 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 290 291 /* Enable debug IRQ */ 292 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 293 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 294 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 295 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 296 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 297 298 /* Configure PCIe to endpoint mode */ 299 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 300 301 /* Allow entering L1 state */ 302 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 303 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 304 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 305 306 /* Read halts write */ 307 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 308 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 309 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 310 311 /* Write after write halt */ 312 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 313 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 314 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 315 316 /* Q2A flush disable */ 317 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 318 val &= ~PARF_Q2A_FLUSH_EN; 319 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 320 321 /* Disable DBI Wakeup, core clock CGC and enable AUX power */ 322 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 323 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 324 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 325 PARF_SYS_CTRL_AUX_PWR_DET; 326 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 327 328 /* Disable the debouncers */ 329 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 330 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 331 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 332 PARF_DB_CTRL_MST_WKP_BLOCK; 333 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 334 335 /* Request to exit from L1SS for MSI and LTR MSG */ 336 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 337 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 338 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 339 340 dw_pcie_dbi_ro_wr_en(pci); 341 342 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 343 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 344 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 345 val &= ~PCI_EXP_LNKCAP_L0SEL; 346 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 347 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 348 349 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 350 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 351 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 352 val &= ~PCI_EXP_LNKCAP_L1EL; 353 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 354 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 355 356 dw_pcie_dbi_ro_wr_dis(pci); 357 358 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 359 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 360 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 361 PARF_INT_ALL_LINK_UP; 362 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 363 364 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); 365 if (ret) { 366 dev_err(dev, "Failed to complete initialization: %d\n", ret); 367 goto err_disable_resources; 368 } 369 370 /* 371 * The physical address of the MMIO region which is exposed as the BAR 372 * should be written to MHI BASE registers. 373 */ 374 writel_relaxed(pcie_ep->mmio_res->start, 375 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 376 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 377 378 dw_pcie_ep_init_notify(&pcie_ep->pci.ep); 379 380 /* Enable LTSSM */ 381 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 382 val |= BIT(8); 383 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 384 385 return 0; 386 387 err_disable_resources: 388 qcom_pcie_disable_resources(pcie_ep); 389 390 return ret; 391 } 392 393 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 394 { 395 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 396 struct device *dev = pci->dev; 397 398 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) { 399 dev_dbg(dev, "Link is already disabled\n"); 400 return; 401 } 402 403 qcom_pcie_disable_resources(pcie_ep); 404 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 405 } 406 407 /* Common DWC controller ops */ 408 static const struct dw_pcie_ops pci_ops = { 409 .link_up = qcom_pcie_dw_link_up, 410 .start_link = qcom_pcie_dw_start_link, 411 .stop_link = qcom_pcie_dw_stop_link, 412 }; 413 414 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 415 struct qcom_pcie_ep *pcie_ep) 416 { 417 struct device *dev = &pdev->dev; 418 struct dw_pcie *pci = &pcie_ep->pci; 419 struct device_node *syscon; 420 struct resource *res; 421 int ret; 422 423 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 424 if (IS_ERR(pcie_ep->parf)) 425 return PTR_ERR(pcie_ep->parf); 426 427 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 428 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 429 if (IS_ERR(pci->dbi_base)) 430 return PTR_ERR(pci->dbi_base); 431 pci->dbi_base2 = pci->dbi_base; 432 433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 434 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 435 if (IS_ERR(pcie_ep->elbi)) 436 return PTR_ERR(pcie_ep->elbi); 437 438 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 439 "mmio"); 440 441 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 442 if (!syscon) { 443 dev_err(dev, "Failed to parse qcom,perst-regs\n"); 444 return -EINVAL; 445 } 446 447 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 448 of_node_put(syscon); 449 if (IS_ERR(pcie_ep->perst_map)) 450 return PTR_ERR(pcie_ep->perst_map); 451 452 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 453 1, &pcie_ep->perst_en); 454 if (ret < 0) { 455 dev_err(dev, "No Perst Enable offset in syscon\n"); 456 return ret; 457 } 458 459 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 460 2, &pcie_ep->perst_sep_en); 461 if (ret < 0) { 462 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 463 return ret; 464 } 465 466 return 0; 467 } 468 469 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 470 struct qcom_pcie_ep *pcie_ep) 471 { 472 struct device *dev = &pdev->dev; 473 int ret; 474 475 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 476 if (ret) { 477 dev_err(&pdev->dev, "Failed to get io resources %d\n", ret); 478 return ret; 479 } 480 481 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(qcom_pcie_ep_clks), 482 qcom_pcie_ep_clks); 483 if (ret) 484 return ret; 485 486 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 487 if (IS_ERR(pcie_ep->core_reset)) 488 return PTR_ERR(pcie_ep->core_reset); 489 490 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 491 if (IS_ERR(pcie_ep->reset)) 492 return PTR_ERR(pcie_ep->reset); 493 494 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 495 if (IS_ERR(pcie_ep->wake)) 496 return PTR_ERR(pcie_ep->wake); 497 498 pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy"); 499 if (IS_ERR(pcie_ep->phy)) 500 ret = PTR_ERR(pcie_ep->phy); 501 502 return ret; 503 } 504 505 /* TODO: Notify clients about PCIe state change */ 506 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 507 { 508 struct qcom_pcie_ep *pcie_ep = data; 509 struct dw_pcie *pci = &pcie_ep->pci; 510 struct device *dev = pci->dev; 511 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 512 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 513 u32 dstate, val; 514 515 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 516 status &= mask; 517 518 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 519 dev_dbg(dev, "Received Linkdown event\n"); 520 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 521 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 522 dev_dbg(dev, "Received BME event. Link is enabled!\n"); 523 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 524 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 525 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 526 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 527 val |= PARF_PM_CTRL_READY_ENTR_L23; 528 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 529 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 530 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 531 DBI_CON_STATUS_POWER_STATE_MASK; 532 dev_dbg(dev, "Received D%d state event\n", dstate); 533 if (dstate == 3) { 534 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 535 val |= PARF_PM_CTRL_REQ_EXIT_L1; 536 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 537 } 538 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 539 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 540 dw_pcie_ep_linkup(&pci->ep); 541 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 542 } else { 543 dev_dbg(dev, "Received unknown event: %d\n", status); 544 } 545 546 return IRQ_HANDLED; 547 } 548 549 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 550 { 551 struct qcom_pcie_ep *pcie_ep = data; 552 struct dw_pcie *pci = &pcie_ep->pci; 553 struct device *dev = pci->dev; 554 u32 perst; 555 556 perst = gpiod_get_value(pcie_ep->reset); 557 if (perst) { 558 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 559 qcom_pcie_perst_assert(pci); 560 } else { 561 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 562 qcom_pcie_perst_deassert(pci); 563 } 564 565 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 566 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 567 568 return IRQ_HANDLED; 569 } 570 571 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 572 struct qcom_pcie_ep *pcie_ep) 573 { 574 int irq, ret; 575 576 irq = platform_get_irq_byname(pdev, "global"); 577 if (irq < 0) 578 return irq; 579 580 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 581 qcom_pcie_ep_global_irq_thread, 582 IRQF_ONESHOT, 583 "global_irq", pcie_ep); 584 if (ret) { 585 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 586 return ret; 587 } 588 589 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 590 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 591 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 592 qcom_pcie_ep_perst_irq_thread, 593 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 594 "perst_irq", pcie_ep); 595 if (ret) { 596 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 597 disable_irq(irq); 598 return ret; 599 } 600 601 return 0; 602 } 603 604 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 605 enum pci_epc_irq_type type, u16 interrupt_num) 606 { 607 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 608 609 switch (type) { 610 case PCI_EPC_IRQ_LEGACY: 611 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 612 case PCI_EPC_IRQ_MSI: 613 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 614 default: 615 dev_err(pci->dev, "Unknown IRQ type\n"); 616 return -EINVAL; 617 } 618 } 619 620 static const struct pci_epc_features qcom_pcie_epc_features = { 621 .linkup_notifier = true, 622 .core_init_notifier = true, 623 .msi_capable = true, 624 .msix_capable = false, 625 }; 626 627 static const struct pci_epc_features * 628 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 629 { 630 return &qcom_pcie_epc_features; 631 } 632 633 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 634 { 635 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 636 enum pci_barno bar; 637 638 for (bar = BAR_0; bar <= BAR_5; bar++) 639 dw_pcie_ep_reset_bar(pci, bar); 640 } 641 642 static const struct dw_pcie_ep_ops pci_ep_ops = { 643 .ep_init = qcom_pcie_ep_init, 644 .raise_irq = qcom_pcie_ep_raise_irq, 645 .get_features = qcom_pcie_epc_get_features, 646 }; 647 648 static int qcom_pcie_ep_probe(struct platform_device *pdev) 649 { 650 struct device *dev = &pdev->dev; 651 struct qcom_pcie_ep *pcie_ep; 652 int ret; 653 654 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 655 if (!pcie_ep) 656 return -ENOMEM; 657 658 pcie_ep->pci.dev = dev; 659 pcie_ep->pci.ops = &pci_ops; 660 pcie_ep->pci.ep.ops = &pci_ep_ops; 661 platform_set_drvdata(pdev, pcie_ep); 662 663 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 664 if (ret) 665 return ret; 666 667 ret = qcom_pcie_enable_resources(pcie_ep); 668 if (ret) { 669 dev_err(dev, "Failed to enable resources: %d\n", ret); 670 return ret; 671 } 672 673 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 674 if (ret) { 675 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 676 goto err_disable_resources; 677 } 678 679 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 680 if (ret) 681 goto err_disable_resources; 682 683 return 0; 684 685 err_disable_resources: 686 qcom_pcie_disable_resources(pcie_ep); 687 688 return ret; 689 } 690 691 static int qcom_pcie_ep_remove(struct platform_device *pdev) 692 { 693 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 694 695 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 696 return 0; 697 698 qcom_pcie_disable_resources(pcie_ep); 699 700 return 0; 701 } 702 703 static const struct of_device_id qcom_pcie_ep_match[] = { 704 { .compatible = "qcom,sdx55-pcie-ep", }, 705 { } 706 }; 707 708 static struct platform_driver qcom_pcie_ep_driver = { 709 .probe = qcom_pcie_ep_probe, 710 .remove = qcom_pcie_ep_remove, 711 .driver = { 712 .name = "qcom-pcie-ep", 713 .of_match_table = qcom_pcie_ep_match, 714 }, 715 }; 716 builtin_platform_driver(qcom_pcie_ep_driver); 717 718 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 719 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 720 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 721 MODULE_LICENSE("GPL v2"); 722