1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/module.h> 22 23 #include "pcie-designware.h" 24 25 /* PARF registers */ 26 #define PARF_SYS_CTRL 0x00 27 #define PARF_DB_CTRL 0x10 28 #define PARF_PM_CTRL 0x20 29 #define PARF_MHI_BASE_ADDR_LOWER 0x178 30 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 31 #define PARF_DEBUG_INT_EN 0x190 32 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 33 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 34 #define PARF_Q2A_FLUSH 0x1ac 35 #define PARF_LTSSM 0x1b0 36 #define PARF_CFG_BITS 0x210 37 #define PARF_INT_ALL_STATUS 0x224 38 #define PARF_INT_ALL_CLEAR 0x228 39 #define PARF_INT_ALL_MASK 0x22c 40 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 41 #define PARF_DBI_BASE_ADDR 0x350 42 #define PARF_DBI_BASE_ADDR_HI 0x354 43 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 44 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 45 #define PARF_ATU_BASE_ADDR 0x634 46 #define PARF_ATU_BASE_ADDR_HI 0x638 47 #define PARF_SRIS_MODE 0x644 48 #define PARF_DEVICE_TYPE 0x1000 49 #define PARF_BDF_TO_SID_CFG 0x2c00 50 51 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 52 #define PARF_INT_ALL_LINK_DOWN BIT(1) 53 #define PARF_INT_ALL_BME BIT(2) 54 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 55 #define PARF_INT_ALL_DEBUG BIT(4) 56 #define PARF_INT_ALL_LTR BIT(5) 57 #define PARF_INT_ALL_MHI_Q6 BIT(6) 58 #define PARF_INT_ALL_MHI_A7 BIT(7) 59 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 60 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 61 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 62 #define PARF_INT_ALL_CFG_WRITE BIT(11) 63 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 64 #define PARF_INT_ALL_LINK_UP BIT(13) 65 #define PARF_INT_ALL_AER_LEGACY BIT(14) 66 #define PARF_INT_ALL_PLS_ERR BIT(15) 67 #define PARF_INT_ALL_PME_LEGACY BIT(16) 68 #define PARF_INT_ALL_PLS_PME BIT(17) 69 70 /* PARF_BDF_TO_SID_CFG register fields */ 71 #define PARF_BDF_TO_SID_BYPASS BIT(0) 72 73 /* PARF_DEBUG_INT_EN register fields */ 74 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 75 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 76 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 77 78 /* PARF_DEVICE_TYPE register fields */ 79 #define PARF_DEVICE_TYPE_EP 0x0 80 81 /* PARF_PM_CTRL register fields */ 82 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 83 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 84 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 85 86 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 87 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 88 89 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 90 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 91 92 /* PARF_Q2A_FLUSH register fields */ 93 #define PARF_Q2A_FLUSH_EN BIT(16) 94 95 /* PARF_SYS_CTRL register fields */ 96 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 97 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 98 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 99 100 /* PARF_DB_CTRL register fields */ 101 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 102 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 103 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 104 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 105 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 106 107 /* PARF_CFG_BITS register fields */ 108 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 109 110 /* ELBI registers */ 111 #define ELBI_SYS_STTS 0x08 112 113 /* DBI registers */ 114 #define DBI_CON_STATUS 0x44 115 116 /* DBI register fields */ 117 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 118 119 #define XMLH_LINK_UP 0x400 120 #define CORE_RESET_TIME_US_MIN 1000 121 #define CORE_RESET_TIME_US_MAX 1005 122 #define WAKE_DELAY_US 2000 /* 2 ms */ 123 124 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 125 126 enum qcom_pcie_ep_link_status { 127 QCOM_PCIE_EP_LINK_DISABLED, 128 QCOM_PCIE_EP_LINK_ENABLED, 129 QCOM_PCIE_EP_LINK_UP, 130 QCOM_PCIE_EP_LINK_DOWN, 131 }; 132 133 static struct clk_bulk_data qcom_pcie_ep_clks[] = { 134 { .id = "cfg" }, 135 { .id = "aux" }, 136 { .id = "bus_master" }, 137 { .id = "bus_slave" }, 138 { .id = "ref" }, 139 { .id = "sleep" }, 140 { .id = "slave_q2a" }, 141 }; 142 143 struct qcom_pcie_ep { 144 struct dw_pcie pci; 145 146 void __iomem *parf; 147 void __iomem *elbi; 148 struct regmap *perst_map; 149 struct resource *mmio_res; 150 151 struct reset_control *core_reset; 152 struct gpio_desc *reset; 153 struct gpio_desc *wake; 154 struct phy *phy; 155 156 u32 perst_en; 157 u32 perst_sep_en; 158 159 enum qcom_pcie_ep_link_status link_status; 160 int global_irq; 161 int perst_irq; 162 }; 163 164 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 165 { 166 struct dw_pcie *pci = &pcie_ep->pci; 167 struct device *dev = pci->dev; 168 int ret; 169 170 ret = reset_control_assert(pcie_ep->core_reset); 171 if (ret) { 172 dev_err(dev, "Cannot assert core reset\n"); 173 return ret; 174 } 175 176 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 177 178 ret = reset_control_deassert(pcie_ep->core_reset); 179 if (ret) { 180 dev_err(dev, "Cannot de-assert core reset\n"); 181 return ret; 182 } 183 184 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 185 186 return 0; 187 } 188 189 /* 190 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 191 * device reset during host reboot and hibernation. The driver is 192 * expected to handle this situation. 193 */ 194 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 195 { 196 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 197 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 198 } 199 200 static int qcom_pcie_dw_link_up(struct dw_pcie *pci) 201 { 202 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 203 u32 reg; 204 205 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 206 207 return reg & XMLH_LINK_UP; 208 } 209 210 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 211 { 212 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 213 214 enable_irq(pcie_ep->perst_irq); 215 216 return 0; 217 } 218 219 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 220 { 221 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 222 223 disable_irq(pcie_ep->perst_irq); 224 } 225 226 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 227 { 228 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 229 struct device *dev = pci->dev; 230 u32 val, offset; 231 int ret; 232 233 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), 234 qcom_pcie_ep_clks); 235 if (ret) 236 return ret; 237 238 ret = qcom_pcie_ep_core_reset(pcie_ep); 239 if (ret) 240 goto err_disable_clk; 241 242 ret = phy_init(pcie_ep->phy); 243 if (ret) 244 goto err_disable_clk; 245 246 ret = phy_power_on(pcie_ep->phy); 247 if (ret) 248 goto err_phy_exit; 249 250 /* Assert WAKE# to RC to indicate device is ready */ 251 gpiod_set_value_cansleep(pcie_ep->wake, 1); 252 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 253 gpiod_set_value_cansleep(pcie_ep->wake, 0); 254 255 qcom_pcie_ep_configure_tcsr(pcie_ep); 256 257 /* Disable BDF to SID mapping */ 258 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 259 val |= PARF_BDF_TO_SID_BYPASS; 260 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 261 262 /* Enable debug IRQ */ 263 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 264 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 265 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 266 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 267 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 268 269 /* Configure PCIe to endpoint mode */ 270 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 271 272 /* Allow entering L1 state */ 273 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 274 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 275 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 276 277 /* Read halts write */ 278 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 279 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 280 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 281 282 /* Write after write halt */ 283 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 284 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 285 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 286 287 /* Q2A flush disable */ 288 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 289 val &= ~PARF_Q2A_FLUSH_EN; 290 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 291 292 /* Disable DBI Wakeup, core clock CGC and enable AUX power */ 293 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 294 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 295 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 296 PARF_SYS_CTRL_AUX_PWR_DET; 297 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 298 299 /* Disable the debouncers */ 300 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 301 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 302 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 303 PARF_DB_CTRL_MST_WKP_BLOCK; 304 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 305 306 /* Request to exit from L1SS for MSI and LTR MSG */ 307 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 308 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 309 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 310 311 dw_pcie_dbi_ro_wr_en(pci); 312 313 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 314 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 315 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 316 val &= ~PCI_EXP_LNKCAP_L0SEL; 317 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 318 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 319 320 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 321 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 322 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 323 val &= ~PCI_EXP_LNKCAP_L1EL; 324 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 325 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 326 327 dw_pcie_dbi_ro_wr_dis(pci); 328 329 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 330 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 331 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 332 PARF_INT_ALL_LINK_UP; 333 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 334 335 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); 336 if (ret) { 337 dev_err(dev, "Failed to complete initialization: %d\n", ret); 338 goto err_phy_power_off; 339 } 340 341 /* 342 * The physical address of the MMIO region which is exposed as the BAR 343 * should be written to MHI BASE registers. 344 */ 345 writel_relaxed(pcie_ep->mmio_res->start, 346 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 347 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 348 349 dw_pcie_ep_init_notify(&pcie_ep->pci.ep); 350 351 /* Enable LTSSM */ 352 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 353 val |= BIT(8); 354 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 355 356 return 0; 357 358 err_phy_power_off: 359 phy_power_off(pcie_ep->phy); 360 err_phy_exit: 361 phy_exit(pcie_ep->phy); 362 err_disable_clk: 363 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 364 qcom_pcie_ep_clks); 365 366 return ret; 367 } 368 369 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 370 { 371 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 372 struct device *dev = pci->dev; 373 374 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) { 375 dev_dbg(dev, "Link is already disabled\n"); 376 return; 377 } 378 379 phy_power_off(pcie_ep->phy); 380 phy_exit(pcie_ep->phy); 381 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 382 qcom_pcie_ep_clks); 383 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 384 } 385 386 /* Common DWC controller ops */ 387 static const struct dw_pcie_ops pci_ops = { 388 .link_up = qcom_pcie_dw_link_up, 389 .start_link = qcom_pcie_dw_start_link, 390 .stop_link = qcom_pcie_dw_stop_link, 391 }; 392 393 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 394 struct qcom_pcie_ep *pcie_ep) 395 { 396 struct device *dev = &pdev->dev; 397 struct dw_pcie *pci = &pcie_ep->pci; 398 struct device_node *syscon; 399 struct resource *res; 400 int ret; 401 402 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 403 if (IS_ERR(pcie_ep->parf)) 404 return PTR_ERR(pcie_ep->parf); 405 406 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 407 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 408 if (IS_ERR(pci->dbi_base)) 409 return PTR_ERR(pci->dbi_base); 410 pci->dbi_base2 = pci->dbi_base; 411 412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 413 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 414 if (IS_ERR(pcie_ep->elbi)) 415 return PTR_ERR(pcie_ep->elbi); 416 417 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 418 "mmio"); 419 420 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 421 if (!syscon) { 422 dev_err(dev, "Failed to parse qcom,perst-regs\n"); 423 return -EINVAL; 424 } 425 426 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 427 of_node_put(syscon); 428 if (IS_ERR(pcie_ep->perst_map)) 429 return PTR_ERR(pcie_ep->perst_map); 430 431 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 432 1, &pcie_ep->perst_en); 433 if (ret < 0) { 434 dev_err(dev, "No Perst Enable offset in syscon\n"); 435 return ret; 436 } 437 438 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 439 2, &pcie_ep->perst_sep_en); 440 if (ret < 0) { 441 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 449 struct qcom_pcie_ep *pcie_ep) 450 { 451 struct device *dev = &pdev->dev; 452 int ret; 453 454 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 455 if (ret) { 456 dev_err(&pdev->dev, "Failed to get io resources %d\n", ret); 457 return ret; 458 } 459 460 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(qcom_pcie_ep_clks), 461 qcom_pcie_ep_clks); 462 if (ret) 463 return ret; 464 465 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 466 if (IS_ERR(pcie_ep->core_reset)) 467 return PTR_ERR(pcie_ep->core_reset); 468 469 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 470 if (IS_ERR(pcie_ep->reset)) 471 return PTR_ERR(pcie_ep->reset); 472 473 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 474 if (IS_ERR(pcie_ep->wake)) 475 return PTR_ERR(pcie_ep->wake); 476 477 pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy"); 478 if (IS_ERR(pcie_ep->phy)) 479 ret = PTR_ERR(pcie_ep->phy); 480 481 return ret; 482 } 483 484 /* TODO: Notify clients about PCIe state change */ 485 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 486 { 487 struct qcom_pcie_ep *pcie_ep = data; 488 struct dw_pcie *pci = &pcie_ep->pci; 489 struct device *dev = pci->dev; 490 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 491 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 492 u32 dstate, val; 493 494 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 495 status &= mask; 496 497 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 498 dev_dbg(dev, "Received Linkdown event\n"); 499 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 500 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 501 dev_dbg(dev, "Received BME event. Link is enabled!\n"); 502 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 503 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 504 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 505 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 506 val |= PARF_PM_CTRL_READY_ENTR_L23; 507 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 508 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 509 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 510 DBI_CON_STATUS_POWER_STATE_MASK; 511 dev_dbg(dev, "Received D%d state event\n", dstate); 512 if (dstate == 3) { 513 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 514 val |= PARF_PM_CTRL_REQ_EXIT_L1; 515 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 516 } 517 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 518 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 519 dw_pcie_ep_linkup(&pci->ep); 520 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 521 } else { 522 dev_dbg(dev, "Received unknown event: %d\n", status); 523 } 524 525 return IRQ_HANDLED; 526 } 527 528 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 529 { 530 struct qcom_pcie_ep *pcie_ep = data; 531 struct dw_pcie *pci = &pcie_ep->pci; 532 struct device *dev = pci->dev; 533 u32 perst; 534 535 perst = gpiod_get_value(pcie_ep->reset); 536 if (perst) { 537 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 538 qcom_pcie_perst_assert(pci); 539 } else { 540 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 541 qcom_pcie_perst_deassert(pci); 542 } 543 544 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 545 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 546 547 return IRQ_HANDLED; 548 } 549 550 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 551 struct qcom_pcie_ep *pcie_ep) 552 { 553 int irq, ret; 554 555 irq = platform_get_irq_byname(pdev, "global"); 556 if (irq < 0) 557 return irq; 558 559 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 560 qcom_pcie_ep_global_irq_thread, 561 IRQF_ONESHOT, 562 "global_irq", pcie_ep); 563 if (ret) { 564 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 565 return ret; 566 } 567 568 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 569 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 570 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 571 qcom_pcie_ep_perst_irq_thread, 572 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 573 "perst_irq", pcie_ep); 574 if (ret) { 575 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 576 disable_irq(irq); 577 return ret; 578 } 579 580 return 0; 581 } 582 583 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 584 enum pci_epc_irq_type type, u16 interrupt_num) 585 { 586 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 587 588 switch (type) { 589 case PCI_EPC_IRQ_LEGACY: 590 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 591 case PCI_EPC_IRQ_MSI: 592 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 593 default: 594 dev_err(pci->dev, "Unknown IRQ type\n"); 595 return -EINVAL; 596 } 597 } 598 599 static const struct pci_epc_features qcom_pcie_epc_features = { 600 .linkup_notifier = true, 601 .core_init_notifier = true, 602 .msi_capable = true, 603 .msix_capable = false, 604 }; 605 606 static const struct pci_epc_features * 607 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 608 { 609 return &qcom_pcie_epc_features; 610 } 611 612 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 613 { 614 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 615 enum pci_barno bar; 616 617 for (bar = BAR_0; bar <= BAR_5; bar++) 618 dw_pcie_ep_reset_bar(pci, bar); 619 } 620 621 static const struct dw_pcie_ep_ops pci_ep_ops = { 622 .ep_init = qcom_pcie_ep_init, 623 .raise_irq = qcom_pcie_ep_raise_irq, 624 .get_features = qcom_pcie_epc_get_features, 625 }; 626 627 static int qcom_pcie_ep_probe(struct platform_device *pdev) 628 { 629 struct device *dev = &pdev->dev; 630 struct qcom_pcie_ep *pcie_ep; 631 int ret; 632 633 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 634 if (!pcie_ep) 635 return -ENOMEM; 636 637 pcie_ep->pci.dev = dev; 638 pcie_ep->pci.ops = &pci_ops; 639 pcie_ep->pci.ep.ops = &pci_ep_ops; 640 platform_set_drvdata(pdev, pcie_ep); 641 642 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 643 if (ret) 644 return ret; 645 646 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), 647 qcom_pcie_ep_clks); 648 if (ret) 649 return ret; 650 651 ret = qcom_pcie_ep_core_reset(pcie_ep); 652 if (ret) 653 goto err_disable_clk; 654 655 ret = phy_init(pcie_ep->phy); 656 if (ret) 657 goto err_disable_clk; 658 659 /* PHY needs to be powered on for dw_pcie_ep_init() */ 660 ret = phy_power_on(pcie_ep->phy); 661 if (ret) 662 goto err_phy_exit; 663 664 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 665 if (ret) { 666 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 667 goto err_phy_power_off; 668 } 669 670 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 671 if (ret) 672 goto err_phy_power_off; 673 674 return 0; 675 676 err_phy_power_off: 677 phy_power_off(pcie_ep->phy); 678 err_phy_exit: 679 phy_exit(pcie_ep->phy); 680 err_disable_clk: 681 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 682 qcom_pcie_ep_clks); 683 684 return ret; 685 } 686 687 static int qcom_pcie_ep_remove(struct platform_device *pdev) 688 { 689 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 690 691 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 692 return 0; 693 694 phy_power_off(pcie_ep->phy); 695 phy_exit(pcie_ep->phy); 696 clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), 697 qcom_pcie_ep_clks); 698 699 return 0; 700 } 701 702 static const struct of_device_id qcom_pcie_ep_match[] = { 703 { .compatible = "qcom,sdx55-pcie-ep", }, 704 { } 705 }; 706 707 static struct platform_driver qcom_pcie_ep_driver = { 708 .probe = qcom_pcie_ep_probe, 709 .remove = qcom_pcie_ep_remove, 710 .driver = { 711 .name = "qcom-pcie-ep", 712 .of_match_table = qcom_pcie_ep_match, 713 }, 714 }; 715 builtin_platform_driver(qcom_pcie_ep_driver); 716 717 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 718 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 719 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 720 MODULE_LICENSE("GPL v2"); 721