1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/module.h>
25
26 #include "pcie-designware.h"
27
28 /* PARF registers */
29 #define PARF_SYS_CTRL 0x00
30 #define PARF_DB_CTRL 0x10
31 #define PARF_PM_CTRL 0x20
32 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
33 #define PARF_MHI_BASE_ADDR_LOWER 0x178
34 #define PARF_MHI_BASE_ADDR_UPPER 0x17c
35 #define PARF_DEBUG_INT_EN 0x190
36 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
37 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
38 #define PARF_Q2A_FLUSH 0x1ac
39 #define PARF_LTSSM 0x1b0
40 #define PARF_CFG_BITS 0x210
41 #define PARF_INT_ALL_STATUS 0x224
42 #define PARF_INT_ALL_CLEAR 0x228
43 #define PARF_INT_ALL_MASK 0x22c
44 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0
45 #define PARF_DBI_BASE_ADDR 0x350
46 #define PARF_DBI_BASE_ADDR_HI 0x354
47 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
48 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
49 #define PARF_ATU_BASE_ADDR 0x634
50 #define PARF_ATU_BASE_ADDR_HI 0x638
51 #define PARF_SRIS_MODE 0x644
52 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
53 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
54 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
55 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
56 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
57 #define PARF_DEVICE_TYPE 0x1000
58 #define PARF_BDF_TO_SID_CFG 0x2c00
59
60 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
61 #define PARF_INT_ALL_LINK_DOWN BIT(1)
62 #define PARF_INT_ALL_BME BIT(2)
63 #define PARF_INT_ALL_PM_TURNOFF BIT(3)
64 #define PARF_INT_ALL_DEBUG BIT(4)
65 #define PARF_INT_ALL_LTR BIT(5)
66 #define PARF_INT_ALL_MHI_Q6 BIT(6)
67 #define PARF_INT_ALL_MHI_A7 BIT(7)
68 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
69 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
70 #define PARF_INT_ALL_MMIO_WRITE BIT(10)
71 #define PARF_INT_ALL_CFG_WRITE BIT(11)
72 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
73 #define PARF_INT_ALL_LINK_UP BIT(13)
74 #define PARF_INT_ALL_AER_LEGACY BIT(14)
75 #define PARF_INT_ALL_PLS_ERR BIT(15)
76 #define PARF_INT_ALL_PME_LEGACY BIT(16)
77 #define PARF_INT_ALL_PLS_PME BIT(17)
78 #define PARF_INT_ALL_EDMA BIT(22)
79
80 /* PARF_BDF_TO_SID_CFG register fields */
81 #define PARF_BDF_TO_SID_BYPASS BIT(0)
82
83 /* PARF_DEBUG_INT_EN register fields */
84 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
85 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
86 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
87
88 /* PARF_DEVICE_TYPE register fields */
89 #define PARF_DEVICE_TYPE_EP 0x0
90
91 /* PARF_PM_CTRL register fields */
92 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
93 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
94 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
95
96 /* PARF_MHI_CLOCK_RESET_CTRL fields */
97 #define PARF_MSTR_AXI_CLK_EN BIT(1)
98
99 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
100 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
101
102 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
103 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
104
105 /* PARF_Q2A_FLUSH register fields */
106 #define PARF_Q2A_FLUSH_EN BIT(16)
107
108 /* PARF_SYS_CTRL register fields */
109 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
110 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
111 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
112 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
113
114 /* PARF_DB_CTRL register fields */
115 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
116 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
117 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
118 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
119 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
120
121 /* PARF_CFG_BITS register fields */
122 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
123
124 /* ELBI registers */
125 #define ELBI_SYS_STTS 0x08
126 #define ELBI_CS2_ENABLE 0xa4
127
128 /* DBI registers */
129 #define DBI_CON_STATUS 0x44
130
131 /* DBI register fields */
132 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
133
134 #define XMLH_LINK_UP 0x400
135 #define CORE_RESET_TIME_US_MIN 1000
136 #define CORE_RESET_TIME_US_MAX 1005
137 #define WAKE_DELAY_US 2000 /* 2 ms */
138
139 #define PCIE_GEN1_BW_MBPS 250
140 #define PCIE_GEN2_BW_MBPS 500
141 #define PCIE_GEN3_BW_MBPS 985
142 #define PCIE_GEN4_BW_MBPS 1969
143
144 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
145
146 enum qcom_pcie_ep_link_status {
147 QCOM_PCIE_EP_LINK_DISABLED,
148 QCOM_PCIE_EP_LINK_ENABLED,
149 QCOM_PCIE_EP_LINK_UP,
150 QCOM_PCIE_EP_LINK_DOWN,
151 };
152
153 /**
154 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
155 * @pci: Designware PCIe controller struct
156 * @parf: Qualcomm PCIe specific PARF register base
157 * @elbi: Designware PCIe specific ELBI register base
158 * @mmio: MMIO register base
159 * @perst_map: PERST regmap
160 * @mmio_res: MMIO region resource
161 * @core_reset: PCIe Endpoint core reset
162 * @reset: PERST# GPIO
163 * @wake: WAKE# GPIO
164 * @phy: PHY controller block
165 * @debugfs: PCIe Endpoint Debugfs directory
166 * @icc_mem: Handle to an interconnect path between PCIe and MEM
167 * @clks: PCIe clocks
168 * @num_clks: PCIe clocks count
169 * @perst_en: Flag for PERST enable
170 * @perst_sep_en: Flag for PERST separation enable
171 * @link_status: PCIe Link status
172 * @global_irq: Qualcomm PCIe specific Global IRQ
173 * @perst_irq: PERST# IRQ
174 */
175 struct qcom_pcie_ep {
176 struct dw_pcie pci;
177
178 void __iomem *parf;
179 void __iomem *elbi;
180 void __iomem *mmio;
181 struct regmap *perst_map;
182 struct resource *mmio_res;
183
184 struct reset_control *core_reset;
185 struct gpio_desc *reset;
186 struct gpio_desc *wake;
187 struct phy *phy;
188 struct dentry *debugfs;
189
190 struct icc_path *icc_mem;
191
192 struct clk_bulk_data *clks;
193 int num_clks;
194
195 u32 perst_en;
196 u32 perst_sep_en;
197
198 enum qcom_pcie_ep_link_status link_status;
199 int global_irq;
200 int perst_irq;
201 };
202
qcom_pcie_ep_core_reset(struct qcom_pcie_ep * pcie_ep)203 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
204 {
205 struct dw_pcie *pci = &pcie_ep->pci;
206 struct device *dev = pci->dev;
207 int ret;
208
209 ret = reset_control_assert(pcie_ep->core_reset);
210 if (ret) {
211 dev_err(dev, "Cannot assert core reset\n");
212 return ret;
213 }
214
215 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
216
217 ret = reset_control_deassert(pcie_ep->core_reset);
218 if (ret) {
219 dev_err(dev, "Cannot de-assert core reset\n");
220 return ret;
221 }
222
223 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
224
225 return 0;
226 }
227
228 /*
229 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
230 * device reset during host reboot and hibernation. The driver is
231 * expected to handle this situation.
232 */
qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep * pcie_ep)233 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
234 {
235 if (pcie_ep->perst_map) {
236 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
237 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
238 }
239 }
240
qcom_pcie_dw_link_up(struct dw_pcie * pci)241 static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
242 {
243 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
244 u32 reg;
245
246 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
247
248 return reg & XMLH_LINK_UP;
249 }
250
qcom_pcie_dw_start_link(struct dw_pcie * pci)251 static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
252 {
253 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
254
255 enable_irq(pcie_ep->perst_irq);
256
257 return 0;
258 }
259
qcom_pcie_dw_stop_link(struct dw_pcie * pci)260 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
261 {
262 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
263
264 disable_irq(pcie_ep->perst_irq);
265 }
266
qcom_pcie_dw_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val)267 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
268 u32 reg, size_t size, u32 val)
269 {
270 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
271 int ret;
272
273 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE);
274
275 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
276 if (ret)
277 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);
278
279 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE);
280 }
281
qcom_pcie_ep_icc_update(struct qcom_pcie_ep * pcie_ep)282 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
283 {
284 struct dw_pcie *pci = &pcie_ep->pci;
285 u32 offset, status, bw;
286 int speed, width;
287 int ret;
288
289 if (!pcie_ep->icc_mem)
290 return;
291
292 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
293 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
294
295 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
296 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
297
298 switch (speed) {
299 case 1:
300 bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);
301 break;
302 case 2:
303 bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);
304 break;
305 case 3:
306 bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);
307 break;
308 default:
309 dev_warn(pci->dev, "using default GEN4 bandwidth\n");
310 fallthrough;
311 case 4:
312 bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);
313 break;
314 }
315
316 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);
317 if (ret)
318 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
319 ret);
320 }
321
qcom_pcie_enable_resources(struct qcom_pcie_ep * pcie_ep)322 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
323 {
324 struct dw_pcie *pci = &pcie_ep->pci;
325 int ret;
326
327 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
328 if (ret)
329 return ret;
330
331 ret = qcom_pcie_ep_core_reset(pcie_ep);
332 if (ret)
333 goto err_disable_clk;
334
335 ret = phy_init(pcie_ep->phy);
336 if (ret)
337 goto err_disable_clk;
338
339 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
340 if (ret)
341 goto err_phy_exit;
342
343 ret = phy_power_on(pcie_ep->phy);
344 if (ret)
345 goto err_phy_exit;
346
347 /*
348 * Some Qualcomm platforms require interconnect bandwidth constraints
349 * to be set before enabling interconnect clocks.
350 *
351 * Set an initial peak bandwidth corresponding to single-lane Gen 1
352 * for the pcie-mem path.
353 */
354 ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));
355 if (ret) {
356 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
357 ret);
358 goto err_phy_off;
359 }
360
361 return 0;
362
363 err_phy_off:
364 phy_power_off(pcie_ep->phy);
365 err_phy_exit:
366 phy_exit(pcie_ep->phy);
367 err_disable_clk:
368 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
369
370 return ret;
371 }
372
qcom_pcie_disable_resources(struct qcom_pcie_ep * pcie_ep)373 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
374 {
375 icc_set_bw(pcie_ep->icc_mem, 0, 0);
376 phy_power_off(pcie_ep->phy);
377 phy_exit(pcie_ep->phy);
378 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
379 }
380
qcom_pcie_perst_deassert(struct dw_pcie * pci)381 static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
382 {
383 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
384 struct device *dev = pci->dev;
385 u32 val, offset;
386 int ret;
387
388 ret = qcom_pcie_enable_resources(pcie_ep);
389 if (ret) {
390 dev_err(dev, "Failed to enable resources: %d\n", ret);
391 return ret;
392 }
393
394 /* Assert WAKE# to RC to indicate device is ready */
395 gpiod_set_value_cansleep(pcie_ep->wake, 1);
396 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
397 gpiod_set_value_cansleep(pcie_ep->wake, 0);
398
399 qcom_pcie_ep_configure_tcsr(pcie_ep);
400
401 /* Disable BDF to SID mapping */
402 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
403 val |= PARF_BDF_TO_SID_BYPASS;
404 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
405
406 /* Enable debug IRQ */
407 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
408 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
409 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
410 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
411 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
412
413 /* Configure PCIe to endpoint mode */
414 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
415
416 /* Allow entering L1 state */
417 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
418 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
419 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
420
421 /* Read halts write */
422 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
423 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
424 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
425
426 /* Write after write halt */
427 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
428 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
429 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
430
431 /* Q2A flush disable */
432 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
433 val &= ~PARF_Q2A_FLUSH_EN;
434 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
435
436 /*
437 * Disable Master AXI clock during idle. Do not allow DBI access
438 * to take the core out of L1. Disable core clock gating that
439 * gates PIPE clock from propagating to core clock. Report to the
440 * host that Vaux is present.
441 */
442 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
443 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
444 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
445 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
446 PARF_SYS_CTRL_AUX_PWR_DET;
447 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
448
449 /* Disable the debouncers */
450 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
451 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
452 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
453 PARF_DB_CTRL_MST_WKP_BLOCK;
454 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
455
456 /* Request to exit from L1SS for MSI and LTR MSG */
457 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
458 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
459 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
460
461 dw_pcie_dbi_ro_wr_en(pci);
462
463 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
464 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
465 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
466 val &= ~PCI_EXP_LNKCAP_L0SEL;
467 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
468 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
469
470 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
471 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
472 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
473 val &= ~PCI_EXP_LNKCAP_L1EL;
474 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
475 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
476
477 dw_pcie_dbi_ro_wr_dis(pci);
478
479 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
480 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
481 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
482 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
483 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
484
485 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
486 if (ret) {
487 dev_err(dev, "Failed to complete initialization: %d\n", ret);
488 goto err_disable_resources;
489 }
490
491 /*
492 * The physical address of the MMIO region which is exposed as the BAR
493 * should be written to MHI BASE registers.
494 */
495 writel_relaxed(pcie_ep->mmio_res->start,
496 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
497 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
498
499 /* Gate Master AXI clock to MHI bus during L1SS */
500 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
501 val &= ~PARF_MSTR_AXI_CLK_EN;
502 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
503
504 dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
505
506 /* Enable LTSSM */
507 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
508 val |= BIT(8);
509 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
510
511 return 0;
512
513 err_disable_resources:
514 qcom_pcie_disable_resources(pcie_ep);
515
516 return ret;
517 }
518
qcom_pcie_perst_assert(struct dw_pcie * pci)519 static void qcom_pcie_perst_assert(struct dw_pcie *pci)
520 {
521 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
522
523 qcom_pcie_disable_resources(pcie_ep);
524 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
525 }
526
527 /* Common DWC controller ops */
528 static const struct dw_pcie_ops pci_ops = {
529 .link_up = qcom_pcie_dw_link_up,
530 .start_link = qcom_pcie_dw_start_link,
531 .stop_link = qcom_pcie_dw_stop_link,
532 .write_dbi2 = qcom_pcie_dw_write_dbi2,
533 };
534
qcom_pcie_ep_get_io_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)535 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
536 struct qcom_pcie_ep *pcie_ep)
537 {
538 struct device *dev = &pdev->dev;
539 struct dw_pcie *pci = &pcie_ep->pci;
540 struct device_node *syscon;
541 struct resource *res;
542 int ret;
543
544 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
545 if (IS_ERR(pcie_ep->parf))
546 return PTR_ERR(pcie_ep->parf);
547
548 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
549 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
550 if (IS_ERR(pci->dbi_base))
551 return PTR_ERR(pci->dbi_base);
552 pci->dbi_base2 = pci->dbi_base;
553
554 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
555 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
556 if (IS_ERR(pcie_ep->elbi))
557 return PTR_ERR(pcie_ep->elbi);
558
559 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
560 "mmio");
561 if (!pcie_ep->mmio_res) {
562 dev_err(dev, "Failed to get mmio resource\n");
563 return -EINVAL;
564 }
565
566 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
567 if (IS_ERR(pcie_ep->mmio))
568 return PTR_ERR(pcie_ep->mmio);
569
570 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
571 if (!syscon) {
572 dev_dbg(dev, "PERST separation not available\n");
573 return 0;
574 }
575
576 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
577 of_node_put(syscon);
578 if (IS_ERR(pcie_ep->perst_map))
579 return PTR_ERR(pcie_ep->perst_map);
580
581 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
582 1, &pcie_ep->perst_en);
583 if (ret < 0) {
584 dev_err(dev, "No Perst Enable offset in syscon\n");
585 return ret;
586 }
587
588 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
589 2, &pcie_ep->perst_sep_en);
590 if (ret < 0) {
591 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
592 return ret;
593 }
594
595 return 0;
596 }
597
qcom_pcie_ep_get_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)598 static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
599 struct qcom_pcie_ep *pcie_ep)
600 {
601 struct device *dev = &pdev->dev;
602 int ret;
603
604 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
605 if (ret) {
606 dev_err(dev, "Failed to get io resources %d\n", ret);
607 return ret;
608 }
609
610 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
611 if (pcie_ep->num_clks < 0) {
612 dev_err(dev, "Failed to get clocks\n");
613 return pcie_ep->num_clks;
614 }
615
616 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
617 if (IS_ERR(pcie_ep->core_reset))
618 return PTR_ERR(pcie_ep->core_reset);
619
620 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
621 if (IS_ERR(pcie_ep->reset))
622 return PTR_ERR(pcie_ep->reset);
623
624 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
625 if (IS_ERR(pcie_ep->wake))
626 return PTR_ERR(pcie_ep->wake);
627
628 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
629 if (IS_ERR(pcie_ep->phy))
630 ret = PTR_ERR(pcie_ep->phy);
631
632 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
633 if (IS_ERR(pcie_ep->icc_mem))
634 ret = PTR_ERR(pcie_ep->icc_mem);
635
636 return ret;
637 }
638
639 /* TODO: Notify clients about PCIe state change */
qcom_pcie_ep_global_irq_thread(int irq,void * data)640 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
641 {
642 struct qcom_pcie_ep *pcie_ep = data;
643 struct dw_pcie *pci = &pcie_ep->pci;
644 struct device *dev = pci->dev;
645 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
646 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK);
647 u32 dstate, val;
648
649 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
650 status &= mask;
651
652 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
653 dev_dbg(dev, "Received Linkdown event\n");
654 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
655 pci_epc_linkdown(pci->ep.epc);
656 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
657 dev_dbg(dev, "Received BME event. Link is enabled!\n");
658 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
659 qcom_pcie_ep_icc_update(pcie_ep);
660 pci_epc_bme_notify(pci->ep.epc);
661 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
662 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
663 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
664 val |= PARF_PM_CTRL_READY_ENTR_L23;
665 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
666 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
667 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
668 DBI_CON_STATUS_POWER_STATE_MASK;
669 dev_dbg(dev, "Received D%d state event\n", dstate);
670 if (dstate == 3) {
671 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
672 val |= PARF_PM_CTRL_REQ_EXIT_L1;
673 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
674 }
675 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
676 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
677 dw_pcie_ep_linkup(&pci->ep);
678 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
679 } else {
680 dev_err(dev, "Received unknown event: %d\n", status);
681 }
682
683 return IRQ_HANDLED;
684 }
685
qcom_pcie_ep_perst_irq_thread(int irq,void * data)686 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
687 {
688 struct qcom_pcie_ep *pcie_ep = data;
689 struct dw_pcie *pci = &pcie_ep->pci;
690 struct device *dev = pci->dev;
691 u32 perst;
692
693 perst = gpiod_get_value(pcie_ep->reset);
694 if (perst) {
695 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
696 qcom_pcie_perst_assert(pci);
697 } else {
698 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
699 qcom_pcie_perst_deassert(pci);
700 }
701
702 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
703 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
704
705 return IRQ_HANDLED;
706 }
707
qcom_pcie_ep_enable_irq_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)708 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
709 struct qcom_pcie_ep *pcie_ep)
710 {
711 int ret;
712
713 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
714 if (pcie_ep->global_irq < 0)
715 return pcie_ep->global_irq;
716
717 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
718 qcom_pcie_ep_global_irq_thread,
719 IRQF_ONESHOT,
720 "global_irq", pcie_ep);
721 if (ret) {
722 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
723 return ret;
724 }
725
726 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
727 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
728 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
729 qcom_pcie_ep_perst_irq_thread,
730 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
731 "perst_irq", pcie_ep);
732 if (ret) {
733 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
734 disable_irq(pcie_ep->global_irq);
735 return ret;
736 }
737
738 return 0;
739 }
740
qcom_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,enum pci_epc_irq_type type,u16 interrupt_num)741 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
742 enum pci_epc_irq_type type, u16 interrupt_num)
743 {
744 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
745
746 switch (type) {
747 case PCI_EPC_IRQ_LEGACY:
748 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
749 case PCI_EPC_IRQ_MSI:
750 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
751 default:
752 dev_err(pci->dev, "Unknown IRQ type\n");
753 return -EINVAL;
754 }
755 }
756
qcom_pcie_ep_link_transition_count(struct seq_file * s,void * data)757 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
758 {
759 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
760 dev_get_drvdata(s->private);
761
762 seq_printf(s, "L0s transition count: %u\n",
763 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
764
765 seq_printf(s, "L1 transition count: %u\n",
766 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
767
768 seq_printf(s, "L1.1 transition count: %u\n",
769 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
770
771 seq_printf(s, "L1.2 transition count: %u\n",
772 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
773
774 seq_printf(s, "L2 transition count: %u\n",
775 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
776
777 return 0;
778 }
779
qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep * pcie_ep)780 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
781 {
782 struct dw_pcie *pci = &pcie_ep->pci;
783
784 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
785 qcom_pcie_ep_link_transition_count);
786 }
787
788 static const struct pci_epc_features qcom_pcie_epc_features = {
789 .linkup_notifier = true,
790 .core_init_notifier = true,
791 .msi_capable = true,
792 .msix_capable = false,
793 .align = SZ_4K,
794 };
795
796 static const struct pci_epc_features *
qcom_pcie_epc_get_features(struct dw_pcie_ep * pci_ep)797 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
798 {
799 return &qcom_pcie_epc_features;
800 }
801
qcom_pcie_ep_init(struct dw_pcie_ep * ep)802 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
803 {
804 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
805 enum pci_barno bar;
806
807 for (bar = BAR_0; bar <= BAR_5; bar++)
808 dw_pcie_ep_reset_bar(pci, bar);
809 }
810
811 static const struct dw_pcie_ep_ops pci_ep_ops = {
812 .ep_init = qcom_pcie_ep_init,
813 .raise_irq = qcom_pcie_ep_raise_irq,
814 .get_features = qcom_pcie_epc_get_features,
815 };
816
qcom_pcie_ep_probe(struct platform_device * pdev)817 static int qcom_pcie_ep_probe(struct platform_device *pdev)
818 {
819 struct device *dev = &pdev->dev;
820 struct qcom_pcie_ep *pcie_ep;
821 char *name;
822 int ret;
823
824 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
825 if (!pcie_ep)
826 return -ENOMEM;
827
828 pcie_ep->pci.dev = dev;
829 pcie_ep->pci.ops = &pci_ops;
830 pcie_ep->pci.ep.ops = &pci_ep_ops;
831 pcie_ep->pci.edma.nr_irqs = 1;
832 platform_set_drvdata(pdev, pcie_ep);
833
834 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
835 if (ret)
836 return ret;
837
838 ret = qcom_pcie_enable_resources(pcie_ep);
839 if (ret) {
840 dev_err(dev, "Failed to enable resources: %d\n", ret);
841 return ret;
842 }
843
844 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
845 if (ret) {
846 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
847 goto err_disable_resources;
848 }
849
850 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
851 if (ret)
852 goto err_disable_resources;
853
854 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
855 if (!name) {
856 ret = -ENOMEM;
857 goto err_disable_irqs;
858 }
859
860 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
861 qcom_pcie_ep_init_debugfs(pcie_ep);
862
863 return 0;
864
865 err_disable_irqs:
866 disable_irq(pcie_ep->global_irq);
867 disable_irq(pcie_ep->perst_irq);
868
869 err_disable_resources:
870 qcom_pcie_disable_resources(pcie_ep);
871
872 return ret;
873 }
874
qcom_pcie_ep_remove(struct platform_device * pdev)875 static void qcom_pcie_ep_remove(struct platform_device *pdev)
876 {
877 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
878
879 disable_irq(pcie_ep->global_irq);
880 disable_irq(pcie_ep->perst_irq);
881
882 debugfs_remove_recursive(pcie_ep->debugfs);
883
884 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
885 return;
886
887 qcom_pcie_disable_resources(pcie_ep);
888 }
889
890 static const struct of_device_id qcom_pcie_ep_match[] = {
891 { .compatible = "qcom,sdx55-pcie-ep", },
892 { .compatible = "qcom,sm8450-pcie-ep", },
893 { }
894 };
895 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
896
897 static struct platform_driver qcom_pcie_ep_driver = {
898 .probe = qcom_pcie_ep_probe,
899 .remove_new = qcom_pcie_ep_remove,
900 .driver = {
901 .name = "qcom-pcie-ep",
902 .of_match_table = qcom_pcie_ep_match,
903 },
904 };
905 builtin_platform_driver(qcom_pcie_ep_driver);
906
907 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
908 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
909 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
910 MODULE_LICENSE("GPL v2");
911